JP5607175B2 - データ記憶装置及び方法 - Google Patents
データ記憶装置及び方法 Download PDFInfo
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- JP5607175B2 JP5607175B2 JP2012542249A JP2012542249A JP5607175B2 JP 5607175 B2 JP5607175 B2 JP 5607175B2 JP 2012542249 A JP2012542249 A JP 2012542249A JP 2012542249 A JP2012542249 A JP 2012542249A JP 5607175 B2 JP5607175 B2 JP 5607175B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3268—Power saving in hard disk drive
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Storage Device Security (AREA)
Description
代替的に、図7、図8及び/又は図9の例示的な処理は、1つ又は2つ以上の特定用途集積回路(ASIC)、1つ又は2つ以上のプログラマブルロジックデバイス(PLD)、1つ又は2つ以上のフィールドプログラマブルロジックデバイス(FPLD)、個別論理素子、ハードウェア、ファームウェア等のうちの1つ又は2つ以上の任意の組み合わせを使用して実施することが可能である。また、図7、図8及び/又は図9の例示的な処理は、上述の技術の1つ又は2つ以上の任意の組み合わせとして、例えば、ファームウェア、ソフトウェア、個別論理素子、及び/又はハードウェアの任意の組み合わせとして、実施することが可能である。更に、図7、図8及び図9の例示的な処理は、図7、図8及び図9のフローチャートに関して説明するが、図7、図8及び/又は図9の処理を実施する他の方法を用いることも可能である。例えば、各ブロック実行順を変更することが可能であり、及び/又は一部のブロックを変更し、削除し、分割し、又は組み合わせることが可能である。更に、図7、図8及び図9の例示的な処理の何れか又は全てを逐次に実行し、及び/又は例えば別個の処理スレッド、プロセッサ、装置、個別論理素子、回路その他により並列的に実行することが可能である。
Claims (13)
- データ記憶装置であって、
キャッシュ層と、
不揮発性データ記憶手段と、
該キャッシュ層及び該不揮発性データ記憶手段と通信可能なプロセッサであって、該不揮発性データ記憶手段に対する書き込みアクセス及び読み出しアクセスの書き込み対読み出し比に基づきキャッシュ層イネーブルラインを介して該キャッシュ層を動的にイネーブル又はディセーブルにするプロセッサと
を備えている、データ記憶装置。 - 前記読み出しアクセスの読み出しカウントを追跡するための読み出しカウンタと、前記書き込みアクセスの書き込みカウントを追跡するための書き込みカウンタとを更に備えており、前記プロセッサが、該書き込みカウント及び該読み出しカウントの書き込み対読み出し比に基づいて前記キャッシュ層を動的にイネーブル又はディセーブルにすべきときを決定する、請求項1に記載のデータ記憶装置。
- 前記プロセッサが、前記書き込み対読み出し比が所定のしきい値を超えた際に前記キャッシュ層をイネーブルにし、及び前記書き込み対読み出し比が該しきい値を下回った際に前記キャッシュ層をディセーブルにする、請求項2に記載のデータ記憶装置。
- 前記キャッシュ層イネーブルラインが前記キャッシュ層から電力をゲートオフする、請求項1ないし請求項3の何れか一項に記載のデータ記憶装置。
- 前記プロセッサ及び前記不揮発性データ記憶手段と通信可能なメモリコントローラを更に備えており、該メモリコントローラが、該不揮発性データ記憶手段に対する過去のアクセス要求を追跡する期間を追跡するためのタイマを備えており、該プロセッサが、該追跡された過去のアクセス要求を取得して、前記キャッシュ層を動的にイネーブル又はディセーブルにすべきときの決定を容易にする、請求項1ないし請求項4の何れか一項に記載のデータ記憶装置。
- 前記キャッシュ層をディセーブルにすることが、該キャッシュ層をイネーブルにする前の前記不揮発性データ記憶手段に対する複数の後続のアクセスについて該キャッシュ層をディセーブルにすることからなる、請求項1ないし請求項5の何れか一項に記載のデータ記憶装置。
- 前記後続のアクセスが複数の単一読み出しアクセスを含む、請求項6に記載のデータ記憶装置。
- 前記後続のアクセスが少なくとも1つのバーストモードアクセスを含む、請求項6に記載のデータ記憶装置。
- 前記不揮発性データ記憶手段が、単一のICダイ又は1つ若しくは2つ以上の積層ICダイからなる、請求項1ないし請求項8の何れか一項に記載のデータ記憶装置。
- 前記プロセッサが、前記不揮発性データ記憶手段と緊密に又は近接して統合された態様で提供される、請求項1ないし請求項9の何れか一項に記載のデータ記憶装置。
- 該データ記憶装置がパッケージ内に配設されており、
前記プロセッサが、該パッケージの外部の装置と交信するよう該パッケージの外部通信インタフェイスと通信可能である、請求項1ないし請求項10の何れか一項に記載のデータ記憶装置。 - 前記外部通信インタフェイスが、前記パッケージの外部の装置の様々なタイプの通信インタフェイスと通信する、請求項11に記載のデータ記憶装置。
- 複数の基板を備えたブレードサーバであって、該複数の基板の各々が、請求項1ないし請求項12の何れか一項に記載のデータ記憶装置を複数備えている、ブレードサーバ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US31174410P | 2010-03-08 | 2010-03-08 | |
US61/311,744 | 2010-03-08 | ||
PCT/US2011/027443 WO2011112523A2 (en) | 2010-03-08 | 2011-03-07 | Data storage apparatus and methods |
Publications (2)
Publication Number | Publication Date |
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JP2013512529A JP2013512529A (ja) | 2013-04-11 |
JP5607175B2 true JP5607175B2 (ja) | 2014-10-15 |
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JP2012542249A Expired - Fee Related JP5607175B2 (ja) | 2010-03-08 | 2011-03-07 | データ記憶装置及び方法 |
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Country | Link |
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US (1) | US8924645B2 (ja) |
EP (1) | EP2545452B1 (ja) |
JP (1) | JP5607175B2 (ja) |
KR (1) | KR101840238B1 (ja) |
CN (1) | CN102792289B (ja) |
WO (1) | WO2011112523A2 (ja) |
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JP2013512529A (ja) | 2013-04-11 |
EP2545452A4 (en) | 2015-01-21 |
EP2545452B1 (en) | 2017-11-29 |
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WO2011112523A2 (en) | 2011-09-15 |
EP2545452A2 (en) | 2013-01-16 |
US8924645B2 (en) | 2014-12-30 |
US20120131278A1 (en) | 2012-05-24 |
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