JP5592526B2 - 樹脂封止型半導体装置の製造方法 - Google Patents
樹脂封止型半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5592526B2 JP5592526B2 JP2013080191A JP2013080191A JP5592526B2 JP 5592526 B2 JP5592526 B2 JP 5592526B2 JP 2013080191 A JP2013080191 A JP 2013080191A JP 2013080191 A JP2013080191 A JP 2013080191A JP 5592526 B2 JP5592526 B2 JP 5592526B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- matrix substrate
- semiconductor device
- manufacturing
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
主面、前記主面に形成された複数のボンディングパッド、および前記主面とは反対側の裏面を有し、前記配線基板の前記上面に搭載された半導体チップと、
主面、および側面を有し、前記半導体チップを封止する樹脂と、を含み、
前記配線基板の前記上面および前記樹脂の前記主面のそれぞれは、四角形であり、
前記樹脂の各側面は、前記配線基板の各側面とそれぞれ面一であり、
前記複数の第1パッドのそれぞれは、前記第1ソルダレジストから露出しており、
前記複数の第2パッドのそれぞれと前記インデックスパターンとは、前記第2ソルダレジストから露出しており、
前記アドレス情報パターンは、前記第2ソルダレジストで覆われている。
図1、図2は、本実施形態の樹脂封止型半導体装置の製造に用いるマトリクス基板の一部を拡大して示す図であり、図1はそのチップ搭載面(上面)、図2は実装面(下面)をそれぞれ示している。
前記実施の形態1では、配線材料を使ってマトリクス基板1Aの実装面にアドレス情報パターン8を形成したが、これに限定されるものではなく、例えば次のような方法でアドレス情報パターン8を形成することもできる。
2 パッド
3 アライメントターゲット
4 パッド
5 配線
6 アライメントターゲット
7 インデックスパターン
8 アドレス情報パターン
9 ソルダレジスト
11 ガイドホール
12 半導体チップ
13 ワイヤ
14 樹脂
15 金型
15a 上型
15b 下型
16 スリット
17 半田バンプ
18 アライメントターゲット
19 マーク
20 樹脂封止型半導体装置
BP ボンディングパッド
Claims (2)
- 以下の工程を含む樹脂封止型半導体装置の製造方法:
(a)上面と、前記上面に形成された複数のパッドと、前記上面に形成されたアライメントターゲットと、前記アライメントターゲットを覆うように前記上面上に形成されたソルダレジストと、前記上面とは反対側の下面と、を有する配線基板を準備する工程;
(b)主面、前記主面に形成された複数のボンディングパッド、および前記主面とは反対側の裏面を有する半導体チップを、前記半導体チップの前記裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面上に搭載する工程;
(c)前記半導体チップの前記複数のボンディングパッドと前記配線基板の前記複数のパッドとを、複数のワイヤを介してそれぞれ電気的に接続する工程;
(d)前記半導体チップおよび前記複数のワイヤを樹脂で封止する工程;
ここで、
前記アライメントターゲットは、平面視において、前記配線基板の前記複数のパッドで囲まれる領域内に設けられており、
前記(b)工程では、前記アライメントターゲットを認識して前記配線基板に対する前記半導体チップの位置合わせを行ってから、前記アライメントターゲット上に前記半導体チップを搭載する。 - 前記アライメントターゲットは、前記配線基板の前記上面に複数個形成されており、
複数の前記アライメントターゲットは、平面視において、前記配線基板の前記複数のパッドで囲まれる領域内に設けられている、請求項1に記載の樹脂封止型半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013080191A JP5592526B2 (ja) | 2013-04-08 | 2013-04-08 | 樹脂封止型半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013080191A JP5592526B2 (ja) | 2013-04-08 | 2013-04-08 | 樹脂封止型半導体装置の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012005939A Division JP5444382B2 (ja) | 2012-01-16 | 2012-01-16 | 樹脂封止型半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014051375A Division JP2014132682A (ja) | 2014-03-14 | 2014-03-14 | 樹脂封止型半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013138263A JP2013138263A (ja) | 2013-07-11 |
JP5592526B2 true JP5592526B2 (ja) | 2014-09-17 |
Family
ID=48913667
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013080191A Expired - Lifetime JP5592526B2 (ja) | 2013-04-08 | 2013-04-08 | 樹脂封止型半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5592526B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020047836A (ja) | 2018-09-20 | 2020-03-26 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02253649A (ja) * | 1989-03-27 | 1990-10-12 | Nec Kyushu Ltd | 半導体装置用リードフレーム |
JPH065729A (ja) * | 1992-06-17 | 1994-01-14 | Sony Corp | プリント配線板および半導体素子の位置合わせ方法 |
JPH06104315A (ja) * | 1992-09-18 | 1994-04-15 | Fujitsu Ltd | 半導体パッケージとその製造方法 |
EP1213754A3 (en) * | 1994-03-18 | 2005-05-25 | Hitachi Chemical Co., Ltd. | Fabrication process of semiconductor package and semiconductor package |
JPH08111475A (ja) * | 1994-10-12 | 1996-04-30 | Sony Corp | 基台およびこれを用いた半導体装置の製造方法 |
JPH11274357A (ja) * | 1998-03-20 | 1999-10-08 | Sony Corp | 電子部品の分割方法および分割装置 |
JP3827497B2 (ja) * | 1999-11-29 | 2006-09-27 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
-
2013
- 2013-04-08 JP JP2013080191A patent/JP5592526B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2013138263A (ja) | 2013-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3827497B2 (ja) | 半導体装置の製造方法 | |
US20020180040A1 (en) | Super thin/super thermal ball grid array package | |
JP2000200859A (ja) | チップサイズ半導体パッケ―ジ及びその集合体並びにその製造方法 | |
JP2005322921A (ja) | バンプテストのためのフリップチップ半導体パッケージ及びその製造方法 | |
JP2995264B2 (ja) | 半導体パッケージ用印刷回路基板ストリップ及びこの基板ストリップの不良印刷回路基板ユニット表示方法 | |
JP3074264B2 (ja) | 半導体装置及びその製造方法及びリードフレーム及びその製造方法 | |
JP4948035B2 (ja) | 樹脂封止型半導体装置の製造方法 | |
JP2012129452A (ja) | 半導体装置、半導体パッケージおよび半導体装置の製造方法 | |
KR100829613B1 (ko) | 반도체 칩 패키지 및 그 제조 방법 | |
JP5592526B2 (ja) | 樹脂封止型半導体装置の製造方法 | |
JP2000040676A (ja) | 半導体装置の製造方法 | |
JP5308464B2 (ja) | 半導体装置の製造方法 | |
KR101015267B1 (ko) | 가용 영역이 최대화된 집적 회로 패키지용 스트립 | |
JP5885332B2 (ja) | 半導体装置の製造方法 | |
JP5444382B2 (ja) | 樹脂封止型半導体装置 | |
JP4889359B2 (ja) | 電子装置 | |
JP2007173606A (ja) | 電子装置及びその製造方法 | |
JP2015097297A (ja) | 樹脂封止型半導体装置およびその製造方法 | |
JP2014132682A (ja) | 樹脂封止型半導体装置の製造方法 | |
KR20110137060A (ko) | 반도체 패키지 | |
KR20080084075A (ko) | 적층 반도체 패키지 | |
TW202312405A (zh) | 引線框架、半導體裝置、檢查方法及引線框架的製造方法 | |
KR100900229B1 (ko) | Fbga 패키지 | |
JP2004172647A (ja) | 半導体装置 | |
KR20060075431A (ko) | Fbga 패키지의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130408 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140108 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140114 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140314 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140408 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140604 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140708 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140731 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5592526 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
EXPY | Cancellation because of completion of term |