JP5584986B2 - Interposer - Google Patents
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- JP5584986B2 JP5584986B2 JP2009073126A JP2009073126A JP5584986B2 JP 5584986 B2 JP5584986 B2 JP 5584986B2 JP 2009073126 A JP2009073126 A JP 2009073126A JP 2009073126 A JP2009073126 A JP 2009073126A JP 5584986 B2 JP5584986 B2 JP 5584986B2
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Description
本発明は、二つの電子部材間に介在して両者を機械的、電気的に接続するインターポーザに関する。 The present invention relates to an interposer that is interposed between two electronic members and mechanically and electrically connects them.
近年、電子機器の高性能化、小型化が急速に進展している。これに伴い、電子機器を構成する半導体素子及びこれを実装するための配線基板には、小型薄型であること、高い機能を有すること、また高い信頼性を有することなどが要求されている。 In recent years, high performance and miniaturization of electronic devices are rapidly progressing. Along with this, a semiconductor element constituting an electronic device and a wiring board for mounting the semiconductor element are required to be small and thin, to have high functions, and to have high reliability.
このような要求に応えるべく、半導体素子の実装方法として、プリント基板上に半導体素子を直接実装するベアチップ実装技術が用いられるようになった。他方半導体素子の多ピン化に伴い、半導体素子を実装するための配線基板として、配線層を多層化した、樹脂材料、あるいはセラミックス材料の多層配線基板の重要性が高まっている。例えば、半導体素子をテストするためのテスター用ボード（プローブカード）においては、テストピンの多数化、高密度化などにより配線層の更なる多層化が必要不可欠の状況となっていて、多層配線基板としては、絶縁層と導体層とが交互に積層された微細配線がコア基材の片面または両面に形成されたビルトアップ方式のものや、低熱膨張係数のセラミックスを絶縁材料に用いたものなどが開発されてきた。 In order to meet such demands, a bare chip mounting technique in which a semiconductor element is directly mounted on a printed board has been used as a method for mounting a semiconductor element. On the other hand, as the number of pins of a semiconductor element increases, the importance of a multilayer wiring board made of a resin material or a ceramic material in which a wiring layer is multilayered is increasing as a wiring board for mounting a semiconductor element. For example, in a tester board (probe card) for testing a semiconductor element, it is indispensable to further increase the number of wiring layers by increasing the number of test pins and increasing the density. For example, there are built-up types in which fine wiring with alternating layers of insulating layers and conductor layers formed on one or both sides of the core substrate, and those using ceramics with a low thermal expansion coefficient as the insulating material. Has been developed.
樹脂膜と金属膜を積層して作製するビルドアップ方式などの多層配線基板においては、基板自体の軽量化や熱膨張係数の低減化を目的に、そのコア基材として、炭素系繊維（織布）をバインダ用有機高分子樹脂で固化した導電性基材、あるいはその積層体、また繊維強化金属、軽量かつ化学的に安定した金属板などを用いる提案もなされている。 In multilayer wiring boards such as build-up systems that are manufactured by laminating resin films and metal films, carbon-based fibers (woven fabrics) are used as the core substrate for the purpose of reducing the weight of the board itself and reducing the thermal expansion coefficient. ) Is solidified with an organic polymer resin for a binder, or a laminate thereof, a fiber reinforced metal, a lightweight and chemically stable metal plate, and the like have also been proposed.
ところで、ベアチップ実装においては、シリコンチップが、多用されるプリント基板の一つであるガラスエポキシ樹脂ベースの基板上またはセラミック基板などに直接実装される場合、シリコンチップの熱膨張係数は約３．５ｐｐｍ／℃であるのに対し、ガラスエポキシ樹脂ベースの基板のそれは約１２〜２０ｐｐｍ／℃、典型的には１７ｐｐｍ／℃前後、セラミック基板のそれは５〜１２ｐｐｍ／℃となっている。 By the way, in bare chip mounting, when a silicon chip is directly mounted on a glass epoxy resin-based substrate, which is one of the frequently used printed boards, or a ceramic substrate, the thermal expansion coefficient of the silicon chip is about 3.5 ppm. Whereas glass / epoxy resin based substrates are about 12-20 ppm / ° C., typically around 17 ppm / ° C., and ceramic substrates are 5-12 ppm / ° C.
シリコンチップをガラスエポキシ樹脂基板に搭載するとき、上記のような熱膨張係数の大きな違いから、これに起因する両者間の応力歪で、疲労破壊、断線などが発生しやすく、これを防止するために、実装される基板の熱膨張係数を低減すし、シリコンのそれに近づける必要がある。 When mounting a silicon chip on a glass epoxy resin substrate, due to the large difference in coefficient of thermal expansion as described above, the stress strain between them tends to cause fatigue failure, disconnection, etc. In addition, it is necessary to reduce the thermal expansion coefficient of the substrate to be mounted and to approximate it to that of silicon.
一方シリコンチップをセラミック基板上に実装する場合、この例としてセラミックパッケージに半導体チップを搭載して、パッケージ化された半導体モジュールを形成することに相当するが、装置化実装のためにはこの半導体モジュールを、さらに装置用のマザーボードに搭載する工程が必然的に生じる。マザーボードは通常ガラスエポキシ樹脂基板よりなるプリント基板を用いるため、上記の熱膨張係数の差、つまり、セラミック基板の５〜１２ｐｐｍ／℃とガラスエポキシ樹脂基板の１７ｐｐｍ／℃前後といった熱膨張係数差が生じ、このために実装後のインターコネクションに応力が集中してしまい、断線に至るケースがある。 On the other hand, when a silicon chip is mounted on a ceramic substrate, this corresponds to forming a packaged semiconductor module by mounting a semiconductor chip on a ceramic package as an example. Is further inevitably generated on the motherboard for the device. Since the motherboard usually uses a printed circuit board made of a glass epoxy resin substrate, the difference in thermal expansion coefficient described above, that is, a thermal expansion coefficient difference of 5-12 ppm / ° C. of the ceramic substrate and about 17 ppm / ° C. of the glass epoxy resin substrate occurs. For this reason, there is a case where stress is concentrated on the interconnection after mounting, resulting in disconnection.
前述のプローブカードに関し、図９に模式的な構成を示す。図にあるように、プローブカード１０１は、プリント基板であるメイン基板１０２上に、セラミック基板であるスペーストランスフォーマ（ＳＴ）１０３が搭載され、このスペーストランスフォーマ（ＳＴ）１０３は多層配線セラミック基板とそれに取り付けられた多数のピン（プローブ針）１０４からなっている。この構成においても、やはりメイン基板１０２であるプリント基板上へのスペーストランスフォーマ（ＳＴ）１０３であるセラミック基板の搭載によって生じる熱膨張係数の差による接合境界面の応力集中が大きな問題となる。 A schematic configuration of the probe card is shown in FIG. As shown in the figure, a probe card 101 has a space transformer (ST) 103, which is a ceramic substrate, mounted on a main substrate 102, which is a printed circuit board. The space transformer (ST) 103 is attached to a multilayer wiring ceramic substrate. It consists of a large number of pins (probe needles) 104 formed. Even in this configuration, the stress concentration at the joint interface due to the difference in thermal expansion coefficient caused by mounting the ceramic substrate, which is the space transformer (ST) 103, on the printed circuit board, which is the main substrate 102, becomes a big problem.
この接合に、例えば樹脂を用いて接着する方法がある。しかし加熱処理を伴い、張り合わせ後に、熱膨張係数の差でメイン基板に反りが発生する。また例えば、セラミック基板をプリント基板にＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｌｌａｙ；ボールグリッドアレイ）実装する方法がある。しかしこの場合も熱膨張係数の差から、はんだボール接続部に応力が集中し断線につながる。 For this bonding, for example, there is a method of bonding using a resin. However, with the heat treatment, after bonding, the main substrate is warped due to the difference in thermal expansion coefficient. For example, there is a method of mounting a ceramic substrate on a printed circuit board by BGA (Ball Grid Array). However, in this case as well, due to the difference in thermal expansion coefficient, stress concentrates on the solder ball connection portion, leading to disconnection.
こういった背景から、両基板のインターコネクションをポゴピンなどを用いて行うことが考えられ、これならば接点境界での応力集中は避けられる。しかし、これは点ないし面接触による電気的接合であり不安定であるという問題を有する。確実な金属同士の結合を伴う接続方法が基本的に望ましく、多くはこの境界面をはんだ接合などによる結合方法が実施されている。こういった、はんだ接合などの接続方式での信頼性向上が必要不可欠となっている。 From such a background, it is conceivable to perform interconnection between both substrates using pogo pins or the like, and in this case, stress concentration at the contact boundary can be avoided. However, this is an electrical connection by point or surface contact and has the problem of being unstable. Basically, a connection method involving reliable metal-to-metal bonding is desirable, and in many cases, a bonding method using solder bonding or the like is performed on this boundary surface. It is essential to improve the reliability of such connection methods such as soldering.
そこで、本発明の課題は、熱膨張係数の異なる基板などの電子部材間に介在し、実質的にその熱膨張係数の差を埋めるように働いて、両部材と基板との接続個所においても応力発生が抑制されるような接続が実現できるインターポーザを提供することにある。 Therefore, an object of the present invention is to intervene between electronic members such as substrates having different thermal expansion coefficients and work to substantially fill the difference in the thermal expansion coefficients, so that stress is also applied at the connection point between both members and the substrate. An object of the present invention is to provide an interposer that can realize a connection in which generation is suppressed.
本発明のインターポーザは、
互いに異なる熱膨張率を有する二つの部材間に介在して接続するインターポーザであって、前記インターポーザは、
導電性基材と、
前記導電性基材上の第１面側絶縁層及び第２面側絶縁層と、
前記両絶縁層上に形成された第１面側導体層及び第２面側導体層と、
前記両絶縁層を含んで前記導電性基材を貫通する複数の貫通孔と、
前記貫通孔中を、前記導電性基材に絶縁して、前記第１面側導体層と前記第２面側導体層とを電気的に接続する導電ビアとを有し、
第１面側開口径は第２面側開口径より小さく、
前記第１面側導体層に接続する前記部材の熱膨張係数は、前記第２面側導体層に接続する前記部材の熱膨張係数より小さく、かつ前記導電性基材の熱膨張係数よりも大きいことを特徴とするインターポーザ。
ことを特徴とする。
The interposer of the present invention
A interposer for connecting interposed between the two parts materials having different thermal expansion coefficients from one another, the interposer,
A conductive substrate;
A first surface side insulating layer and a second surface side insulating layer on the conductive substrate;
A first surface side conductor layer and a second surface side conductor layer formed on the both insulating layers;
A plurality of through holes including both the insulating layers and penetrating through the conductive substrate;
Insulating the inside of the through hole with the conductive base material, and having a conductive via that electrically connects the first surface side conductor layer and the second surface side conductor layer,
The first surface side opening diameter is smaller than the second surface side opening diameter,
The thermal expansion coefficient of the member connected to the first surface side conductor layer is smaller than the thermal expansion coefficient of the member connected to the second surface side conductor layer and larger than the thermal expansion coefficient of the conductive base material. Interposer characterized by that .
It is characterized by that.
本発明のインターポーザは、第１面側と第２面側の開口径を適宜変えることで、各面側での実効的な熱膨張係数を各面に接続する材料の熱膨張係数に適合するように設計可能でもあり、比較的簡単な方法で作製可能といった特徴を持つ。 The interposer of the present invention, by changing the opening diameter of the first surface side and the second surface side as appropriate, adapted to the thermal expansion coefficient of the effective to connect the thermal expansion coefficient of each surface wood charge on each surface side It can be designed as such, and can be manufactured by a relatively simple method.
以下に、本発明の実施の形態を、添付図を参照しつつ説明する。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
（本発明のインターポーザの基本的な構成）
先ず、本発明のインターポーザの基本的な構成について説明する。
(Basic configuration of the interposer of the present invention)
First, the basic configuration of the interposer of the present invention will be described.
前述のように、特に、互いに大きく熱膨張係数の異なる、電子部材同士、例えば、半導体チップやセラミック基板とプリント基板とを直接接合することや、はんだ（ボール）などを介して金属接合すると大きな応力がその接合界面に発生し、断線などの大きな障害が発生することを述べた。 As described above, particularly when electronic members having large thermal expansion coefficients differ from each other, for example, directly joining a semiconductor chip or a ceramic substrate and a printed board, or metal joining via solder (ball) or the like, a large stress is caused. He said that it occurs at the joint interface and causes a major failure such as disconnection.
その応力の発生を抑制する理想的な解決策の一つとして、例えば、熱膨張係数が異なるＡ、Ｂ二つの電子部材の間に、両電子部材が接する中間的な緩衝基材を設け、この緩衝基材における一方の面（例えば、表面）側の熱膨張係数を電子部材Ａの熱膨張係数と同等とし、同じ緩衝基材における他方の面（例えば、裏面）側の熱膨張係数を電子部材Ｂの熱膨張係数と同等とし、電子部材Ａをこの緩衝基材の表面側に、電子部材Ｂをこの緩衝基材の裏面側に機械的に接着させる方法が考えられる。こうすることで、Ａ、Ｂ二つの電子部材はその緩衝基材との接合面で応力の発生は抑制できる。 As one of the ideal solutions to suppress the generation of the stress, for example, an intermediate buffer base material in which both electronic members are in contact is provided between two electronic members A and B having different thermal expansion coefficients. The thermal expansion coefficient on one side (for example, the front surface) side of the buffer base material is made equal to the thermal expansion coefficient of the electronic member A, and the thermal expansion coefficient on the other side (for example, the back surface) side of the same buffer base material is set to the electronic member. A method is conceivable in which the electronic member A is mechanically bonded to the front surface side of the buffer base material and the electronic member B is mechanically bonded to the back surface side of the buffer base material with the same thermal expansion coefficient as B. By carrying out like this, generation | occurrence | production of stress can be suppressed by the joint surface with the buffer base material of the two electronic members of A and B.
このような特徴を有する中間的な緩衝基材、すなわちインターポーザとして、例えば熱膨張係数の異なる材料を大きいものから小さいものへと順に多層に積層し、インターポーザ内部で、実効的に徐々に、一方の電子部材の熱膨張係数に同等のものから他方のそれになるようにする方法が想定される。しかし、実際には、各段階で要求される熱膨張係数に適した積層材料を準備し、それらを順に積み上げるということは、自ずから限界があって、技術的に非常に困難である。 As an intermediate buffer base material having such characteristics, that is, an interposer, for example, materials having different thermal expansion coefficients are laminated in multiple layers in order from large to small, and one of the layers is effectively gradually and gradually inside the interposer. A method is envisaged in which the thermal expansion coefficient of the electronic member is equal to that of the other one. However, in practice, it is technically very difficult to prepare laminated materials suitable for the thermal expansion coefficient required in each stage and to stack them in order because of their limitations.
われわれは、種々検討の結果、こういった特性を実効的に実現する、以下のような本発明に係るインターポーザを考え出すに至った。 As a result of various studies, we have come up with the following interposer according to the present invention that effectively realizes these characteristics.
例えば、小さな熱膨張係数を有する平板状基材に、適切なピッチで適切な開口径を持つ開口部を複数形成し、さらに、それと異なる開口径を有する開口平板状基材を複数作成し、それぞれの実効的な熱膨張係数を測定すると、大きい開口径を有する平板状基材ほど熱膨張係数が大きくなる。 For example, a plurality of openings having an appropriate opening diameter at an appropriate pitch are formed on a flat substrate having a small thermal expansion coefficient, and a plurality of opening flat substrates having an opening diameter different from that are formed. When the effective thermal expansion coefficient is measured, the thermal expansion coefficient of the flat substrate having a larger opening diameter increases.
以下にその実験結果を示す。先ず、平板状基材として用いたのは、非常に軽量かつ低熱膨張係数を有した、通常、ビルドアップ型の多層配線基板の導電性コア基材として用いられる、カーボンファイバ織布とエポキシ樹脂からなる材料を用いた基材である。 The experimental results are shown below. First, the flat base material used was a carbon fiber woven fabric and an epoxy resin, which are very lightweight and have a low thermal expansion coefficient, and are usually used as a conductive core base material for build-up type multilayer wiring boards. It is the base material using the material which becomes.
その基材は、その先ず、０．２ｍｍ厚の、カーボンファイバ織布シートとエポキシ系樹脂組成物とを複合化して作製したプリプレグを５枚と、０．１ｍｍ厚のガラス/エポキシプリプレグをその外側に１枚づつ積層し、さらに圧着して厚さ約１．２ｍｍの平板状基材とした。カーボンファイバ織布シートを包容するエポキシ系樹脂組成物には、組成物全体の１０ｗｔ％のシリカフィラーを混合した。このような材料により構成された基材は、温度範囲２５〜２００℃において、面方向の平均熱膨張係数が、２ｐｐｍ／℃であった。 The base material is composed of five prepregs prepared by combining a carbon fiber woven sheet and an epoxy resin composition having a thickness of 0.2 mm, and a glass / epoxy prepreg having a thickness of 0.1 mm on the outside. One by one was laminated and further pressed to form a flat substrate having a thickness of about 1.2 mm. The epoxy resin composition enclosing the carbon fiber woven fabric sheet was mixed with 10 wt% silica filler of the entire composition. The base material made of such a material had an average coefficient of thermal expansion in the plane direction of 2 ppm / ° C. in the temperature range of 25 to 200 ° C.
この平板基材を用い、１．０ｍｍピッチ、開口径０．２、０．４、０．６、０．８ｍｍで複数開口された基材をそれぞれ作製し、各々の実効的な熱膨張係数（ＣＴＥ；Ｃｏｅｆｆｉｃｉｅｎｔ ｏｆ Ｔｈｅｒｍａｌ Ｅｘｐａｎｓｉｏｎ）を測定した結果を、図１に示す。ここで横軸は測定基板の開口径（Ｈｏｌｅ Ｄｉａｍｅｔｅｒ）（ｍｍ）、縦軸はＣＴＥ（ｐｐｍ／Ｋ）である。いずれも各開口のピッチは１．０ｍｍである。この結果から解るように、０．２ｍｍ開口径では、熱膨張係数は、約２ｐｐｍ／Ｋで、この値は開口部が形成されて無い平板基材の熱膨張係数とほぼ同じである。他方開口径が大きくなると、この場合、ほぼ直線的に熱膨張係数が増加し、０．４ｍｍ開口径で熱膨張係数は約４ｐｐｍ／Ｋ、０．８ｍｍ開口径で熱膨張係数は約１６ｐｐｍ／Ｋとなった。 Using this flat plate base material, each base material having a plurality of openings with a pitch of 1.0 mm, an opening diameter of 0.2, 0.4, 0.6, and 0.8 mm was prepared, and each effective thermal expansion coefficient ( The result of measuring CTE (Coefficient of Thermal Expansion) is shown in FIG. Here, the horizontal axis represents the opening diameter (Hole Diameter) (mm) of the measurement substrate, and the vertical axis represents CTE (ppm / K). In any case, the pitch of each opening is 1.0 mm. As can be seen from this result, when the opening diameter is 0.2 mm, the thermal expansion coefficient is about 2 ppm / K, which is almost the same as the thermal expansion coefficient of the flat plate base material having no opening. On the other hand, as the opening diameter increases, the thermal expansion coefficient increases almost linearly in this case, with a 0.4 mm opening diameter, the thermal expansion coefficient is about 4 ppm / K, and with a 0.8 mm opening diameter, the thermal expansion coefficient is about 16 ppm / K. It became.
この結果から、図２に示すような、断面形状を有するインターポーザを用いることで、表裏各面側の熱膨張係数がそれぞれ異なる、あるいは図１で示されるよう熱膨張係数の変化の範囲で、表裏各面側の熱膨張係数を設計可能とするインターポーザを作製できると想定される。 From this result, by using an interposer having a cross-sectional shape as shown in FIG. 2, the thermal expansion coefficient on each side of the front and back surfaces is different, or within the range of change in the thermal expansion coefficient as shown in FIG. It is assumed that an interposer capable of designing the thermal expansion coefficient on each side can be produced.
図２は、本発明のインターポーザの例の断面模式図を示す。ここにおいて、それぞれ、（１）テーパー形状の開口部断面をもつ基材（テーパー形状開口部基材）を用いた例と、（２）階段状の開口部断面をもつ基材（階段形状開口部基材）を用いた例を示し、いずれも、インターポーザ１は、基材２の表面側（図中の上側）、裏面側（同下側）に、絶縁層３が形成されている。この絶縁層３を含む基材２を表裏貫通する開口部４が、同一ピッチで形成されている。また両者とも、表面側（上側）の開口径が裏面側（下側）の開口径よりも小さい径としている。図示されている様に、（１）テーパー形状開口部基材では、開口部４の断面において、開口径変化がテーパー状に下に向かって大に変わる台形（立体形状では下に大の円錐柱）ある。他方（２）階段形状開口部基材では、開口部４の断面において、開口径変化が下に大の階段状（立体形状では下に大の階段状円柱）となっている。そしていずれも、開口部４の中を基材２に接触しないでビア５が上下に絶縁層３上の電極６に接続形成され、開口部４中のクリアランス部分は、絶縁樹脂７が充填される。 FIG. 2 shows a schematic cross-sectional view of an example of the interposer of the present invention. Here, (1) an example using a base material having a taper-shaped opening section (taper-shaped opening base material), and (2) a base material having a step-shaped opening section (stair-shaped opening section), respectively. In each case, the interposer 1 has an insulating layer 3 formed on the front surface side (upper side in the drawing) and the rear surface side (lower side) of the base material 2. Openings 4 penetrating the base material 2 including the insulating layer 3 are formed at the same pitch. In both cases, the opening diameter on the front surface side (upper side) is smaller than the opening diameter on the back surface side (lower side). As shown in the figure, (1) in the tapered opening base material, in the cross section of the opening 4, the trapezoidal shape in which the change in the opening diameter greatly changes downward in a tapered shape (in the three-dimensional shape, a large conical column on the bottom) )is there. On the other hand, in the (2) staircase-shaped opening base material, in the cross section of the opening 4, the change in the opening diameter is a large staircase downward (in the three-dimensional shape, a large staircase-shaped cylinder is downward). In either case, the via 5 is connected to the electrode 6 on the insulating layer 3 vertically without contacting the substrate 2 in the opening 4, and the clearance portion in the opening 4 is filled with the insulating resin 7. .
このようなインターポーザの構成により、図１の結果から、表面側（上側）における実効的な熱膨張係数は、基材２の熱膨張係数と同じないしはそれ以上の値を持ち、裏面側（下側）における実効的な熱膨張係数は、より開口径が大きいことから、表面側の熱膨張係数より大きい値の熱膨張係数を有するインターポーザを形成することが可能となる。 With the configuration of such an interposer, the effective thermal expansion coefficient on the front surface side (upper side) has the same or higher value as the thermal expansion coefficient of the base material 2 from the result of FIG. Since the effective thermal expansion coefficient in (2) has a larger opening diameter, it is possible to form an interposer having a thermal expansion coefficient larger than the thermal expansion coefficient on the surface side.
（実施例の形成工程）
本発明のインターポーザの作製工程を図３〜５の断面模式図によって説明する。
(Formation process of Example)
The manufacturing process of the interposer of this invention is demonstrated with the cross-sectional schematic diagram of FIGS.
図３（１）に示す様に、０．２ｍｍ厚のカーボンファイバ織布シートとエポキシ系樹脂組成物とを複合化した（ＣＦＲＰ；Ｃａｒｂｏｎ Ｆｉｂｅｒ Ｒｅｉｎｆｏｒｃｅｄ Ｐｌａｓｔｉｃｓ、炭素繊維強化プラスティック）ものである、導電性を有するカーボン／エポキシプリプレグ８を５枚と、その外側に絶縁性である、０．１ｍｍ厚のガラス／エポキシプリプレグ９を1枚ずつ、計２枚をレイアップする。カーボンファイバ織布シートを包含するエポキシ系樹脂組成物には、組成物全体の１０ｗｔ％のシリカフェラーを混合した。 As shown in FIG. 3 (1), a 0.2 mm thick carbon fiber woven fabric sheet and an epoxy resin composition are combined (CFRP; Carbon Fiber Reinforced Plastics, carbon fiber reinforced plastic). A total of two carbon / epoxy prepregs 8 each having a thickness of 1 and a glass / epoxy prepreg 9 having a thickness of 0.1 mm, which is insulative, are laid up. The epoxy resin composition including the carbon fiber woven fabric sheet was mixed with 10 wt% silica feller of the entire composition.
図３（２）に示す様に、レイアップしたプリプレグを真空プレス装置を用いて圧着し、厚さ約１．２ｍｍの、外側が絶縁性、内部が導電性を有する平板状の基材１０を形成する。作製した基材１０は、温度範囲２５〜２００℃の範囲で、面方向の平均熱膨張係数が、２ｐｐｍ／℃であった。なお、さきに図１で示した結果を得るのに用いた基材も、これと同様に作製された基材である。 As shown in FIG. 3 (2), the laid-up prepreg is pressure-bonded by using a vacuum press apparatus, and a flat substrate 10 having a thickness of about 1.2 mm and having an outer insulating property and an inner conductive property is obtained. Form. The produced base material 10 had a temperature range of 25 to 200 ° C. and an average coefficient of thermal expansion in the plane direction of 2 ppm / ° C. The base material used to obtain the result shown in FIG. 1 is also a base material manufactured in the same manner.
次に、図３（３）に示す様に、基材１０の表面側（図の上側）より、それぞれ、１．００ｍｍピッチの位置に０．４ｍｍ径のドリルを用いて貫通孔加工を行い、細径貫通孔１１を形成する。 Next, as shown in FIG. 3 (3), from the surface side of the base material 10 (upper side in the drawing), through holes are drilled at a position of 1.00 mm pitch using a 0.4 mm diameter drill, A small-diameter through hole 11 is formed.
そして、図３（４）に示す様に、再度、表面側より、基材１０面上に同じピッチ位置に０．６ｍｍ径のドリルを用いて、表面より０．８ｍｍの深さまで加工し、中間径加工孔１２を形成する。 Then, as shown in FIG. 3 (4), from the surface side again, using a 0.6 mm diameter drill at the same pitch position on the surface of the base material 10, it is processed to a depth of 0.8 mm from the surface. A diameter machining hole 12 is formed.
そして、図３（５）に示す様に、更に、表面側より、基材１０面上に同じピッチ位置に０．８ｍｍ径のドリルを用いて、表面より、０．４ｍｍの深さまで加工し、大径加工孔１３を形成する。こうして、表面側から裏面側に向かって、ステップ状に開口径が小さくなっている、三段階開口部１４を形成する。 Then, as shown in FIG. 3 (5), from the surface side, using a 0.8mm diameter drill at the same pitch position on the surface of the base material 10, it is processed to a depth of 0.4mm from the surface, A large-diameter hole 13 is formed. In this way, the three-stage opening 14 having an opening diameter that decreases in a stepped manner from the front surface side to the back surface side is formed.
次に、図４（６）に示す様に、それぞれの三段階開口部１４内に絶縁樹脂１５を充填する。絶縁樹脂はエポキシ樹脂を用い、これにシリカフィラーを４０ｗｔ％添加した。これを真空印刷機によってスクリーン印刷をして三段階開口部１４内に充填し、高温槽内１８０℃で硬化させる。その後、開口部から基材１０の上下に突出している絶縁樹脂部分をバフ研磨機によって研磨し、樹脂充填面を表面および裏面とフラットになるようにする。 Next, as shown in FIG. 4 (6), the insulating resin 15 is filled in each of the three-stage openings 14. As the insulating resin, an epoxy resin was used, and 40 wt% of silica filler was added thereto. This is screen-printed by a vacuum printer, filled into the three-stage opening 14 and cured at 180 ° C. in a high-temperature tank. Thereafter, the insulating resin portions projecting up and down of the base material 10 from the opening are polished by a buffing machine so that the resin-filled surface becomes flat with the front surface and the back surface.
そして、図４（７）に示すように、絶縁樹脂１５が充填された三段階開口部１４の中心位置にスルーホール１６を形成する。このスルーホール加工は、０．２ｍｍ径のドリルを用いて貫通孔を開口をした。 Then, as shown in FIG. 4 (7), a through hole 16 is formed at the center position of the three-stage opening 14 filled with the insulating resin 15. In this through hole processing, a through hole was opened using a drill having a diameter of 0.2 mm.
次いで、図４（８）に示す様に、基材１０の表面・裏面及びスルーホール１６内に、０．５μｍ厚の無電界銅めっき膜１７を形成し、これをシード層として、図４（９）に示す様に、スルーホール１６内で２０μｍ厚になるように、電解銅めっき膜１８を成膜する。こうして、三段階開口部１４内において、導電性の基材１０を貫通し、かつ、絶縁樹脂１５によるクレアランスを有して基材１０と絶縁されている円筒状の導電性のビア１９が形成される。この場合、ビア１９内に電解銅めっき膜１８で満たされないビア空洞部２０が残っていることになる。 Next, as shown in FIG. 4 (8), an electroless copper plating film 17 having a thickness of 0.5 μm is formed in the front and back surfaces of the substrate 10 and in the through holes 16, and this is used as a seed layer. As shown in 9), an electrolytic copper plating film 18 is formed so as to have a thickness of 20 μm in the through hole 16. Thus, a cylindrical conductive via 19 is formed in the three-stage opening 14 that penetrates the conductive base material 10 and has a clearance by the insulating resin 15 and is insulated from the base material 10. Is done. In this case, the via cavity 20 that is not filled with the electrolytic copper plating film 18 remains in the via 19.
そのために、先に三段階開口部１４中に絶縁樹脂１５を充填した工程と同様に、同じ樹脂と形成法を用いて、図５（１０）に示す様にビア空洞部２０中に、スクリーン印刷で絶縁樹脂２１を充填し、そして加熱して硬化し、図５（１１）に示す様に、研磨によって突出樹脂分を除去することで、ビア空洞部２０中の絶縁樹脂２１が表裏面とフラットになるように充填される。 Therefore, in the same manner as in the process of filling the insulating resin 15 in the three-stage opening 14, the screen printing is performed in the via cavity 20 as shown in FIG. The insulating resin 21 is filled with, and heated and cured, and as shown in FIG. 5 (11), the protruding resin is removed by polishing so that the insulating resin 21 in the via cavity 20 is flat with the front and back surfaces. It is filled to become.
以降、基材の表面側および裏面側に露出する各ビア１９に電極パッドを形成する工程を実施する。図５（１２）に示す様に、基材１０の表・裏面に０．５μｍ厚の無電界銅めっき膜２２を成膜後、図５（１３）に示す様に、基材１０の表・裏面に２０μｍ厚の電界銅めっき膜２３を成膜する。 Thereafter, a process of forming an electrode pad in each via 19 exposed on the front surface side and the back surface side of the base material is performed. As shown in FIG. 5 (12), after forming an electroless copper plating film 22 having a thickness of 0.5 μm on the front and back surfaces of the base material 10, as shown in FIG. An electrolytic copper plating film 23 having a thickness of 20 μm is formed on the back surface.
図６（１４）に示す様に、表面・裏面にドライフィルムレジスト（ＤＦＲ）２４をラミネートし、次いで図６（１５）に示す様に、露光・現像とフォトリソグラフィプロセスによって、ＤＦＲをパターニングして、ビアの上下面をカバーする所定の形状のレジストパターン２５を得る。 As shown in FIG. 6 (14), a dry film resist (DFR) 24 is laminated on the front and back surfaces, and then the DFR is patterned by exposure / development and photolithography processes as shown in FIG. 6 (15). Then, a resist pattern 25 having a predetermined shape covering the upper and lower surfaces of the via is obtained.
そして図６（１６）に示す様に、レジストパターン２５をマスクとして、サブトラクティブ法により、塩化銅系エッチング液を用いて、マスクされない銅エッチング部２６をエッチングする。そして図６（１７）に示す様に、剥離液によってレジストパターン２５を除去することにより、ビア１９に接続した電極パッド２７（配線パターンのランド）が形成される。こうして、表裏面の各電極パッド２７に、それぞれ熱膨張係数が異なる電子部材の電極を接続するなどして、両電子部材間に介在し安定的な接続を実現する、本発明のインターポーザが完成する。 Then, as shown in FIG. 6 (16), the copper etching portion 26 that is not masked is etched by a subtractive method using the resist pattern 25 as a mask, using a copper chloride etching solution. Then, as shown in FIG. 6 (17), by removing the resist pattern 25 with a stripping solution, an electrode pad 27 (land of a wiring pattern) connected to the via 19 is formed. In this way, the interposer of the present invention is realized, which intervenes between both electronic members and realizes stable connection by connecting electrodes of electronic members having different thermal expansion coefficients to the respective electrode pads 27 on the front and back surfaces. .
本実施例のインターポーザは、上記のように表面側の開口径を０．８ｍｍ、裏面側の開口径を０．４ｍｍで形成した。このとき、表面側の熱膨張係数は、１６ｐｐｍ／℃、裏面側のそれは、５ｐｐｍ／℃であった。これは、図１に示した、開口径と熱膨張係数の結果にほとんど相当している。 The interposer of this example was formed with the opening diameter on the front surface side being 0.8 mm and the opening diameter on the back surface side being 0.4 mm as described above. At this time, the thermal expansion coefficient on the front surface side was 16 ppm / ° C., and that on the back surface side was 5 ppm / ° C. This almost corresponds to the results of the opening diameter and the coefficient of thermal expansion shown in FIG.
このインターポーザの表面側に、熱膨張係数１７ｐｐｍ／℃のガラスエポキシ樹脂のプリント基板を、裏面側に熱膨張係数５．５ｐｐｍ／℃のガラスセラミック基板をはんだ接合により張り合わせた。この結果、反り量が、ガラスセラミック基板側の直径１００ｍｍ範囲で０．０５ｍｍ、またこのガラスセラミック基板上にチップを搭載したときのチップサイズ領域相当である２０×２０ｍｍ範囲野場合は０．０１ｍｍと非常に小さな反りが実現できた。 A glass epoxy resin printed board having a thermal expansion coefficient of 17 ppm / ° C. was bonded to the front side of the interposer, and a glass ceramic board having a thermal expansion coefficient of 5.5 ppm / ° C. was bonded to the back side by solder bonding. As a result, the warp amount is 0.05 mm in the range of 100 mm in diameter on the glass ceramic substrate side, and 0.01 mm in the case of a 20 × 20 mm range corresponding to the chip size region when the chip is mounted on this glass ceramic substrate A very small warp could be realized.
比較のために、インターポーザとして、従来と同様に、接合する両基板の中間程度の熱膨張係数（１１〜１２ｐｐｍ／℃）をもつ基板（例えば、ビルアップ基板など）を用いて同様な接合を行ったとき、反り量が、ガラスセラミック基板側の直径１００ｍｍ範囲で０．２ｍｍ、またチップサイズ領域相当である２０×２０ｍｍ範囲の場合は０．０６ｍｍとなっており、本発明のインターポーザで得られる特性の優位性が顕著であることが解る。 For comparison, similar bonding is performed using a substrate (for example, a building-up substrate) having a thermal expansion coefficient (11 to 12 ppm / ° C.) intermediate between both substrates to be bonded as an interposer, as in the past. The warping amount is 0.2 mm in the range of 100 mm in diameter on the glass ceramic substrate side, and 0.06 mm in the case of a 20 × 20 mm range corresponding to the chip size region, and the characteristics obtained with the interposer of the present invention It can be seen that the superiority of is remarkable.
上記の実施例は本発明の一形態と、その作製工程を述べたものであって、これに限らない。実施例では、基材の表面と裏面の異なる開口径間を繋ぐ貫通孔の断面を、三段階のステップ状変化状態（立体空間的には三段の円柱状）としているが、更に多段で構わないし、ステップ状ではなく、リニア状変化状態（立体空間的には先端部が切断された円錐柱状）あるいは一次曲線状としても良い。つまり両開口間の基材内での変化は直線状、（一次）曲線状あるいは階段状でも良い。 The above embodiment describes one embodiment of the present invention and a manufacturing process thereof, but is not limited thereto. In the embodiment, the cross-section of the through hole that connects between the different opening diameters of the front surface and the back surface of the base material has a three-step step change state (three-stage cylindrical shape in three-dimensional space), but it may be further multi-stage. Or it is good also as a linear change state (conical column shape where the front-end | tip part was cut | disconnected in three-dimensional space) or a linear curve shape instead of step shape. That is, the change in the base material between the openings may be linear, (primary) curved or stepped.
使用する基材材料については、開口部のない状態のその基材の熱膨張係数が、インターポーザに接続される電子部材のうち小さいほうの電子部材の熱膨張係数と同等ないしそれ以下のものであれば良い。つまり、一方の面に開口部を設けなければ、同じ熱膨張係数の電子部材のものを接合し、他方の面に開口部を設けて熱膨張係数の大きいほうの電子部材を接続すればよい。 Regarding the base material to be used, the thermal expansion coefficient of the base material without an opening is equal to or less than the thermal expansion coefficient of the smaller electronic member among the electronic members connected to the interposer. It ’s fine. That is, if an opening is not provided on one surface, an electronic member having the same thermal expansion coefficient may be joined, and an opening having an opening on the other surface may be connected to the electronic member having the larger thermal expansion coefficient.
実施例で用いたのと同じ基材ＣＦＲＰ（Ｃａｒｂｏｎ Ｆｉｂｅｒ Ｒｅｉｎｆｏｒｃｅｄ Ｐｌａｓｔｉｃｓ、炭素繊維強化プラスティック）の、プリプレグを積層した基板を基材として用いれば、少なくとも図１で示した実験結果を用いて、熱膨張係数が２〜１６ｐｐｍ／℃の範囲にある２つの電子部材を組み合わせて、ストレスが少ない状態でそれぞれ接続できる表裏２面での開口径を設計することが可能である。さらに適用可能な基材の材料としては、上記のような炭素繊維を含んだ他の構成の材料以外に、同様にビルドアップ基板形成に適用されるコア用の材料、例えば、インバー、コバール、４２アロイ、タングステン、モリブデンなどを少なくとも一つを含む材料が適している。 If a substrate on which a prepreg of the same base material CFRP (Carbon Fiber Reinforced Plastics) used in the example is laminated is used as a base material, thermal expansion is performed using at least the experimental results shown in FIG. By combining two electronic members having a coefficient in the range of 2 to 16 ppm / ° C., it is possible to design the opening diameters on the front and back surfaces that can be connected in a state where there is little stress. Further, as applicable base material materials, in addition to the above-described materials including carbon fibers, core materials similarly applied to build-up substrate formation, for example, Invar, Kovar, 42 A material containing at least one of alloy, tungsten, molybdenum and the like is suitable.
本発明のインターポーザを用いることで、先に図９で説明したようなプローブカード１０１の課題を、例えば図７で示すような構成で、接合個所の応力を大きく抑制できる。即ち、図７（１）の模式的な斜視図にあるように、プローブカード１０１のメイン基板１０２とピン（プローブ針）１０４をもつスペーストランスフォーマ（ＳＴ）１０３との間に、両者の熱膨張係数に、開口径を変えることでフィットさせたインターポーザ１を挿入し、図７（２）の断面模式図に示す様に、インターポーザ１を挟んで配置し、図７（３）に示す様に、加熱して両者をはんだ接合する。熱膨張係数１７ｐｐｍ／℃のガラスエポキシ樹脂のプリント基板からなるメイン基板１０２と、熱膨張係数５．５ｐｐｍ／℃のガラスセラミック基板からなるスペーストランスフォーマ（ＳＴ）１０３とストレス無く接合するには、例えば、実施例で述べたインターポーザ１、つまり積層ＣＦＲＰプリプレグ基板を基材とし、一方の側の開口径を０．４ｍｍ、他方の側の開口径を０．８ｍｍとして１ｍｍピッチ開口加工して形成したインターポーザを用いればよい。 By using the interposer of the present invention, the problem of the probe card 101 as previously described with reference to FIG. 9 can be largely suppressed with the configuration as shown in FIG. 7, for example. That is, as shown in the schematic perspective view of FIG. 7 (1), between the main board 102 of the probe card 101 and the space transformer (ST) 103 having the pins (probe needles) 104, the thermal expansion coefficients of the two are both. Then, the interposer 1 fitted by changing the opening diameter is inserted, and the interposer 1 is arranged with the interposer 1 interposed therebetween as shown in the schematic cross-sectional view of FIG. 7 (2), and the heating is performed as shown in FIG. 7 (3). Then, they are soldered together. In order to join the main substrate 102 made of a glass epoxy resin printed board having a thermal expansion coefficient of 17 ppm / ° C. and the space transformer (ST) 103 made of a glass ceramic substrate having a thermal expansion coefficient of 5.5 ppm / ° C. without stress, for example, The interposer 1 described in the embodiment, that is, an interposer formed by processing a 1 mm pitch opening with a laminated CFRP prepreg substrate as a base and an opening diameter on one side of 0.4 mm and an opening diameter on the other side of 0.8 mm. Use it.
また、例えばプリント基板からなるマザーボード上に、半導体チップがパッケージされたセラミックパッケージをＢＧＡ実装したときの接合個所での大きなストレスを解消するためには、同様に本発明のインターポーザを両者の間に挿入すればよい。 For example, in order to relieve a large stress at a joint portion when a ceramic package in which a semiconductor chip is packaged is mounted on a motherboard made of a printed circuit board by BGA, the interposer of the present invention is similarly inserted between the two. do it.
図８はその様子を示す模式的な断面図である。図８（１）において、メイン基板１０２に、この場合は下部電極にはんだボール２８が搭載された本発明のインターポーザ１を用意し、その上に搭載するセラミックパッケージ２９も下部電極にはんだボール２８が搭載されていて、ＢＧＡ実装可能とする。この場合、２回のリフロー工程を行うことから、前者はんだボールの融点は後者のはんだボールのそれより高いものとする。図８（２）に示す様に、リフロー工程により、メイン基板１０２上にインターポーザ１をＢＧＡ実装法で搭載し、次いで同様にインターポーザ1上にセラミックパッケージ２８をＢＧＡ実装法で搭載する。このような構成によって、インターポーザ１の上側・下側の各熱膨張係数の値をセラミック基板およびプリント基板の各熱膨張係数の値に合わせてように開口径などを調整し、各ＢＧＡ実装接合点での応力を緩和することができる。 FIG. 8 is a schematic sectional view showing the state. In FIG. 8 (1), the interposer 1 of the present invention in which the solder ball 28 is mounted on the lower electrode in this case is prepared on the main substrate 102, and the ceramic package 29 mounted thereon also has the solder ball 28 mounted on the lower electrode. It is installed and BGA mounting is possible. In this case, since the reflow process is performed twice, the melting point of the former solder ball is higher than that of the latter solder ball. As shown in FIG. 8B, by the reflow process, the interposer 1 is mounted on the main substrate 102 by the BGA mounting method, and then the ceramic package 28 is similarly mounted on the interposer 1 by the BGA mounting method. With such a configuration, the aperture diameter and the like are adjusted so that the thermal expansion coefficient values of the upper and lower sides of the interposer 1 match the thermal expansion coefficient values of the ceramic substrate and the printed circuit board. The stress at can be relaxed.
１ インターポーザ
２、１０ 基材
３ 絶縁層
４ 開口部
５、１９ ビア
６ 電極
７、１５、２１ 絶縁樹脂
８ カーボン／エポキシプリプレグ
９ ガラス／エポキシプリプレグ
１１ 細径貫通孔
１２ 中間径加工孔
１３ 大径加工孔
１４ 三段階開口径
１６ スルーホール
１７、２２ 無電解めっき膜
１８、２３ 電解めっき膜
２０ ビア空洞部
２４ ドライフィルムレジスト
２５ レジストパターン
２６ 銅エッチング部
２７ 電極パッド
２８ はんだボール
２９ セラミックパッケージ
DESCRIPTION OF SYMBOLS 1 Interposer 2, 10 Base material 3 Insulating layer 4 Opening part 5, 19 Via 6 Electrode 7, 15, 21 Insulating resin 8 Carbon / epoxy prepreg 9 Glass / epoxy prepreg 11 Small diameter through-hole 12 Medium diameter processing hole 13 Large diameter processing Hole 14 Three-stage opening diameter 16 Through hole 17, 22 Electroless plating film 18, 23 Electrolytic plating film 20 Via cavity 24 Dry film resist 25 Resist pattern 26 Copper etching part 27 Electrode pad 28 Solder ball 29 Ceramic package
Claims (5)
導電性基材と、
前記導電性基材上の第１面側絶縁層及び第２面側絶縁層と、
前記第１面側絶縁層及び前記第２面側絶縁層上に形成された、第１面側導体層及び第２面側導体層と、
前記第１面側絶縁層、前記第２面側絶縁層及び前記導電性基材を貫通する複数の貫通孔と、
前記貫通孔中に形成された絶縁層と、
前記貫通孔中の前記絶縁層上に形成され、前記第１面側導体層と前記第２面側導体層とを電気的に接続する導電ビアとを有し、
前記貫通孔の前記導電性基材における第１面側開口径は第２面側開口径より小さく、
前記第１面側導体層に接続する前記電子部材の熱膨張係数は、前記第２面側導体層に接続する前記電子部材の熱膨張係数より小さく、かつ前記導電性基材の熱膨張係数よりも大きいことを特徴とするインターポーザ。 An interposer that connects each electronic member interposed between two electronic members having different thermal expansion coefficients, the interposer,
A conductive substrate;
A first surface side insulating layer and a second surface side insulating layer on the conductive substrate;
A first surface side conductor layer and a second surface side conductor layer formed on the first surface side insulating layer and the second surface side insulating layer;
A plurality of through holes penetrating the first surface side insulating layer, the second surface side insulating layer, and the conductive substrate;
An insulating layer formed in the through hole;
A conductive via formed on the insulating layer in the through hole and electrically connecting the first surface side conductor layer and the second surface side conductor layer;
The first surface side opening diameter of the through hole in the conductive substrate is smaller than the second surface side opening diameter,
The thermal expansion coefficient of the electronic member connected to the first surface side conductor layer is smaller than the thermal expansion coefficient of the electronic member connected to the second surface side conductor layer, and more than the thermal expansion coefficient of the conductive base material. An interposer characterized by its large size.
前記第１面側開口径は表面側開口径、前記第２面側開口径は裏面側開口径であることを特徴とする請求項１に記載のインターポーザ。
The first surface side insulating layer is a front surface side insulating layer, the second surface side insulating layer is a back surface side insulating layer,
The interposer according to claim 1, wherein the first surface side opening diameter is a front surface side opening diameter, and the second surface side opening diameter is a back surface side opening diameter.
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| JP6690142B2 (en) * | 2015-07-09 | 2020-04-28 | 大日本印刷株式会社 | Through electrode substrate, method of manufacturing through electrode substrate, and interposer using through electrode substrate |
| JP7221601B2 (en) * | 2018-06-11 | 2023-02-14 | 新光電気工業株式会社 | Wiring board, method for manufacturing wiring board |
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