JP2006114621A - Wiring plate with built-in component and manufacturing method thereof - Google Patents

Wiring plate with built-in component and manufacturing method thereof Download PDF

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JP2006114621A
JP2006114621A JP2004299048A JP2004299048A JP2006114621A JP 2006114621 A JP2006114621 A JP 2006114621A JP 2004299048 A JP2004299048 A JP 2004299048A JP 2004299048 A JP2004299048 A JP 2004299048A JP 2006114621 A JP2006114621 A JP 2006114621A
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wiring
wiring board
conductor
insulating layer
conductive bump
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JP4597631B2 (en
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Kenji Sasaoka
賢司 笹岡
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DT Circuit Technology Co Ltd
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DT Circuit Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a load in production in a wiring plate with a built-in component, having an electric/electronic component embedded into an insulating layer, and to provide its manufacturing method. <P>SOLUTION: The wiring plate with the built-in component is equipped with the insulating layer, a first conductor penetrating the insulating layer, first and second wiring layers provided on the upper and lower surfaces of the insulating layer while being conducted electrically with the first conductor, the electric/electronic component provided so that at least one part thereof is embedded into the insulating layer, and a second conductor connecting electrically and mechanically the terminal of the electric/electronic component with the first or second wiring layer and constituted of a composite material same as the material of the first conductor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、電気／電子部品を絶縁層中に埋め込み有する部品内蔵配線板およびその製造方法に係り、特に、生産性向上に適する部品内蔵配線板およびその製造方法に関する。   The present invention relates to a component built-in wiring board having electric / electronic components embedded in an insulating layer and a manufacturing method thereof, and more particularly to a component built-in wiring board suitable for improving productivity and a manufacturing method thereof.

電気部品を絶縁層中に埋め込み有する部品内蔵配線板として、例えば下記特許文献１に開示されたものがある。同文献図１に示されるその構造によると、電気部品の配線層への電気的接続には半田（または導電性組成物）が用いられ、電気部品を埋め込み有する絶縁層を貫通する層間接続体（配線層間の導電体）には貫通孔に充填された導電性組成物が用いられている。その製造方法は、あらかじめ、コアとなる配線板に半田（または導電性組成物）を用いて電気部品を電気的・機械的に接続する。またこれとは別の絶縁樹脂層に穴あけを行いこの穴に導電性組成物を充填し、先に部品実装したコア板と位置合わせ配置して積層・一体化する。
特開２００３−１９７８４９号公報 As a component built-in wiring board having an electrical component embedded in an insulating layer, for example, there is one disclosed in Patent Document 1 below. According to the structure shown in FIG. 1 of the same literature, solder (or a conductive composition) is used for electrical connection to the wiring layer of the electrical component, and an interlayer connection body (through the insulating layer embedded with the electrical component) ( For the conductor between the wiring layers, a conductive composition filled in the through holes is used. In the manufacturing method, electrical components are electrically and mechanically connected to a wiring board serving as a core in advance using solder (or a conductive composition). In addition, a hole is formed in another insulating resin layer, and the hole is filled with a conductive composition, aligned and arranged with the core plate on which the component has been previously mounted, and laminated and integrated.
JP 2003-197849 A

上記のような配線板では、部品実装に要する部材（半田または導電性組成物）と層間接続体とするための部材とは材料として別または別の組成に調製することが適切と考えられる。このため、複数の材料の調達や在庫管理など管理上の手間がかかる。また、部品実装工程で必要な生産設備と、配線板として積層・一体化するための必要な生産設備とはまったく別であり、設備投資上の負担が大きい。   In the wiring board as described above, it is considered appropriate to prepare a member (solder or conductive composition) required for component mounting and a member for forming an interlayer connector as materials or different compositions. For this reason, it takes time and effort for management such as procurement of a plurality of materials and inventory management. Also, the production equipment necessary for the component mounting process is completely different from the production equipment necessary for stacking and integrating as a wiring board, and the burden on equipment investment is large.

本発明は、上記の事情を考慮してなされたもので、電気／電子部品を絶縁層中に埋め込み有する部品内蔵配線板およびその製造方法において、製造上の負担が小さい部品内蔵配線板およびその製造方法を提供することを目的とする。   The present invention has been made in consideration of the above circumstances, and in a component built-in wiring board having an electric / electronic component embedded in an insulating layer and a method for manufacturing the same, a component built-in wiring board having a small manufacturing burden and its manufacturing It aims to provide a method.

上記の課題を解決するため、本発明に係る部品内蔵配線板は、絶縁層と、前記絶縁層を貫通する第１の導電体と、前記絶縁層の上面および下面に設けられ、前記第１の導電体に電気的導通する第１および第２の配線層と、前記絶縁層に少なくとも一部が埋め込まれて設けられた電気／電子部品と、前記電気／電子部品の端子と前記第１または第２の配線層とを電気的・機械的に接続し、かつ、前記第１の導電体と同じ組成材料からなる第２の導電体とを具備することを特徴とする。   In order to solve the above problems, a component built-in wiring board according to the present invention is provided on an insulating layer, a first conductor penetrating the insulating layer, and an upper surface and a lower surface of the insulating layer, First and second wiring layers that are electrically connected to a conductor, an electrical / electronic component that is provided with at least a portion embedded in the insulating layer, a terminal of the electrical / electronic component, and the first or second And a second conductor made of the same composition material as the first conductor. The second conductor layer is electrically and mechanically connected to the second wiring layer.

この部品内蔵配線板では、電気／電子部品の端子が第２の導電体により第１または第２の配線層に電気的・機械的に接続されている。第１の配線層と第２の配線層とはその間に絶縁層を有しており、この絶縁層を第１の導電体が貫通することにより第１の配線層と第２の配線層とが電気的導通可能な構成である。電気／電子部品は絶縁層に少なくともその一部が埋め込まれている。このような部品内蔵配線板で、第１の導電体（層間接続体）と第２の導電体（部品実装に要する部材）とは同じ組成材料からなっている。したがって、第１および第２の導電体を容易に同時に形成することが可能であり、材料調達や生産設備などの点で製造上の負担を軽くすることが可能である。   In this component built-in wiring board, the terminal of the electric / electronic component is electrically and mechanically connected to the first or second wiring layer by the second conductor. The first wiring layer and the second wiring layer have an insulating layer between them, and the first wiring layer and the second wiring layer are formed by the first conductor passing through the insulating layer. It is the structure which can be electrically conducted. The electric / electronic component is at least partially embedded in the insulating layer. In such a component built-in wiring board, the first conductor (interlayer connection body) and the second conductor (members required for component mounting) are made of the same composition material. Therefore, the first and second conductors can be easily formed at the same time, and the manufacturing burden can be reduced in terms of material procurement and production facilities.

また、本発明に係る部品内蔵配線板の製造方法は、第１の金属箔上または第１の金属配線パターンを有する第１の絶縁層の前記第１の金属配線パターン上に、第１の導電性バンプと、該第１の導電性バンプより高さが低くかつ該第１の導電性バンプと同じ材料からなる第２の導電性バンプとを形成する第１の工程と、前記形成された第２の導電性バンプを介するように、前記第１の金属箔上または前記第１の絶縁層の前記第１の金属配線パターン上に電気／電子部品をマウントする第２の工程と、前記形成された第１の導電性バンプが貫通するように前記第１の金属箔上または前記第１の絶縁層の前記第１の金属配線パターン上に第２の絶縁層を積層する第３の工程と、前記第２の絶縁層を貫通した前記第１の導電性バンプの頭部を変形させこれと電気的導通を得るように、前記積層された第２の絶縁層上に、第２の金属箔を積層・一体化または第２の金属配線パターンを有する第３の絶縁層を積層・一体化する第４の工程とを具備することを特徴とする。   In the method for manufacturing a component built-in wiring board according to the present invention, the first conductive layer is formed on the first metal foil or on the first metal wiring pattern of the first insulating layer having the first metal wiring pattern. A first step of forming a conductive bump and a second conductive bump having a height lower than that of the first conductive bump and made of the same material as the first conductive bump; A second step of mounting an electrical / electronic component on the first metal foil or on the first metal wiring pattern of the first insulating layer so as to pass through two conductive bumps; A third step of laminating a second insulating layer on the first metal foil or on the first metal wiring pattern of the first insulating layer so that the first conductive bump penetrates; The head of the first conductive bump penetrating the second insulating layer is deformed. In order to obtain electrical continuity, a second metal foil is laminated / integrated or a third insulating layer having a second metal wiring pattern is laminated / integrated on the laminated second insulating layer. And a fourth step.

この製造方法は、上記の部品内蔵配線板を製造するひとつの方法である。第１の導電性バンプと第２の導電性バンプとはひとつの工程として形成され、その後の工程で第１の導電性バンプは層間接続体となり、第２の導電性バンプは電気／電子部品の端子接続用の部材となる。よって製造上の負担が小さい。   This manufacturing method is one method for manufacturing the component built-in wiring board. The first conductive bump and the second conductive bump are formed as one process, and in the subsequent process, the first conductive bump becomes an interlayer connection, and the second conductive bump is an electric / electronic component. It becomes a member for terminal connection. Therefore, the manufacturing burden is small.

本発明によれば、電気／電子部品を絶縁層中に埋め込み有する部品内蔵配線板およびその製造方法において、製造上の負担を小さくすることができる。   According to the present invention, in a component built-in wiring board having an electric / electronic component embedded in an insulating layer and a method for manufacturing the same, the manufacturing burden can be reduced.

本発明の実施態様として、前記第１の導電体は、導電性組成物からなり、かつ、層方向に一致する軸を有し前記軸の方向に径が変化している形状である、とすることができる。例えば第１の導電体を導電性組成物ペーストのスクリーン印刷によって形成した場合である。   As an embodiment of the present invention, the first conductor is made of a conductive composition and has a shape that has an axis that coincides with the layer direction and has a diameter that changes in the direction of the axis. be able to. For example, the first conductor is formed by screen printing of a conductive composition paste.

また、実施態様として、前記第１の導電体は、金属からなり、かつ、層方向に一致する軸を有し前記軸の方向に径が変化している形状である、とすることもできる。例えば第１の導電体を金属板のエッチングにより形成した場合である。   As an embodiment, the first conductor may be made of a metal and has a shape that has an axis that coincides with the layer direction and has a diameter that changes in the direction of the axis. For example, this is a case where the first conductor is formed by etching a metal plate.

また、実施態様として、前記第１の導電体は、金属からなり、かつ、層方向に一致する軸を有し前記軸の方向に径が変化していない形状である、とすることもできる。例えば第２の導電体を金属面上の選択的領域への金属めっきで形成した場合である。   As an embodiment, the first conductor may be made of a metal and has a shape that has an axis that coincides with the layer direction and has a diameter that does not change in the direction of the axis. For example, the second conductor is formed by metal plating on a selective region on the metal surface.

また、実施態様として、前記第１および第２の導電体と、前記電気／電子部品が接続された前記第１または第２の配線層との間に前記第１の導電体とは異なる材料の層をさらに具備する、とすることができる。例えば、第１および第２の導電体を金属板のエッチングで形成した場合に、エッチングストッパの層が残存したものである。   As an embodiment, a material different from that of the first conductor is provided between the first and second conductors and the first or second wiring layer to which the electric / electronic component is connected. It may further comprise a layer. For example, when the first and second conductors are formed by etching a metal plate, the etching stopper layer remains.

また、実施態様として、前記第２の導電体の前記第１または第２の配線層に接する面積は、前記第１の導電体の該第１または第２の配線層に接する面積より小さい、とすることができる。第１の導電体および第２の導電体で、必要な高さに応じた底面積を持たせたものである。   As an embodiment, the area of the second conductor in contact with the first or second wiring layer is smaller than the area of the first conductor in contact with the first or second wiring layer. can do. The first conductor and the second conductor have a bottom area corresponding to the required height.

また、実施態様として、前記電気／電子部品は、ベアチップ半導体であるとすることができる。電気／電子部品のひとつの例である。ここで、前記第２の導電体は、前記ベアチップ半導体を前記第１または第２の配線層にフリップチップ接続する導電体である、とすることができる。第１または第２の配線層とベアチップ半導体上の端子パッドとを第２の導電体で接続する態様である。   As an embodiment, the electric / electronic component may be a bare chip semiconductor. It is an example of an electrical / electronic component. Here, the second conductor may be a conductor that flip-chip connects the bare chip semiconductor to the first or second wiring layer. In this embodiment, the first or second wiring layer and the terminal pad on the bare chip semiconductor are connected by a second conductor.

また、製造方法としての実施態様として、前記第１の工程は、前記第１の導電性バンプと前記第２の導電性バンプとを同時形成する、とし得る。同時形成によりなお生産性を向上する。第１および第２の導電性バンプの材料が同じであることから同時形成が容易である。   Further, as an embodiment as a manufacturing method, the first step may be to simultaneously form the first conductive bump and the second conductive bump. Productivity is still improved by simultaneous formation. Since the materials of the first and second conductive bumps are the same, simultaneous formation is easy.

ここで、前記第１の工程は、前記第１の導電性バンプと前記第２の導電性バンプとを導電性組成物のスクリーン印刷により同時形成する、とし得る。スクリーン印刷によればこのような同時形成は容易に行うことができる。   Here, the first step may be that the first conductive bump and the second conductive bump are simultaneously formed by screen printing of a conductive composition. Such simultaneous formation can be easily performed by screen printing.

さらに、ここで、前記第１の工程は、前記スクリーン印刷のため径の異なる２種のピットを有するスクリーン板を用いてなされる、とすることができる。径の異なるピットを有するスクリーン板によればピット内容積の違いから容易に高さの異なる導電性バンプを同時に形成することができる。   Further, here, the first step may be performed using a screen plate having two types of pits having different diameters for the screen printing. According to the screen plate having pits having different diameters, conductive bumps having different heights can be easily formed at the same time due to the difference in pit internal volume.

また、ここで、前記第２の工程は、前記導電性組成物をスクリーン印刷することにより形成された前記第２の導電性バンプが硬化する前になされる、とすることができる。硬化する前に電気／電子部品をマウントすることにより導電性組成物の接着性を利用した部品実装ができる。   Here, the second step may be performed before the second conductive bump formed by screen printing the conductive composition is cured. By mounting the electrical / electronic component before curing, component mounting utilizing the adhesive property of the conductive composition can be performed.

あるいは、ここで、前記第２の工程は、前記導電性組成物をスクリーン印刷することにより形成された前記第２の導電性バンプが硬化した後になされる、とすることもできる。硬化した後に電気／電子部品をマウントすることにより、部品の端子上に形成された酸化層などの接続阻害層を破って電気的導通を得ることが容易になり安定した接続が可能になる。   Alternatively, the second step may be performed after the second conductive bump formed by screen printing the conductive composition is cured. By mounting the electrical / electronic component after curing, it is easy to break the connection hindering layer such as an oxide layer formed on the terminal of the component to obtain electrical conduction, and stable connection is possible.

また、ここで、前記第１の工程は、前記第１の導電性バンプと前記第２の導電性バンプとを金属めっき工程により同時形成する、ともできる。金属めっきによってもこのような同時形成は容易に行うことができる。   Also, here, the first step can be performed by simultaneously forming the first conductive bump and the second conductive bump by a metal plating step. Such simultaneous formation can also be easily performed by metal plating.

また、ここで、前記第１の工程は、前記第１の導電性バンプと前記第２の導電性バンプとを金属板のエッチングにより同時形成する、ともできる。金属板のエッチングによってもこのような同時形成は容易に行うことができる。   Here, in the first step, the first conductive bump and the second conductive bump can be simultaneously formed by etching a metal plate. Such simultaneous formation can also be easily performed by etching a metal plate.

また、実施態様として、前記第２の工程は、前記第１および第２の導電性バンプが前記第１の金属箔上に形成されている場合に、前記第１の金属箔を真空吸着によりステージ上に固定してなされる、とすることができる。変形しやすい金属箔の表面上への部品のマウントを確実に行うためである。   As an embodiment, in the second step, the first metal foil is staged by vacuum suction when the first and second conductive bumps are formed on the first metal foil. It can be fixed on the top. This is for reliably mounting the component on the surface of the metal foil that is easily deformed.

以上を踏まえ、以下では本発明の実施形態を図面を参照しながら説明する。図１は、本発明の一実施形態に係る部品内蔵配線板の構成を示す模式的断面図である。図１に示すように、この部品内蔵配線板は、絶縁層１１、配線層（金属配線パターン）１２、１３、導電性バンプ（第１の導電体）１４、導電性バンプ（第２の導電体）１５、抵抗チップ（電気／電子部品）１６を有する。   Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11, wiring layers (metal wiring patterns) 12, 13, conductive bumps (first conductor) 14, conductive bumps (second conductor). ) 15 and a resistor chip (electric / electronic component) 16.

絶縁層１１は、例えばガラスエポキシ樹脂のようなリジッドな絶縁樹脂からなる層あり、その厚さは例えば２００μｍである。配線層１２、１３は、絶縁層１１の上下面にそれぞれ設けられた金属（銅）配線パターンであり厚さは例えば１８μｍである。導電性バンプ１４は、導電性組成物（樹脂中に銀、金、銅などの微細金属粒やカーボンの微細粒を分散させ硬化させたもの）からなり、絶縁層１１を貫通して配線層１２、１３の面間に挟設され配線層１２、１３と電気的導通する。また、製造工程に依拠して軸方向（図示で上下の積層方向）に径が変化しており太い側（配線層１２側）でその直径は例えば３００μｍである。   The insulating layer 11 is a layer made of a rigid insulating resin such as glass epoxy resin, and has a thickness of 200 μm, for example. The wiring layers 12 and 13 are metal (copper) wiring patterns provided on the upper and lower surfaces of the insulating layer 11 and have a thickness of 18 μm, for example. The conductive bumps 14 are made of a conductive composition (in which fine metal particles such as silver, gold, and copper and fine particles of carbon are dispersed and cured in a resin), and penetrate the insulating layer 11 to form the wiring layer 12. , 13 are electrically connected to the wiring layers 12 and 13. Further, the diameter changes in the axial direction (upper and lower lamination directions in the drawing) depending on the manufacturing process, and the diameter is 300 μm on the thick side (wiring layer 12 side), for example.

導電性バンプ１５は、導電性バンプ１４と同じ組成材料からなり、絶縁層１１内に埋め込み設けられて、配線層１２と、内蔵された抵抗チップ１６の端子との間を電気的に接続する。その直径は、配線層１２に接する側で例えば１００μｍである。抵抗チップ１６は、絶縁層１１内に埋め込み設けられおり、その端子が導電性バンプ１５を介して配線層１２に電気的に接続されている。抵抗チップ１６として、例えば０４０２（０．４ｍｍ×０．２ｍｍ）のサイズのものを用いることができる。その厚さは０．１ｍｍを若干上回る程度である。   The conductive bump 15 is made of the same composition material as that of the conductive bump 14 and is embedded in the insulating layer 11 to electrically connect the wiring layer 12 and the terminal of the built-in resistor chip 16. The diameter is, for example, 100 μm on the side in contact with the wiring layer 12. The resistor chip 16 is embedded in the insulating layer 11, and its terminal is electrically connected to the wiring layer 12 through the conductive bump 15. For example, a resistor chip 16 having a size of 0402 (0.4 mm × 0.2 mm) can be used. Its thickness is a little over 0.1 mm.

このような構成の部品内蔵配線板では、層間接続である導電性バンプ１４と、部品（抵抗チップ１６）を配線層１２に電気的に接続するための部材である導電性バンプ１５とが製造上容易に同時形成できる。これは、それらがまったく同じ組成材料でありかつ形成される先が、配線層１２のもととなる同じ金属箔上だからである。以下、この工程を含めて一連の製造工程を説明する。   In the component built-in wiring board having such a configuration, the conductive bumps 14 that are interlayer connections and the conductive bumps 15 that are members for electrically connecting the component (resistor chip 16) to the wiring layer 12 are manufactured. Can be easily formed simultaneously. This is because they are the same composition material and are formed on the same metal foil that is the basis of the wiring layer 12. Hereinafter, a series of manufacturing steps including this step will be described.

図２は、図１に示した部品内蔵配線板の製造過程を模式的断面で示す工程図であり、図１中に示した構成要素と同一または同一相当のものには同一符号を付してある。まず、図２（ａ）に示すように、配線層１２とすべき厚さ例えば１８μｍの金属箔（電解銅箔）１２Ａを用意し、その所定位置に層間接続とする導電性バンプ１４と部品接続用の導電性バンプ１５とを例えば導電性組成物ペーストをスクリーン印刷することにより形成する。   FIG. 2 is a process diagram schematically showing a manufacturing process of the component built-in wiring board shown in FIG. 1, and the same or equivalent components as those shown in FIG. is there. First, as shown in FIG. 2 (a), a metal foil (electrolytic copper foil) 12A having a thickness of, for example, 18 μm to be used as the wiring layer 12 is prepared, and the conductive bumps 14 and the components are connected to each other at predetermined positions. The conductive bumps 15 are formed by screen printing a conductive composition paste, for example.

スクリーン印刷に用いるスクリーン板（メタルマスク）には径の異なる２種のピット（貫通孔）が穿設されたものを用いる。これにより、そのピット内の容積の違いから、大きさ（円錐形状としての底面径および高さ）の異なる２種の導電性バンプ１４、１５を容易に同時形成できる。層間接続とする導電性バンプ１４は例えば底面径３００μｍ、高さ３００μｍ、部品接続用の導電性バンプ１５は、例えば底面径１００μｍ、高さ１００μｍである。   A screen plate (metal mask) used for screen printing is used in which two types of pits (through holes) having different diameters are formed. Thus, two types of conductive bumps 14 and 15 having different sizes (bottom diameter and height as a conical shape) can be easily formed simultaneously due to the difference in volume in the pit. The conductive bumps 14 for interlayer connection have a bottom surface diameter of 300 μm and a height of 300 μm, for example, and the conductive bumps 15 for connecting components have a bottom surface diameter of 100 μm and a height of 100 μm, for example.

次に、図２（ｂ）に示すように、例えばマウンタを用いて０４０２サイズのチップ抵抗１６を、その両端子が導電性バンプ１５上に載るように金属箔１２Ａ上に載置する。この時点では印刷形成された導電性バンプ１５は硬化しておらず容易に変形してチップ抵抗１６の端子との十分な接触面積が確保できる。なお、マウンタによる部品載置に際して、金属箔１２Ａを真空吸着により位置固定できる平坦なステージを用いると好ましい。これにより、金属箔１２Ａにしわがよるなどの変形を回避でき、位置精度の高い部品載置が可能になる。マウンタによる部品載置が終了したら、導電性バンプ１４、１５を乾燥して硬化させ導電性バンプ１５を介してチップ抵抗１６を金属箔１２Ａ上に機械的に固定する。   Next, as shown in FIG. 2B, for example, a mounter is used to place the 0402 size chip resistor 16 on the metal foil 12 </ b> A so that both terminals thereof are placed on the conductive bumps 15. At this time, the printed conductive bumps 15 are not cured and are easily deformed to ensure a sufficient contact area with the terminals of the chip resistor 16. In addition, it is preferable to use a flat stage that can fix the position of the metal foil 12A by vacuum suction when mounting the component by the mounter. As a result, deformation such as wrinkles on the metal foil 12A can be avoided, and component placement with high positional accuracy becomes possible. When the mounting of the components by the mounter is completed, the conductive bumps 14 and 15 are dried and cured, and the chip resistor 16 is mechanically fixed on the metal foil 12A via the conductive bumps 15.

次に、図２（ｃ）に示すように、絶縁層１１とすべき公称厚さ例えば２００μｍのＦＲ−４のプリプレグ１１Ａを金属箔１２Ａ上にプレス機を用い積層する。このとき、導電性バンプ１５の頭部がプリプレグ１１Ａを貫通するように、かつ加熱でプリプレグ１１Ａが流動性を得てチップ抵抗１６を覆いこれを埋め込むようにする。なお、図２（ｃ）における導電性バンプ１４の頭部の破線は、この段階で導電性バンプ１４の頭部を塑性変形させてつぶしておく場合と塑性変形させない場合の両者あり得ることを示す。   Next, as shown in FIG.2 (c), FR-4 prepreg 11A of nominal thickness which should be used as the insulating layer 11, for example, 200 micrometers is laminated | stacked on the metal foil 12A using a press. At this time, the head of the conductive bump 15 penetrates the prepreg 11A, and the prepreg 11A obtains fluidity by heating to cover the chip resistor 16 and embed it. In addition, the broken line at the head of the conductive bump 14 in FIG. 2C indicates that there may be both cases where the head of the conductive bump 14 is plastically deformed and crushed at this stage and when it is not plastically deformed. .

次に、積層されたプリプレグ１１Ａ上に、配線層１３とすべき厚さ例えば１８μｍの金属箔（電解銅箔）１３Ａを配置してプレス機で積層方向に加圧・加熱する。これにより、図２（ｄ）に示すように、プリプレグ１１Ａを完全に硬化させて（＝絶縁層１１）、全体を積層・一体化する。このとき金属箔１３Ａは導電性バンプ１４に電気的に接続される。最後に、絶縁層１１の両面をシールドする金属箔１２Ａ、１３Ａを周知のフォトリソグラフィを利用して所定にパターニングし、図１に示すような配線層１２、１３を有する部品内蔵配線板を得ることができる。なお、金属箔１２Ａのパターニングは、当然ながら、内蔵されたチップ抵抗１６の両端子に接続される配線層１２のパターンが分離するように行う。   Next, a metal foil (electrolytic copper foil) 13A having a thickness of 18 μm, for example, is arranged on the laminated prepreg 11A, and is pressed and heated in the laminating direction by a press. Thereby, as shown in FIG. 2D, the prepreg 11A is completely cured (= insulating layer 11), and the whole is laminated and integrated. At this time, the metal foil 13 </ b> A is electrically connected to the conductive bump 14. Finally, the metal foils 12A and 13A that shield both surfaces of the insulating layer 11 are patterned in a predetermined manner using well-known photolithography to obtain a component built-in wiring board having the wiring layers 12 and 13 as shown in FIG. Can do. The patterning of the metal foil 12A is naturally performed so that the pattern of the wiring layer 12 connected to both terminals of the built-in chip resistor 16 is separated.

以上説明のように、この実施形態では、部品（チップ抵抗１６）を内蔵することによる工程の増加はわずかであり製造上の負担増が小さい部品内蔵配線板およびその製造方法を提供することができる。   As described above, this embodiment can provide a component built-in wiring board and a method for manufacturing the same with a small increase in the process due to the incorporation of the component (chip resistor 16) and a small increase in manufacturing burden. .

次に、本発明の別の実施形態に係る部品内蔵配線板を図３を参照して説明する。図３は、本発明の別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図である。この実施形態の部品内蔵配線板では、上記実施形態に比較してより大型の（厚さが厚い）電気／電子部品を内蔵することができる。   Next, a component built-in wiring board according to another embodiment of the present invention will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view showing a configuration of a component built-in wiring board according to another embodiment of the present invention. In the component built-in wiring board of this embodiment, it is possible to incorporate a larger (thickness) electric / electronic component than the above embodiment.

その構成として、この部品内蔵配線板は、図３に示すように、絶縁層３１、３２、３３、配線層３４、３５、３６、３７（＝合計４層）、導電性バンプ（第１の導電体）３８、３９、導電性バンプ（第２の導電体）４０、チップ部品（電気／電子部品）４１、スルーホール導電体４２を有する。   As shown in FIG. 3, this component built-in wiring board includes insulating layers 31, 32, 33, wiring layers 34, 35, 36, 37 (= four layers in total), conductive bumps (first conductive layer). Bodies) 38, 39, conductive bumps (second conductor) 40, chip parts (electric / electronic parts) 41, and through-hole conductors 42.

絶縁層３２およびその上下面に位置する配線層３５、３６の部分は、コア板の部分であり、このコア板は、スルーホール導電体４２により配線層３５、３６間の電気的導通が得られるように構成されている。また、内蔵されたチップ部品４１に相当する位置部分が開口部となっており、より厚さの厚いチップ部品４１を内蔵するための空間を提供する。絶縁層３２の厚さは例えば３００μｍであり、例えばガラスエポキシ樹脂のようなリジッドな素材である。配線層３５、３６は、厚さ例えば１８μｍの金属（銅）配線パターンである。   The portions of the insulating layer 32 and the wiring layers 35 and 36 positioned on the upper and lower surfaces thereof are core plate portions, and the core plate can obtain electrical continuity between the wiring layers 35 and 36 by the through-hole conductor 42. It is configured as follows. Further, a position corresponding to the built-in chip component 41 is an opening, and provides a space for incorporating a thicker chip component 41. The insulating layer 32 has a thickness of 300 μm, for example, and is a rigid material such as a glass epoxy resin. The wiring layers 35 and 36 are metal (copper) wiring patterns having a thickness of, for example, 18 μm.

絶縁層３１、これを貫通する導電性バンプ３８、導電性バンプ３８に導通する下面の配線層３４、絶縁層３１内に埋め込み設けられた導電性バンプ４０、および、導電性バンプ４０により配線層３４に電気的導通するチップ部品４１の部分は、上記コア板に積層された下側のビルドアップ部分である。また、絶縁層３３、これを貫通する導電性バンプ３９、および、導電性バンプ３９に導通する上面の配線層３７の部分は、上記コア板に積層された上側のビルドアップ部分である。   The insulating layer 31, the conductive bump 38 passing through the insulating layer 31, the lower wiring layer 34 conducting to the conductive bump 38, the conductive bump 40 embedded in the insulating layer 31, and the wiring layer 34 by the conductive bump 40. The part of the chip part 41 that is electrically connected to the lower part is a lower buildup part laminated on the core plate. The insulating layer 33, the conductive bump 39 passing through the insulating layer 33, and the upper wiring layer 37 connected to the conductive bump 39 are the upper build-up portion laminated on the core plate.

絶縁層３１、３３は、内蔵されたチップ部品４１のための、絶縁層３２の開口部、および絶縁層３２のスルーホール導電体４２内部の空間を埋めるように変形進入しており内部に空隙となる空間は存在しない。絶縁層３１、３３は例えばガラスエポキシ樹脂のようなリジッドな絶縁樹脂からなり、その層としての厚さは例えばそれぞれ１００μｍである。配線層３４、３７は、厚さ例えば１８μｍの金属（銅）配線パターンである。   The insulating layers 31 and 33 are deformed so as to fill the space inside the through-hole conductor 42 of the insulating layer 32 and the opening of the insulating layer 32 for the built-in chip component 41, and there are voids inside. There is no space. The insulating layers 31 and 33 are made of, for example, a rigid insulating resin such as glass epoxy resin, and the thickness of each layer is, for example, 100 μm. The wiring layers 34 and 37 are metal (copper) wiring patterns having a thickness of, for example, 18 μm.

導電性バンプ３８、３９は、すでに説明したような導電性組成物からなり、絶縁層３１または絶縁層３３を貫通して配線層３４、３５間、または配線層３６、３７間に挟設され、配線層３４、３５、または配線層３６、３７と電気的導通する。また、製造工程に依拠して軸方向（図示で上下の積層方向）に径が変化しており太い側（配線層３４側または３７側）でその直径は例えば２００μｍである。   The conductive bumps 38 and 39 are made of a conductive composition as described above, and are interposed between the wiring layers 34 and 35 or between the wiring layers 36 and 37 through the insulating layer 31 or the insulating layer 33. It is electrically connected to the wiring layers 34 and 35 or the wiring layers 36 and 37. Further, the diameter changes in the axial direction (upper and lower lamination directions in the drawing) depending on the manufacturing process, and the diameter is, for example, 200 μm on the thicker side (wiring layer 34 side or 37 side).

導電性バンプ４０は、導電性バンプ３８、３９と同じ組成材料からなり、絶縁層３１内に埋め込み設けられて、配線層３４と、内蔵されたチップ部品４１の端子との間を電気的に接続する。その直径は、配線層３４に接する側で例えば５０μｍである。チップ部品４１は、絶縁層３１、３３内に埋め込み設けられており、その端子が導電性バンプ４０を介して配線層３４に電気的に接続されている。チップ部品４１は、その厚さとして０．４ｍｍ程度のものまでは内蔵可能である。   The conductive bump 40 is made of the same composition material as the conductive bumps 38 and 39 and is embedded in the insulating layer 31 to electrically connect the wiring layer 34 and the terminal of the built-in chip component 41. To do. The diameter is, for example, 50 μm on the side in contact with the wiring layer 34. The chip component 41 is embedded in the insulating layers 31 and 33, and its terminals are electrically connected to the wiring layer 34 via the conductive bumps 40. The chip component 41 can be built up to a thickness of about 0.4 mm.

このような構成の部品内蔵配線板でも、層間接続である導電性バンプ３８と、部品（チップ部品４１）を配線層３４に電気的に接続するための部材である導電性バンプ４０とは製造上容易に同時形成できる。これは、先の実施形態と同様に、それらがまったく同じ組成材料でありかつ形成先が配線層３４のもととなる同じ金属箔上だからである。以下、この工程を含めて一連の製造工程を説明する。   Even in the component built-in wiring board having such a configuration, the conductive bump 38 which is an interlayer connection and the conductive bump 40 which is a member for electrically connecting the component (chip component 41) to the wiring layer 34 are manufactured. Can be easily formed simultaneously. This is because, as in the previous embodiment, they are exactly the same composition material and the formation destination is on the same metal foil from which the wiring layer 34 is based. Hereinafter, a series of manufacturing steps including this step will be described.

図４、図５、図６は、それぞれ、図３に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図、図３に示した部品内蔵配線板の製造過程の別の一部を模式的断面で示す工程図、図３に示した部品内蔵配線板の製造過程のさらに別の一部を模式的断面で示す工程図である。これらの図において、図３中に示した構成要素と同一または同一相当のものには同一符号を付してある。   4, 5, and 6 are process diagrams schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. 3, respectively, and the manufacturing process of the component built-in wiring board shown in FIG. FIG. 4 is a process diagram showing a part of a schematic cross section, and a process diagram showing another part of the manufacturing process of the component built-in wiring board shown in FIG. 3 in a schematic cross section. In these drawings, the same or equivalent components as those shown in FIG. 3 are denoted by the same reference numerals.

図４は、換言すると、コア板に積層される下側のビルドアップ部分の製造工程を示す図である。その思想としては、図４（ａ）、（ｂ）、（ｃ）それぞれ、図２に示した先の実施形態の製造工程における（ａ）、（ｂ）、（ｃ）と一部を除き同様である。   In other words, FIG. 4 is a diagram showing a manufacturing process of the lower buildup portion laminated on the core plate. 4 (a), (b), and (c) are the same except for (a), (b), and (c) in the manufacturing process of the previous embodiment shown in FIG. It is.

まず、図４（ａ）に示すように、配線層３４とすべき厚さ例えば１８μｍの金属箔（電解銅箔）３４Ａを用意し、その所定位置に層間接続とする導電性バンプ３８と部品接続用の導電性バンプ４０とを例えば導電性組成物ペーストをスクリーン印刷することにより形成する。スクリーン板（メタルマスク）には径の異なる２種のピットが穿設されたものを用いる。このようなスクリーン板を使用して、層間接続とする導電性バンプ３８は例えば底面径２００μｍ、高さ１６０μｍ、部品接続用の導電性バンプ４０は、例えば底面径５０μｍ、高さ３０μｍに形成する。   First, as shown in FIG. 4A, a metal foil (electrolytic copper foil) 34A having a thickness of, for example, 18 μm to be used as the wiring layer 34 is prepared, and conductive bumps 38 are connected to the parts at predetermined positions. For example, the conductive bump 40 is formed by screen printing a conductive composition paste. A screen plate (metal mask) having two types of pits with different diameters is used. Using such a screen plate, the conductive bumps 38 for interlayer connection are formed with a bottom diameter of 200 μm and a height of 160 μm, for example, and the conductive bumps 40 for connecting components are formed with a bottom diameter of 50 μm and a height of 30 μm, for example.

次に、図４（ｂ）に示すように、例えばマウンタを用いてチップ部品４１を、その両端子が導電性バンプ４０上に載るように金属箔３４Ａ上に載置する。マウンタによる部品載置が終了したら、導電性バンプ３８、４０を乾燥して硬化させ導電性バンプ４０を介してチップ部品４１を金属箔３４Ａ上に機械的に固定する。   Next, as shown in FIG. 4B, the chip component 41 is placed on the metal foil 34 </ b> A so that both terminals thereof are placed on the conductive bumps 40 using, for example, a mounter. When the mounting of the component by the mounter is completed, the conductive bumps 38 and 40 are dried and cured, and the chip component 41 is mechanically fixed on the metal foil 34 </ b> A via the conductive bump 40.

次に、図４（ｃ）に示すように、絶縁層３１とすべき公称厚さ例えば１００μｍのＦＲ−４のプリプレグ３１Ａを金属箔３４Ａ上にプレス機を用い積層する。このとき、プリプレグ３１Ａとしてチップ部品４１の位置に相当する部分に開口が設けられたものを用い、また、プリプレグ３１Ａの上側にはチップ部品４１の厚さを吸収できるクッション材（不図示）を介在させて加圧・加熱する。これにより、より確実に、導電性バンプ３８の頭部がプリプレグ３１Ａを貫通するようになる。なお、図４（ｃ）における導電性バンプ３８の頭部の破線は、この段階で導電性バンプ３８の頭部を塑性変形させてつぶしておく場合と塑性変形させない場合の両者あり得ることを示す。以上により、図４（ｃ）に示すような、コア板に積層される下側のビルドアップ部分の配線板素材１が得られる。   Next, as shown in FIG.4 (c), FR-4 prepreg 31A of nominal thickness which should be used as the insulating layer 31, for example, 100 micrometers is laminated | stacked on metal foil 34A using a press. At this time, a prepreg 31A having an opening at a portion corresponding to the position of the chip component 41 is used, and a cushion material (not shown) capable of absorbing the thickness of the chip component 41 is interposed above the prepreg 31A. And pressurize and heat. Thereby, the head of the conductive bump 38 penetrates the prepreg 31A more reliably. Note that the broken line at the head of the conductive bump 38 in FIG. 4C indicates that there may be both cases where the head of the conductive bump 38 is plastically deformed and crushed at this stage and when it is not plastically deformed. . As described above, the wiring board material 1 of the lower buildup portion laminated on the core plate as shown in FIG. 4C is obtained.

図５は、言い換えるとコア板の部分の製造工程を示す図である。まず、図５（ａ）に示すように、両面に例えば厚さ１８μｍの金属箔（電解銅箔）３５Ａ、３６Ａが積層された例えば厚さ３００μｍのＦＲ−４の絶縁層３２を用意し、その所定位置にスルーホール導電体を形成するための貫通孔５２をあけ、かつ内蔵するチップ部品４１に相当する部分に開口部５１を形成する。   FIG. 5 is a diagram showing a manufacturing process of the core plate portion in other words. First, as shown in FIG. 5A, for example, an FR-4 insulating layer 32 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 35A and 36A having a thickness of 18 μm are laminated on both surfaces is prepared. A through-hole 52 for forming a through-hole conductor is formed at a predetermined position, and an opening 51 is formed at a portion corresponding to the chip component 41 to be incorporated.

次に、無電解めっきおよび電解めっきを行い、図５（ｂ）に示すように、貫通孔５２の内壁にスルーホール導電体４２を形成する。このとき開口部５１の内壁にも導電体が形成される。さらに、図５（ｃ）に示すように、金属箔３５Ａ、３６Ａを周知のフォトリソグラフィを利用して所定にパターニングする（配線層３５、３６）。配線層３５、３６のパターニング形成により、開口部５１の内壁に形成された導電体も除去される。以上により、コア板の部分の配線板素材２を得ることができる。   Next, electroless plating and electrolytic plating are performed to form a through-hole conductor 42 on the inner wall of the through hole 52 as shown in FIG. At this time, a conductor is also formed on the inner wall of the opening 51. Further, as shown in FIG. 5C, the metal foils 35A and 36A are patterned in a predetermined manner using known photolithography (wiring layers 35 and 36). The conductor formed on the inner wall of the opening 51 is also removed by patterning the wiring layers 35 and 36. As described above, the wiring board material 2 of the core board portion can be obtained.

図６は、換言すると、コア板部分の配線板素材２の上下両面に、上側のビルドアップ部分の配線板素材３と下側のビルドアップ部分の配線板素材１とを積層する配置関係を示す図である。ここで、上側の配線板素材３は、下側の配線板素材１と同様な工程を適用することで得られたものである。ただし、部品（チップ部品４１）を接続するために生じる部位（導電性バンプ４０、プリプレグ３３Ａの開口）のない構成である。そのほかは、金属箔（電解銅箔）３７Ａ、導電性バンプ３９、プリプレグ３３Ａとも、それぞれ配線板素材１の金属箔３４Ａ、導電性バンプ３８、プリプレグ３１Ａと同じである。   In other words, FIG. 6 shows an arrangement relationship in which the upper buildup portion of the wiring board material 3 and the lower buildup portion of the wiring board material 1 are laminated on the upper and lower surfaces of the core board portion of the wiring board material 2. FIG. Here, the upper wiring board material 3 is obtained by applying the same process as the lower wiring board material 1. However, it is a structure without the site | part (conductive bump 40, opening of prepreg 33A) produced in order to connect components (chip component 41). Other than that, the metal foil (electrolytic copper foil) 37A, the conductive bump 39, and the prepreg 33A are the same as the metal foil 34A, the conductive bump 38, and the prepreg 31A of the wiring board material 1, respectively.

図６に示すような配置で各配線板素材１、２、３を積層配置してプレス機で加圧・加熱する。これにより、プリプレグ３１Ａ、３３Ａが完全に硬化し全体が積層・一体化する。このとき、加熱により得られるプリプレグ３１Ａ、３３Ａの流動性により、チップ部品４１の周りの空間にはプリプレグ３１Ａ、３３Ａが変形進入し空隙は発生しない。また、配線層３５、３６は、導電性バンプ３８、３９にそれぞれ電気的に接続される。この積層工程の後、上下両面の金属箔３４Ａ、３７Ａを周知のフォトリソグラフィを利用して所定にパターニングし、図３に示すような部品内蔵配線板を得ることができる。なお、金属箔３４Ａのパターニングは、当然ながら、内蔵されたチップ部品４１の両端子に接続される配線層３４のパターンが分離するように行う。   The respective wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. Thereby, the prepregs 31 </ b> A and 33 </ b> A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 31 </ b> A and 33 </ b> A obtained by heating, the prepregs 31 </ b> A and 33 </ b> A are deformed and enter the space around the chip component 41, and no gap is generated. The wiring layers 35 and 36 are electrically connected to the conductive bumps 38 and 39, respectively. After this laminating step, the metal foils 34A and 37A on both the upper and lower surfaces are patterned in a predetermined manner using well-known photolithography to obtain a component built-in wiring board as shown in FIG. The patterning of the metal foil 34A is naturally performed so that the patterns of the wiring layer 34 connected to both terminals of the built-in chip component 41 are separated.

以上説明のように、この実施形態でも、部品（チップ部品４１）を内蔵することによる工程の増加はわずかであり製造上の負担増が小さい部品内蔵配線板およびその製造方法を提供することができる。また、内蔵部品に提供される領域が厚さ方向により厚く、より多種の部品を内蔵することが可能である。コア板の部分のスルーホール導電体４２については、導電性バンプ３８、３９と同様な層間接続体とする構成も当然ながら製造可能である。   As described above, this embodiment can also provide a component built-in wiring board and a method for manufacturing the component built-in wiring board with a small increase in the process by incorporating the component (chip component 41) and a small increase in manufacturing burden. . In addition, the region provided for the built-in component is thicker in the thickness direction, and more types of components can be built. As for the through-hole conductor 42 in the core plate portion, it is of course possible to manufacture a structure having an interlayer connection similar to the conductive bumps 38 and 39.

次に、本発明のさらに別の実施形態に係る部品内蔵配線板について図７を参照して説明する。図７は、本発明のさらに別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図であり、すでに説明した図中に示した構成要素と同一または同一相当のものには同一符号を付してある。その部位については加える事項がない限り説明を省略する。   Next, a component built-in wiring board according to still another embodiment of the present invention will be described with reference to FIG. FIG. 7 is a schematic cross-sectional view showing a configuration of a component built-in wiring board according to still another embodiment of the present invention. Components identical or equivalent to those shown in the already described drawings are denoted by the same reference numerals. Is attached. The description of the part is omitted unless there is an additional matter.

この部品内蔵配線板は、図３に示した部品内蔵配線板と構成として似ており、違いは、配線層３４に代わり、絶縁層７１およびその上下面の配線層７２、７３が設けられ、かつ配線層３７に代わり、絶縁層８１およびその上下面の配線層８２、８３が設けられていることである。これにより合計６層の配線層がある。また、絶縁層７１を貫通して導電性バンプ７４が存在し、絶縁層７１の上下面の配線層７２、７３が電気的導通可能な構成になっている。これは、絶縁層８１を貫通する導電性バンプ８４についても同様である。   This component built-in wiring board is similar in configuration to the component built-in wiring board shown in FIG. 3 except that an insulating layer 71 and upper and lower wiring layers 72 and 73 are provided instead of the wiring layer 34, and Instead of the wiring layer 37, an insulating layer 81 and upper and lower wiring layers 82 and 83 are provided. Thus, there are a total of six wiring layers. Further, conductive bumps 74 exist through the insulating layer 71, and the wiring layers 72 and 73 on the upper and lower surfaces of the insulating layer 71 are configured to be electrically conductive. The same applies to the conductive bumps 84 that penetrate the insulating layer 81.

製造工程としては、図４に示した導電性バンプ３８、４０の形成において、金属箔３４Ａに代えて、絶縁層７１の上下面に配線層７２、７３が設けられかつこれらに挟設されて導電性バンプ７４を有する両面配線板を用いればよい（絶縁層７１下側の配線層７２についてはパターニング前のものでもよい。）。金属箔３７Ａに代わる、絶縁層８１、導電性バンプ８４、および配線層８２、８３を有する両面配線板についても同様である（これも、絶縁層８１上側の配線層８２についてはパターニング前のものでもよい。）。代わりに使用するこれらの両面配線板は、図１、図２において説明した実施形態の工程を参照して得ることができる。以降は図４ないし図６の工程を適用することにより、図７に示すような部品内蔵配線板を得ることができる。   As a manufacturing process, in the formation of the conductive bumps 38 and 40 shown in FIG. 4, instead of the metal foil 34A, wiring layers 72 and 73 are provided on the upper and lower surfaces of the insulating layer 71 and sandwiched between them to conduct electricity. A double-sided wiring board having a conductive bump 74 may be used (the wiring layer 72 below the insulating layer 71 may be one before patterning). The same applies to the double-sided wiring board having the insulating layer 81, the conductive bumps 84, and the wiring layers 82 and 83 instead of the metal foil 37A (this also applies to the wiring layer 82 above the insulating layer 81 before patterning). Good.) These double-sided wiring boards used instead can be obtained by referring to the steps of the embodiment described in FIGS. Thereafter, by applying the steps of FIGS. 4 to 6, a component built-in wiring board as shown in FIG. 7 can be obtained.

この実施形態では、絶縁層７１（８１）、導電性バンプ７４（８３）、および配線層７２（８２）、７３（８３）からなる両面配線板の部分に、図１に示したような部品内蔵配線板を用いることもできる。これにより、さらに部品を高密度に内蔵した部品内蔵配線板を得ることができる。   In this embodiment, the component as shown in FIG. 1 is incorporated in the double-sided wiring board portion comprising the insulating layer 71 (81), the conductive bump 74 (83), and the wiring layers 72 (82) and 73 (83). A wiring board can also be used. Thereby, it is possible to obtain a component built-in wiring board in which components are further embedded at high density.

次に、本発明のさらに別の実施形態に係る部品内蔵配線板について図８を参照して説明する。図８は、本発明のさらに別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図であり、すでに説明した図中に示した構成要素と同一または同一相当のものには同一符号を付してある。その部位については加える事項がない限り説明を省略する。   Next, a component built-in wiring board according to still another embodiment of the present invention will be described with reference to FIG. FIG. 8 is a schematic cross-sectional view showing a configuration of a component built-in wiring board according to still another embodiment of the present invention. Components that are the same as or equivalent to the components shown in the already described drawings are denoted by the same reference numerals. Is attached. The description of the part is omitted unless there is an additional matter.

この部品内蔵配線板は、内蔵部品としてベアチップ半導体９１を有するものである。ベアチップ半導体９１の導電性バンプ４０Ａとの接続面側にはアンダーフィル樹脂９２が充填されている。製造工程としては、図７に示した実施形態と似ているが多少異なる点もある。以下説明する。   This component built-in wiring board has a bare chip semiconductor 91 as a built-in component. An underfill resin 92 is filled on the connection surface side of the bare chip semiconductor 91 with the conductive bumps 40A. The manufacturing process is similar to the embodiment shown in FIG. This will be described below.

すなわち、スクリーン印刷による導電性バンプ３８、４０Ａの形成に続き、まずこれらの導電性バンプ３８、４０Ａを乾燥させ硬化させる。そして、アンダーフィル樹脂９２を、硬化させた導電性バンプ４０Ａの領域に塗布する。さらに導電性バンプ４０Ａの位置に合わせてベアチップ半導体９１をフリップチップ接続する。このフリップチップ接続においては、硬化した導電性バンプ４０Ａがベアチップ半導体９１の接続パッド上の酸化膜などの接続阻害層を突き破りやすく安定した電気的接続が実現する。以下の工程は、図７に示した実施形態と同様である。このようにこの実施形態では、接続の信頼性高く、部品としてベアチップ半導体９１を内蔵することができる。   That is, following the formation of the conductive bumps 38 and 40A by screen printing, the conductive bumps 38 and 40A are first dried and cured. And underfill resin 92 is apply | coated to the area | region of 40 A of hardened conductive bumps. Further, the bare chip semiconductor 91 is flip-chip connected in accordance with the position of the conductive bump 40A. In this flip-chip connection, the cured conductive bump 40A easily breaks through a connection-inhibiting layer such as an oxide film on the connection pad of the bare chip semiconductor 91, thereby realizing stable electrical connection. The following steps are the same as those in the embodiment shown in FIG. Thus, in this embodiment, the bare chip semiconductor 91 can be incorporated as a component with high connection reliability.

次に、本発明のさらに別の実施形態に係る部品内蔵配線板について図９を参照して説明する。図９は、本発明のさらに別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図であり、すでに説明した図中に示した構成要素と同一または同一相当のものには同一符号を付してある。その部位については加える事項がない限り説明を省略する。   Next, a component built-in wiring board according to still another embodiment of the present invention will be described with reference to FIG. FIG. 9 is a schematic cross-sectional view showing a configuration of a component built-in wiring board according to still another embodiment of the present invention. Components identical or equivalent to those shown in the already described drawings are denoted by the same reference numerals. Is attached. The description of the part is omitted unless there is an additional matter.

この実施形態では、導電性バンプ３８、４０Ａ、３９に代わり、金属板エッチングにより形成された金属バンプ１０８、１００、１０９を有している。これらの金属バンプ１０８、１００、１０９の配線層７３側または配線層８３側には、図示するように、エッチングストッパ層が残存している。また、絶縁層７１（８１）の絶縁層３１（３３）との境界は、図８に示した実施形態と比較して配線層７３（８３）の厚さ分だけ深い方に移動している。以下、このような構成になっている理由を含めて製造工程を説明する。   In this embodiment, instead of the conductive bumps 38, 40A, 39, metal bumps 108, 100, 109 formed by metal plate etching are provided. As shown in the figure, an etching stopper layer remains on the wiring layer 73 side or the wiring layer 83 side of these metal bumps 108, 100, and 109. Further, the boundary between the insulating layer 71 (81) and the insulating layer 31 (33) is moved deeper by the thickness of the wiring layer 73 (83) as compared with the embodiment shown in FIG. Hereinafter, the manufacturing process will be described including the reason for such a configuration.

図１０は、図９に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図であり、図９における絶縁層７１、配線層７２、７３、導電性バンプ７４、金属バンプ１０８、１００の部分の製造工程を示したものである。図９における絶縁層８１、配線層８２、８３、導電性バンプ８４、金属バンプ１０９の部分の製造工程もほぼ同様である。なお、図９中に示した構成要素と同一または同一相当のものには同一符号を付してある。   FIG. 10 is a process diagram schematically showing a part of a manufacturing process of the component built-in wiring board shown in FIG. 9 in an insulating layer 71, wiring layers 72 and 73, conductive bumps 74, metal bumps in FIG. The manufacturing process of the part of 108 and 100 is shown. The manufacturing process of the insulating layer 81, the wiring layers 82 and 83, the conductive bump 84, and the metal bump 109 in FIG. 9 is substantially the same. In addition, the same code | symbol is attached | subjected to the same or equivalent thing as the component shown in FIG.

まず、例えば厚さ１８μｍの金属箔（電解銅箔）７３Ａにごく薄い厚さ例えば２μｍの例えばニッケル合金からなる層（エッチングストッパ層ＥＳ）が積層された積層膜を用意し、このエッチングストッパ層ＥＳ側に厚さ例えば１２０μｍの金属板（銅板）１０８Ａを積層一体化して、図１０（ａ）に示すように３層構造のクラッド材を得る。   First, for example, a laminated film in which a layer (etching stopper layer ES) made of, for example, a nickel alloy having a very thin thickness, for example, 2 μm, is prepared on a metal foil (electrolytic copper foil) 73A having a thickness of 18 μm is prepared. A metal plate (copper plate) 108A having a thickness of, for example, 120 μm is laminated and integrated on the side to obtain a clad material having a three-layer structure as shown in FIG.

次に、図１０（ｂ）に示すように、金属箔７３Ａを周知のフォトリソグラフィを利用し銅のみエッチング可能なエッチング液で所定にパターニングする。これにより配線層７３を形成する。さらに、図３（ｃ）に示すように、配線層７３上の所定の位置に導電性バンプ７４を導電性塑性物ペーストのスクリーン印刷により形成する。続いて、図１０（ｄ）に示すように、絶縁層７１とすべきプリプレグ７１Ａを配線層７３側にプレス機を用い積層する。このとき導電性バンプ７４の頭部をプリプレグ７１Ａに貫通させる。この積層工程により、配線層７３はプリプレグ７１Ａ側に沈み込んで位置することになる。なお、図１０（ｄ）における導電性バンプ７４の頭部の破線は、この段階で導電性バンプ７４の頭部を塑性変形させてつぶしておく場合と塑性変形させない場合の両者あり得ることを示す。   Next, as shown in FIG. 10B, the metal foil 73A is patterned in a predetermined pattern with an etchant that can etch only copper using well-known photolithography. Thereby, the wiring layer 73 is formed. Further, as shown in FIG. 3C, conductive bumps 74 are formed at predetermined positions on the wiring layer 73 by screen printing of a conductive plastic paste. Subsequently, as shown in FIG. 10D, a prepreg 71A to be the insulating layer 71 is laminated on the wiring layer 73 side using a press machine. At this time, the head of the conductive bump 74 is made to penetrate the prepreg 71A. By this lamination process, the wiring layer 73 is sunk and positioned on the prepreg 71A side. In addition, the broken line at the head of the conductive bump 74 in FIG. 10D indicates that there are both cases where the head of the conductive bump 74 is plastically deformed and crushed at this stage and when it is not plastically deformed. .

次に、積層されたプリプレグ７１Ａ上に、配線層７２とすべき厚さ例えば１８μｍの金属箔（電解銅箔）７２Ａを配置してプレス機で積層方向に加圧・加熱する。これにより、図１０（ｅ）に示すように、プリプレグ７１Ａが完全に硬化して絶縁層７１となり積層・一体化がされる。このとき金属箔７２Ａは導電性バンプ７４に電気的に接続される。   Next, on the laminated prepreg 71A, a metal foil (electrolytic copper foil) 72A having a thickness of, for example, 18 μm to be used as the wiring layer 72 is disposed and pressed and heated in the laminating direction by a press. As a result, as shown in FIG. 10E, the prepreg 71A is completely cured to become the insulating layer 71 and laminated and integrated. At this time, the metal foil 72A is electrically connected to the conductive bump 74.

次に、金属板１０８Ａ上に所定位置のエッチングレジストを形成する。このエッチングレジストはエッチングによる金属バンプ１０８、１００を形成すべきところに残存させる。そして銅のみをエッチング可能なエッチング液を用いてエッチング加工し、図１０（ｆ）に示すように、金属板のエッチング加工による金属バンプ１０８、１００を形成する。その形状は、エッチングレジストの形状や大きさ、エッチング加工時間によって変わり、一般には積層方向に一致する軸を有しサイドエッチングによりこの軸の方向に径が変化する形状になる。金属バンプ１０８、１００の高さの違いはエッチングレジストの大きさの違いによる。   Next, an etching resist at a predetermined position is formed on the metal plate 108A. This etching resist is left where the metal bumps 108 and 100 are to be formed by etching. Then, etching is performed using an etchant that can etch only copper, and as shown in FIG. 10F, metal bumps 108 and 100 are formed by etching the metal plate. The shape varies depending on the shape and size of the etching resist and the etching processing time. Generally, the shape has an axis that coincides with the stacking direction, and the diameter changes in the direction of this axis by side etching. The difference in height between the metal bumps 108 and 100 is due to the difference in the size of the etching resist.

最後に、形成された金属バンプ１０８、１００をマスクにエッチングストッパ層ＥＳをエッチング除去することにより、図１０（ｇ）に示すような形態の配線板素材を得ることできる。以下は、図８に示した実施形態と同様の製造工程を適用することにより図９に示す部品内蔵配線板を得ることができる。このように層間接続の導電体と部品を接続する導電体とを金属板をエッチングすることにより同時形成することもできる。   Finally, by using the formed metal bumps 108 and 100 as a mask, the etching stopper layer ES is removed by etching to obtain a wiring board material having a form as shown in FIG. In the following, the component built-in wiring board shown in FIG. 9 can be obtained by applying the same manufacturing process as that of the embodiment shown in FIG. As described above, the conductor for connecting the interlayer and the conductor for connecting the components can be simultaneously formed by etching the metal plate.

次に、本発明のさらに別の実施形態に係る部品内蔵配線板について図１１を参照して説明する。図１１は、本発明のさらに別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図であり、すでに説明した図中に示した構成要素と同一または同一相当のものには同一符号を付してある。その部位については加える事項がない限り説明を省略する。   Next, a component built-in wiring board according to still another embodiment of the present invention will be described with reference to FIG. FIG. 11 is a schematic cross-sectional view showing a configuration of a component built-in wiring board according to still another embodiment of the present invention. Components identical or equivalent to those shown in the drawings already described are denoted by the same reference numerals. Is attached. The description of the part is omitted unless there is an additional matter.

この実施形態は、導電性バンプ３８、４０Ａ、３９（図８参照）に代わり、めっきにより形成された金属バンプ１１８、１１０、１１９を有している。このような金属バンプ１１８、１１０、１１９を有する部品内蔵配線板は、例えば次のようにして製造することができる。すなわち、導電性バンプ３８、４０（図４参照）の形成に代えて、めっきのためのパターン化されたレジストを配線層７３（８３）上に形成し、そのレジストの抜けた部分へのめっき成長でバンプを形成する。これ以外の工程は図８に示した部品内蔵配線板の場合と同様である。   This embodiment has metal bumps 118, 110, and 119 formed by plating instead of the conductive bumps 38, 40A, and 39 (see FIG. 8). The component built-in wiring board having such metal bumps 118, 110, and 119 can be manufactured, for example, as follows. That is, instead of forming the conductive bumps 38 and 40 (see FIG. 4), a patterned resist for plating is formed on the wiring layer 73 (83), and plating growth is performed on the portion where the resist is removed. Form bumps with The other steps are the same as those of the component built-in wiring board shown in FIG.

なお、効率的にめっき成長させるため、配線層７３、８３の形成時にその一部として給電パターンを形成しておくのが好ましい。これにより電解めっき工程を適用して効率的な金属バンプ１１８、１１０、１１９の形成ができる。金属バンプ１１８、１００、１１９の形状は、めっきのためのレジストパターン形状に倣って、軸の方向が積層方向に一致する柱状または錐台状の形状（すなわち軸の方向に径が変化するかまたは変化していない形状）になる。金属バンプ１１８と同１１０との高さの違いは、例えばめっき工程を２段階に分け第１段階後に金属バンプ１１０の上部のみに新たなマスクを形成して第２段階のめっき工程を行うようにすれば実現する。   For efficient plating growth, it is preferable to form a power feeding pattern as a part of the wiring layers 73 and 83 when forming them. As a result, it is possible to efficiently form the metal bumps 118, 110, and 119 by applying an electrolytic plating process. The shape of the metal bumps 118, 100, and 119 is a columnar or frustum shape whose axis direction coincides with the stacking direction following the resist pattern shape for plating (that is, the diameter changes in the axis direction or (The shape has not changed). The difference in height between the metal bump 118 and the metal bump 118 is that, for example, the plating process is divided into two stages, and after the first stage, a new mask is formed only on the metal bump 110 and the second stage plating process is performed. It will be realized.

本発明の一実施形態に係る部品内蔵配線板の構成を示す模式的断面図。The typical sectional view showing the composition of the component built-in wiring board concerning one embodiment of the present invention. 図１に示した部品内蔵配線板の製造過程を模式的断面で示す工程図。Process drawing which shows the manufacturing process of the component built-in wiring board shown in FIG. 本発明の別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図。The typical sectional view showing the composition of the component built-in wiring board concerning another embodiment of the present invention. 図３に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図。Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. 3 with a typical cross section. 図３に示した部品内蔵配線板の製造過程の別の一部を模式的断面で示す工程図。FIG. 4 is a process view schematically showing another part of the manufacturing process of the component built-in wiring board shown in FIG. 図３に示した部品内蔵配線板の製造過程のさらに別の一部を模式的断面で示す工程図。FIG. 5 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 3. 本発明のさらに別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図。The typical sectional view showing the composition of the component built-in wiring board concerning another embodiment of the present invention. 本発明のさらに別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図。The typical sectional view showing the composition of the component built-in wiring board concerning another embodiment of the present invention. 本発明のさらに別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図。The typical sectional view showing the composition of the component built-in wiring board concerning another embodiment of the present invention. 図９に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図。Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. 9 with a typical cross section. 本発明のさらに別の実施形態に係る部品内蔵配線板の構成を示す模式的断面図。The typical sectional view showing the composition of the component built-in wiring board concerning another embodiment of the present invention.

符号の説明Explanation of symbols

１…配線板素材、２…配線板素材（コア板）、３…配線板素材、１１…絶縁層、１１Ａ…プリプレグ、１２…配線層（金属配線パターン）、１２Ａ…金属箔（銅箔）、１３…配線層（金属配線パターン）、１３Ａ…金属箔（銅箔）、１４…導電性バンプ（第１の導電体）、１５…導電性バンプ（第２の導電体）、１６…抵抗チップ（電気／電子部品）、３１…絶縁層、３１Ａ…プリプレグ、３２…絶縁層、３３…絶縁層、３３Ａ…プリプレグ、３４…配線層（金属配線パターン）、３４Ａ…金属箔（銅箔）、３５…配線層（金属配線パターン）、３５Ａ…金属箔（銅箔）、３６…配線層（金属配線パターン）、３６Ａ…金属箔（銅箔）、３７…配線層（金属配線パターン）、３７Ａ…金属箔（銅箔）、３８…導電性バンプ（第１の導電体）、３９…導電性バンプ、４０，４０Ａ…導電性バンプ（第２の導電体）、４１…チップ部品（電気／電子部品）、４２…スルーホール導電体、５１…開口部、５２…貫通孔、７１…絶縁層、７１Ａ…プリプレグ、７２…配線層（金属配線パターン）、７２Ａ…金属箔（銅箔）、７３…配線層（金属配線パターン）、７３Ａ…金属箔（銅箔）、７４…導電性バンプ、８１…絶縁層、８２…配線層（金属配線パターン）、８３…配線層（金属配線パターン）、８４…導電性バンプ、９１…ベアチップ半導体、９２…アンダーフィル樹脂、１００…金属板エッチングにより形成された金属バンプ（第２の導電体）、１０８…金属板エッチングにより形成された金属バンプ（第１の導電体）、１０８Ａ…金属板（銅板）、１０９…金属板エッチングにより形成された金属バンプ、１１０…めっきにより形成された金属バンプ（第２の導電体）、１１８…めっきにより形成された金属バンプ（第１の導電体）、１１９…めっきにより形成された金属バンプ、ＥＳ…エッチングストッパ層。   DESCRIPTION OF SYMBOLS 1 ... Wiring board material, 2 ... Wiring board material (core board), 3 ... Wiring board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Wiring layer (metal wiring pattern), 12A ... Metal foil (copper foil), 13 ... Wiring layer (metal wiring pattern), 13A ... Metal foil (copper foil), 14 ... Conductive bump (first conductor), 15 ... Conductive bump (second conductor), 16 ... Resistor chip ( Electrical / electronic parts), 31 ... insulating layer, 31A ... prepreg, 32 ... insulating layer, 33 ... insulating layer, 33A ... prepreg, 34 ... wiring layer (metal wiring pattern), 34A ... metal foil (copper foil), 35 ... Wiring layer (metal wiring pattern), 35A ... metal foil (copper foil), 36 ... wiring layer (metal wiring pattern), 36A ... metal foil (copper foil), 37 ... wiring layer (metal wiring pattern), 37A ... metal foil (Copper foil), 38 ... conductive bump (first conductor), DESCRIPTION OF SYMBOLS 9 ... Conductive bump, 40, 40A ... Conductive bump (2nd conductor), 41 ... Chip component (electric / electronic component), 42 ... Through-hole conductor, 51 ... Opening part, 52 ... Through-hole, 71 ... Insulating layer, 71A ... Prepreg, 72 ... Wiring layer (metal wiring pattern), 72A ... Metal foil (copper foil), 73 ... Wiring layer (metal wiring pattern), 73A ... Metal foil (copper foil), 74 ... Conductivity Bump, 81 ... insulating layer, 82 ... wiring layer (metal wiring pattern), 83 ... wiring layer (metal wiring pattern), 84 ... conductive bump, 91 ... bare chip semiconductor, 92 ... underfill resin, 100 ... by metal plate etching Formed metal bump (second conductor), 108... Metal bump formed by metal plate etching (first conductor), 108 A... Metal plate (copper plate), 109. Metal bumps formed, 110 ... Metal bumps formed by plating (second conductor), 118 ... Metal bumps formed by plating (first conductor), 119 ... Metal bumps formed by plating, ES: Etching stopper layer.

Claims (17)

絶縁層と、
前記絶縁層を貫通する第１の導電体と、
前記絶縁層の上面および下面に設けられ、前記第１の導電体に電気的導通する第１および第２の配線層と、
前記絶縁層に少なくとも一部が埋め込まれて設けられた電気／電子部品と、
前記電気／電子部品の端子と前記第１または第２の配線層とを電気的・機械的に接続し、かつ、前記第１の導電体と同じ組成材料からなる第２の導電体と
を具備することを特徴とする部品内蔵配線板。 An insulating layer;
A first conductor penetrating the insulating layer;
First and second wiring layers provided on an upper surface and a lower surface of the insulating layer and electrically conducting to the first conductor;
An electrical / electronic component provided at least partially embedded in the insulating layer;
A second conductor made of the same composition material as the first conductor, electrically and mechanically connecting the terminal of the electric / electronic component and the first or second wiring layer; A wiring board with a built-in component. 前記第１の導電体が、導電性組成物からなり、かつ、層方向に一致する軸を有し前記軸の方向に径が変化している形状であることを特徴とする請求項１記載の部品内蔵配線板。   2. The first conductor according to claim 1, wherein the first conductor is made of a conductive composition and has a shape that has an axis that coincides with a layer direction and a diameter that changes in the direction of the axis. Component built-in wiring board. 前記第１の導電体が、金属からなり、かつ、層方向に一致する軸を有し前記軸の方向に径が変化している形状であることを特徴とする請求項１記載の部品内蔵配線板。   2. The component built-in wiring according to claim 1, wherein the first conductor is made of a metal and has a shape that has an axis that coincides with a layer direction and has a diameter that changes in the direction of the axis. Board. 前記第１の導電体が、金属からなり、かつ、層方向に一致する軸を有し前記軸の方向に径が変化していない形状であることを特徴とする請求項１記載の部品内蔵配線板。   2. The component built-in wiring according to claim 1, wherein the first conductor is made of metal and has a shape that has an axis that coincides with a layer direction and has a diameter that does not change in the direction of the axis. Board. 前記第１および第２の導電体と、前記電気／電子部品が接続された前記第１または第２の配線層との間に前記第１の導電体とは異なる材料の層をさらに具備することを特徴とする請求項１記載の部品内蔵配線板。   A layer of a material different from that of the first conductor is further provided between the first and second conductors and the first or second wiring layer to which the electric / electronic component is connected. The component built-in wiring board according to claim 1. 前記第２の導電体の前記第１または第２の配線層に接する面積が、前記第１の導電体の該第１または第２の配線層に接する面積より小さいことを特徴とする請求項１記載の部品内蔵配線板。   2. The area of the second conductor in contact with the first or second wiring layer is smaller than the area of the first conductor in contact with the first or second wiring layer. Wiring board with built-in components. 前記電気／電子部品が、ベアチップ半導体であることを特徴とする請求項１記載の部品内蔵配線板。   2. The component built-in wiring board according to claim 1, wherein the electric / electronic component is a bare chip semiconductor. 前記第２の導電体が、前記ベアチップ半導体を前記第１または第２の配線層にフリップチップ接続する導電体であることを特徴とする請求項７記載の部品内蔵配線板。   8. The component built-in wiring board according to claim 7, wherein the second conductor is a conductor for flip-chip connecting the bare chip semiconductor to the first or second wiring layer. 第１の金属箔上または第１の金属配線パターンを有する第１の絶縁層の前記第１の金属配線パターン上に、第１の導電性バンプと、該第１の導電性バンプより高さが低くかつ該第１の導電性バンプと同じ材料からなる第２の導電性バンプとを形成する第１の工程と、
前記形成された第２の導電性バンプを介するように、前記第１の金属箔上または前記第１の絶縁層の前記第１の金属配線パターン上に電気／電子部品をマウントする第２の工程と、
前記形成された第１の導電性バンプが貫通するように前記第１の金属箔上または前記第１の絶縁層の前記第１の金属配線パターン上に第２の絶縁層を積層する第３の工程と、
前記第２の絶縁層を貫通した前記第１の導電性バンプの頭部を変形させこれと電気的導通を得るように、前記積層された第２の絶縁層上に、第２の金属箔を積層・一体化または第２の金属配線パターンを有する第３の絶縁層を積層・一体化する第４の工程と
を具備することを特徴とする部品内蔵配線板の製造方法。 On the first metal foil or on the first metal wiring pattern of the first insulating layer having the first metal wiring pattern, a first conductive bump and a height higher than the first conductive bump. Forming a second conductive bump that is low and made of the same material as the first conductive bump;
Second step of mounting an electric / electronic component on the first metal foil or on the first metal wiring pattern of the first insulating layer through the formed second conductive bump. When,
A second insulating layer is laminated on the first metal foil or the first metal wiring pattern of the first insulating layer so that the formed first conductive bump penetrates. Process,
A second metal foil is formed on the laminated second insulating layer so as to deform the head of the first conductive bump penetrating the second insulating layer and obtain electrical conduction therewith. And a fourth step of laminating and integrating a third insulating layer having a second metal wiring pattern. 4. A method of manufacturing a component built-in wiring board, comprising: 前記第１の工程が、前記第１の導電性バンプと前記第２の導電性バンプとを同時形成することを特徴とする請求項９記載の部品内蔵配線板の製造方法。   10. The method for manufacturing a component built-in wiring board according to claim 9, wherein the first step forms the first conductive bump and the second conductive bump simultaneously. 前記第１の工程が、前記第１の導電性バンプと前記第２の導電性バンプとを導電性組成物のスクリーン印刷により同時形成することを特徴とする請求項１０記載の部品内蔵配線板の製造方法。   11. The component built-in wiring board according to claim 10, wherein in the first step, the first conductive bump and the second conductive bump are simultaneously formed by screen printing of a conductive composition. Production method. 前記第１の工程が、前記スクリーン印刷のため径の異なる２種のピットを有するスクリーン板を用いてなされることを特徴とする請求項１１記載の部品内蔵配線板の製造方法。   12. The method of manufacturing a component built-in wiring board according to claim 11, wherein the first step is performed using a screen board having two types of pits having different diameters for the screen printing. 前記第２の工程が、前記導電性組成物をスクリーン印刷することにより形成された前記第２の導電性バンプが硬化する前になされることを特徴とする請求項１１記載の部品内蔵配線板の製造方法。   12. The component built-in wiring board according to claim 11, wherein the second step is performed before the second conductive bump formed by screen printing the conductive composition is cured. Production method. 前記第２の工程が、前記導電性組成物をスクリーン印刷することにより形成された前記第２の導電性バンプが硬化した後になされることを特徴とする請求項１１記載の部品内蔵配線板の製造方法。   12. The component built-in wiring board according to claim 11, wherein the second step is performed after the second conductive bumps formed by screen printing the conductive composition are cured. Method. 前記第１の工程が、前記第１の導電性バンプと前記第２の導電性バンプとを金属めっき工程により同時形成することを特徴とする請求項１０記載の部品内蔵配線板の製造方法。   11. The method of manufacturing a component built-in wiring board according to claim 10, wherein in the first step, the first conductive bump and the second conductive bump are simultaneously formed by a metal plating step. 前記第１の工程が、前記第１の導電性バンプと前記第２の導電性バンプとを金属板のエッチングにより同時形成することを特徴とする請求項１０記載の部品内蔵配線板の製造方法。   11. The method of manufacturing a component built-in wiring board according to claim 10, wherein in the first step, the first conductive bump and the second conductive bump are simultaneously formed by etching a metal plate. 前記第２の工程が、前記第１および第２の導電性バンプが前記第１の金属箔上に形成されている場合に、前記第１の金属箔を真空吸着によりステージ上に固定してなされることを特徴とする請求項９記載の部品内蔵配線板の製造方法。   The second step is performed by fixing the first metal foil on the stage by vacuum suction when the first and second conductive bumps are formed on the first metal foil. The method of manufacturing a component built-in wiring board according to claim 9.
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