JP5572531B2 - Manufacturing method of highly reliable semiconductor device - Google Patents

Manufacturing method of highly reliable semiconductor device Download PDF

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JP5572531B2
JP5572531B2 JP2010274956A JP2010274956A JP5572531B2 JP 5572531 B2 JP5572531 B2 JP 5572531B2 JP 2010274956 A JP2010274956 A JP 2010274956A JP 2010274956 A JP2010274956 A JP 2010274956A JP 5572531 B2 JP5572531 B2 JP 5572531B2
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JP2012138385A (en
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いく子 小笠原
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Shindengen Electric Manufacturing Co Ltd
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本発明は、高信頼性半導体装置の製造方法に関するものである。 The present invention relates to a method for manufacturing a highly reliable semiconductor device.

従来、高信頼性半導体装置としては、メサプレーナー構造の高信頼性半導体装置が知られている（例えば、特許文献１参照）。
図８は、従来のメサプレーナー構造の高信頼性半導体装置の一例を示す平面図、図９は図８のＡ−Ａ線に沿う断面図であり、ｎ型シリコン基板２に、ｐ型拡散層からなるベース層３、アルミニウム等の導電体からなる電極５が順次積層され、ｎ型シリコン基板２及びベース層３により形成されたｐｎ接合６の周縁部には、ｐｎ接合６の端部を露出する溝７が形成され、この溝７にはガラス膜８が施されている。
溝７の底部は、ベース層３の底部より深くなるように形成されている。 Conventionally, as a highly reliable semiconductor device, a highly reliable semiconductor device having a mesa planar structure is known (see, for example, Patent Document 1).
FIG. 8 is a plan view showing an example of a highly reliable semiconductor device having a conventional mesa planar structure. FIG. 9 is a cross-sectional view taken along the line AA of FIG. 8, and a p-type diffusion layer is formed on the n-type silicon substrate 2. A base layer 3 made of aluminum and an electrode 5 made of a conductor such as aluminum are sequentially stacked, and an end of the pn junction 6 is exposed at the peripheral edge of the pn junction 6 formed by the n-type silicon substrate 2 and the base layer 3. A groove 7 is formed, and a glass film 8 is applied to the groove 7.
The bottom of the groove 7 is formed deeper than the bottom of the base layer 3.

特開平６−３４２９０２号公報JP-A-6-342902

ところで、従来の高信頼性半導体装置１では、逆方向バイアス試験を行った場合に、溝７の角部（図８中、Ａ領域）に電界が集中し易く、場合によっては破壊に至る虞があった。これは、ｐｎ接合６の溝７の角部近傍における耐圧が、溝７の直線部における耐圧より低下することによるためで、高比抵抗を用いた高信頼性半導体装置１にて顕著に現れる現象である。
そこで、この現象を回避するために、溝７の角部の曲率半径を大きくする（ゆるいカーブにする）ことで、溝７の角部の電界を緩和することが行われているが、溝７の角部の曲率半径と損失との間にはトレードオフの関係があり、したがって、溝７の角部の曲率半径を大きくすると、ｐｎ接合６における整流面積が小さくなる。逆に、溝７の角部の曲率半径を小さくすると、面積は大きくなるが、電界が集中し易くなる。 By the way, in the conventional highly reliable semiconductor device 1, when a reverse bias test is performed, an electric field tends to concentrate on the corner portion (A region in FIG. 8) of the groove 7, and in some cases, there is a risk of destruction. there were. This is because the withstand voltage in the vicinity of the corner of the groove 7 of the pn junction 6 is lower than the withstand voltage in the straight portion of the groove 7, and thus a phenomenon that appears remarkably in the highly reliable semiconductor device 1 using a high specific resistance. It is.
Therefore, in order to avoid this phenomenon, the electric field at the corner of the groove 7 is reduced by increasing the radius of curvature of the corner of the groove 7 (by using a gentle curve). There is a trade-off relationship between the radius of curvature of the corner and the loss. Therefore, when the radius of curvature of the corner of the groove 7 is increased, the rectification area at the pn junction 6 is reduced. Conversely, when the radius of curvature of the corner of the groove 7 is reduced, the area increases, but the electric field tends to concentrate.

本発明は、上記の課題を解決するためになされたものであって、逆方向バイアス試験を行った場合においても、ｐｎ接合の周縁部に形成された溝の角部と直線部とに電界が分散されることで、溝の角部に電界が集中する虞が無く、したがって、耐圧向上及び信頼性向上と低損失とを両立させることが可能な高信頼性半導体装置の製造方法を提供することを目的とする。 The present invention has been made in order to solve the above-described problem, and even when a reverse bias test is performed, an electric field is generated between the corner and the straight portion of the groove formed in the peripheral portion of the pn junction. by being dispersed, there is no possibility that the electric field is concentrated on the corner portion of the groove, thus, to provide a method for manufacturing a highly reliable semiconductor device capable of achieving both improvement in breakdown voltage and reliability and low loss With the goal.

本発明者は、上記の課題を解決するために鋭意検討を重ねた結果、第１の導電型の半導体基板の一主面に第２の導電型の半導体層が形成され、前記第１の導電型の半導体基板及び前記第２の導電型の半導体層により形成されたｐｎ接合の周縁部に前記ｐｎ接合の端部を露出する溝を形成してなる高信頼性半導体装置において、前記溝は、複数の直線部と複数の角部とからなり、前記角部の深さを、前記直線部の深さより深くした構成とすれば、溝の角部における耐圧が直線部における耐圧より高くなる、あるいは、溝の角部の耐圧と直線部の耐圧とが略一致することとなり、よって、逆方向バイアス試験を行った場合においても、印加される電界は溝の角部と直線部あるいは直線部に分散されることとなり、したがって、溝の角部に電界が集中する虞が無いことを見出し、さらに、第１の導電型の半導体基板及び第２の導電型の半導体層により形成されたｐｎ接合における整流面積が小さくならないので、損失が増加する虞もなく、その結果、耐圧及び信頼性の向上と低損失を両立させることが可能になることを見出し、本発明を完成するに至った。   As a result of intensive studies in order to solve the above problems, the present inventor has formed a second conductivity type semiconductor layer on one main surface of the first conductivity type semiconductor substrate, and the first conductivity type In the highly reliable semiconductor device in which a groove exposing an end portion of the pn junction is formed in a peripheral portion of the pn junction formed by the semiconductor substrate of the type and the semiconductor layer of the second conductivity type, If the structure is composed of a plurality of straight portions and a plurality of corner portions, and the depth of the corner portions is made deeper than the depth of the straight portion, the withstand voltage at the corner portions of the grooves is higher than the withstand pressure at the straight portions, or Therefore, the withstand voltage at the corners of the grooves and the withstand voltage at the straight line portions substantially coincide with each other. Therefore, even when the reverse bias test is performed, the applied electric field is distributed to the corners of the groove and the straight or straight portions. Therefore, the electric field is concentrated at the corner of the groove. In addition, since the rectification area in the pn junction formed by the first conductive type semiconductor substrate and the second conductive type semiconductor layer is not reduced, there is no risk of increasing the loss. As a result, it has been found that it is possible to achieve both improvement in breakdown voltage and reliability and low loss, and the present invention has been completed.

請求項１記載の高信頼性半導体装置の製造方法は、第１の導電型の半導体基板の一主面に第２の導電型の半導体層が形成され、前記第１の導電型の半導体基板及び前記第２の導電型の半導体層により形成されたｐｎ接合の周縁部に前記ｐｎ接合の端部を露出する溝を形成してなり、前記溝は、複数の直線部と複数の角部とからなる高信頼性半導体装置の製造方法において、前記ｐｎ接合の周縁部の角部を選択除去する工程と、前記角部を含む前記ｐｎ接合の周縁部を選択除去することにより、前記ｐｎ接合部の周縁部に前記溝を形成するとともに、前記溝の角部の深さを、前記溝の直線部の深さより深くする工程と、を有することを特徴とする。 The method of manufacturing a highly reliable semiconductor device according to claim 1 , wherein a second conductive type semiconductor layer is formed on one main surface of the first conductive type semiconductor substrate, and the first conductive type semiconductor substrate and A groove that exposes an end portion of the pn junction is formed in a peripheral portion of the pn junction formed by the semiconductor layer of the second conductivity type, and the groove includes a plurality of linear portions and a plurality of corner portions. In the method for manufacturing a highly reliable semiconductor device, the step of selectively removing the corner portion of the peripheral portion of the pn junction, and the step of selectively removing the peripheral portion of the pn junction including the corner portion, Forming the groove on the peripheral edge, and making the depth of the corner of the groove deeper than the depth of the linear part of the groove.

この高信頼性半導体装置の製造方法では、ｐｎ接合の周縁部の角部を選択除去する工程と、角部を含むｐｎ接合の周縁部を選択除去することにより、ｐｎ接合部の周縁部に溝を形成するとともに、溝の角部の深さを、溝の直線部の深さより深くする工程と、を有することにより、ｐｎ接合の周縁部に、角部の深さを直線部の深さより深くした溝を形成することが可能になる。よって、耐圧及び信頼性の向上と低損失を両立させることが可能な高信頼性半導体装置を得ることが可能である。   In this method of manufacturing a highly reliable semiconductor device, the step of selectively removing the corner portion of the pn junction and the peripheral portion of the pn junction including the corner portion are selectively removed, thereby forming a groove in the periphery of the pn junction portion. And the step of making the depth of the corner of the groove deeper than the depth of the straight portion of the groove, the depth of the corner is deeper than the depth of the straight portion at the periphery of the pn junction. It is possible to form a groove. Therefore, it is possible to obtain a highly reliable semiconductor device capable of achieving both improvement in breakdown voltage and reliability and low loss.

請求項２記載の高信頼性半導体装置の製造方法は、第１の導電型の半導体基板の一主面に第２の導電型の半導体層が形成され、前記第１の導電型の半導体基板及び前記第２の導電型の半導体層により形成されたｐｎ接合の周縁部に前記ｐｎ接合の端部を露出する溝を形成してなり、前記溝は、複数の直線部と複数の角部とからなる高信頼性半導体装置の製造方法において、レーザの出力を変化させて前記ｐｎ接合の周縁部を選択除去することにより、前記溝の角部の深さを前記溝の直線部の深さより深くする工程を有することを特徴とする。 3. The method for manufacturing a highly reliable semiconductor device according to claim 2, wherein a second conductive type semiconductor layer is formed on one main surface of the first conductive type semiconductor substrate, and the first conductive type semiconductor substrate and A groove that exposes an end portion of the pn junction is formed in a peripheral portion of the pn junction formed by the semiconductor layer of the second conductivity type, and the groove includes a plurality of linear portions and a plurality of corner portions. In the method for manufacturing a highly reliable semiconductor device, the depth of the corner of the groove is made deeper than the depth of the linear portion of the groove by changing the laser output and selectively removing the peripheral portion of the pn junction. It has the process.

この高信頼性半導体装置の製造方法では、レーザの出力を変化させてｐｎ接合の周縁部を選択除去し、溝の角部の深さを溝の直線部の深さより深くすることにより、ｐｎ接合の周縁部に、角部の深さを直線部の深さより深くした溝を形成することが可能になる。よって、耐圧及び信頼性の向上と低損失を両立させることが可能な高信頼性半導体装置を得ることが可能である。   In this method of manufacturing a highly reliable semiconductor device, the peripheral portion of the pn junction is selectively removed by changing the output of the laser, and the depth of the corner of the groove is made deeper than the depth of the straight portion of the groove, thereby making the pn junction It is possible to form a groove having a corner portion deeper than the straight portion. Therefore, it is possible to obtain a highly reliable semiconductor device capable of achieving both improvement in breakdown voltage and reliability and low loss.

請求項１記載の高信頼性半導体装置の製造方法によれば、ｐｎ接合の周縁部の角部を選択除去する工程と、前記角部を含む前記ｐｎ接合の周縁部を選択除去することにより、前記ｐｎ接合部の周縁部に前記溝を形成するとともに、前記溝の角部の深さを、前記溝の直線部の深さより深くする工程とを有するので、ｐｎ接合の周縁部に、角部の深さを直線部の深さより深くした溝を容易に形成することができる。したがって、耐圧及び信頼性の向上と低損失を両立させた高信頼性半導体装置を容易に得ることができる。 According to the method for manufacturing a highly reliable semiconductor device according to claim 1, by selectively removing a corner portion of the peripheral portion of the pn junction and selectively removing the peripheral portion of the pn junction including the corner portion, Forming the groove in the peripheral portion of the pn junction and making the depth of the corner of the groove deeper than the straight portion of the groove. It is possible to easily form a groove whose depth is deeper than the straight portion. Therefore, it is possible to easily obtain a highly reliable semiconductor device that achieves both improved breakdown voltage and reliability and low loss.

請求項２記載の高信頼性半導体装置の製造方法によれば、レーザの出力を変化させてｐｎ接合の周縁部を選択除去することにより、溝の角部の深さを直線部の深さより深くする工程を有するので、ｐｎ接合の周縁部に、角部の深さを直線部の深さより深くした溝を容易に形成することができる。したがって、耐圧及び信頼性の向上と低損失を両立させた高信頼性半導体装置を容易に得ることができる。 According to the method for manufacturing a highly reliable semiconductor device according to claim 2, by changing the laser output and selectively removing the peripheral portion of the pn junction, the depth of the corner of the groove is made deeper than the depth of the straight portion. Therefore, a groove having a corner portion deeper than a straight portion can be easily formed in the peripheral portion of the pn junction. Therefore, it is possible to easily obtain a highly reliable semiconductor device that achieves both improved breakdown voltage and reliability and low loss.

本発明の第１の実施形態の高信頼性半導体装置を示す平面図である。1 is a plan view showing a highly reliable semiconductor device according to a first embodiment of the present invention. 図１のＢ−Ｂ線に沿う断面図である。It is sectional drawing which follows the BB line of FIG. 本発明の第１の実施形態の高信頼性半導体装置の製造方法を示す過程図である。It is process drawing which shows the manufacturing method of the highly reliable semiconductor device of the 1st Embodiment of this invention. 本発明の第２の実施形態の高信頼性半導体装置を示す平面図である。It is a top view which shows the highly reliable semiconductor device of the 2nd Embodiment of this invention. 図４のＣ−Ｃ線に沿う断面図である。It is sectional drawing which follows the CC line of FIG. 本発明の第２の実施形態の高信頼性半導体装置の製造方法を示す過程図である。It is process drawing which shows the manufacturing method of the highly reliable semiconductor device of the 2nd Embodiment of this invention. 本発明の第３の実施形態の高信頼性半導体装置を示す部分断面図である。It is a fragmentary sectional view which shows the highly reliable semiconductor device of the 3rd Embodiment of this invention. 従来の高信頼性半導体装置の一例を示す平面図である。It is a top view which shows an example of the conventional highly reliable semiconductor device. 図８のＡ−Ａ線に沿う断面図である。It is sectional drawing which follows the AA line of FIG.

本発明の高信頼性半導体装置及びその製造方法を実施するための形態について説明する。
なお、この形態は、発明の趣旨をより良く理解させるために具体的に説明するものであり、特に指定のない限り、本発明を限定するものではない。 An embodiment for carrying out a highly reliable semiconductor device and a method for manufacturing the same according to the present invention will be described.
This embodiment is specifically described for better understanding of the gist of the invention, and does not limit the present invention unless otherwise specified.

［第１の実施形態］
図１は、本発明の第１の実施形態の高信頼性半導体装置を示す平面図、図２は図１のＢ−Ｂ線に沿う断面図である。
図１において、符号１１はメサプレーナー構造の高信頼性半導体装置であり、ｎ型シリコン基板（第１の導電型の半導体基板）１２の表面（一主面）１２ａに、ｐ型拡散層からなるベース層（第２の導電型の半導体層）１３、Ａｌ、Ｃｕ、Ｐｄ等の導電体からなる電極１５が順次積層され、ｎ型シリコン基板１２及びベース層１３により形成された平面視略正方形状のｐｎ接合１６の周縁部には、ｐｎ接合１６の端部を露出する溝１７が形成され、この溝１７の内面にはパッシベーション膜となるガラス膜１８が施されている。 [First Embodiment]
FIG. 1 is a plan view showing a highly reliable semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line BB of FIG.
In FIG. 1, reference numeral 11 denotes a highly reliable semiconductor device having a mesa planar structure, and includes a p-type diffusion layer on a surface (one main surface) 12 a of an n-type silicon substrate (first conductive semiconductor substrate) 12. A base layer (second conductivity type semiconductor layer) 13 and an electrode 15 made of a conductor such as Al, Cu, Pd, etc. are sequentially stacked, and are formed in a substantially square shape in plan view formed by the n-type silicon substrate 12 and the base layer 13. A groove 17 exposing the end of the pn junction 16 is formed at the peripheral edge of the pn junction 16, and a glass film 18 serving as a passivation film is applied to the inner surface of the groove 17.

溝１７は、ｐｎ接合１６の平面視略正方形状の各辺に沿って形成された長尺の直線部２１〜２４と、この平面視略正方形状の各角に形成された角部３１〜３４とにより構成されている。これら直線部２１〜２４及び角部３１〜３４を交互に配置することにより全体形状がロの字形の溝１７となっている。
角部３１〜３４の深さｄ２は、ｐｎ接合１６のｎ型シリコン基板１２の表面１２ａからの深さより深く、すなわち、ベース層１３の厚みより大きく、したがって、直線部２１〜２４の深さｄ１より深くなっている。 The groove 17 includes long straight portions 21 to 24 formed along the sides of the pn junction 16 that are substantially square in plan view, and corners 31 to 34 that are formed at the corners of the substantially square shape in plan view. It is comprised by. By alternately arranging the straight portions 21 to 24 and the corner portions 31 to 34, a groove 17 having a square shape as a whole is formed.
The depth d 2 of the corners 31 to 34, deeper than the depth from the surface 12a of the n-type silicon substrate 12 of the pn junction 16, i.e., greater than the thickness of the base layer 13, thus, the depth of the straight portions 21 to 24 It is deeper than d 1.

この溝１７では、角部３１〜３４の幅と直線部２１〜２４の幅とが一致するように、角部３１〜３４における外側の内壁の曲率半径は、内側の内壁の曲率半径より大きくなっている。   In the groove 17, the curvature radius of the outer inner wall at the corner portions 31 to 34 is larger than the curvature radius of the inner inner wall so that the width of the corner portions 31 to 34 and the width of the straight portions 21 to 24 coincide. ing.

一般に、半導体装置では、電界が印加された場合の溝１７における耐圧は、深さが深い程高くなる。
この高信頼性半導体装置１１では、ｐｎ接合１６の周縁部に形成された溝１７を、直線部２１〜２４と、深さが直線部２１〜２４より深い角部３１〜３４とにより構成したことにより、逆方向バイアス試験を行った場合においても、溝１７の角部３１〜３４における耐圧が直線部２１〜２４における耐圧より高くなり、その結果、電界は溝１７の角部３１〜３４に集中することなく、溝１７の角部３１〜３４と直線部２１〜２４とに分散されることとなり、よって、耐圧が向上し、電界による破壊が生じ難くなる。 Generally, in a semiconductor device, the breakdown voltage in the groove 17 when an electric field is applied increases as the depth increases.
In this highly reliable semiconductor device 11, the groove 17 formed in the peripheral portion of the pn junction 16 is configured by the straight portions 21 to 24 and the corner portions 31 to 34 whose depth is deeper than the straight portions 21 to 24. Thus, even when the reverse bias test is performed, the breakdown voltage at the corners 31 to 34 of the groove 17 is higher than the breakdown voltage at the straight portions 21 to 24, and as a result, the electric field is concentrated on the corners 31 to 34 of the groove 17. Without being done, it is dispersed in the corners 31 to 34 and the straight portions 21 to 24 of the groove 17, so that the breakdown voltage is improved and the breakdown due to the electric field is less likely to occur.

また、ｎ型シリコン基板１２におけるｐｎ接合１６の占有面積が変わらずに、溝１７の角部３１〜３４の深さのみが深くなるので、高信頼性半導体装置１１としての損失も増加しない。
これにより、耐圧の向上と低損失を両立させることが可能になる。 Further, since the area occupied by the pn junction 16 in the n-type silicon substrate 12 does not change and only the depths of the corners 31 to 34 of the groove 17 are increased, the loss as the highly reliable semiconductor device 11 does not increase.
This makes it possible to achieve both improvement in breakdown voltage and low loss.

次に、この高信頼性半導体装置１１の製造方法について、図３に基づき説明する。
まず、図３（ａ）に示すように、ｎ型シリコン基板１２の表面の所定位置にベース層１３が形成されたウェーハ４１を用意する。
次いで、ウェーハ４１の表面全面にレジスト４２を塗布し、露光及び現像を行い、レジスト４２のうち形成すべき溝１７の角部３１〜３４に対応する位置に開口４２ａを形成する。 Next, a method for manufacturing the highly reliable semiconductor device 11 will be described with reference to FIG.
First, as shown in FIG. 3A, a wafer 41 having a base layer 13 formed at a predetermined position on the surface of the n-type silicon substrate 12 is prepared.
Next, a resist 42 is applied to the entire surface of the wafer 41, exposed and developed, and openings 42a are formed in the resist 42 at positions corresponding to the corners 31 to 34 of the grooves 17 to be formed.

次いで、図３（ｂ）に示すように、開口４２ａが形成されたレジスト４２をマスクとして、ウェーハ４１をウェットエッチングし、ウェーハ４１の表面４１ａのうち角部３１〜３４に対応する位置に、それぞれ凹部４３を形成する。これら凹部４３の深さは、後述する第２のウェットエッチングによるエッチング深さとの和が角部３１〜３４の所望の深さとなるように設定すればよい。
その後、レジスト４２を剥離する。 Next, as shown in FIG. 3B, the wafer 41 is wet-etched using the resist 42 in which the opening 42a is formed as a mask, and at positions corresponding to the corners 31 to 34 on the surface 41a of the wafer 41, respectively. A recess 43 is formed. What is necessary is just to set the depth of these recessed parts 43 so that the sum with the etching depth by the 2nd wet etching mentioned later may become the desired depth of the corner | angular parts 31-34.
Thereafter, the resist 42 is peeled off.

次いで、図３（ｃ）に示すように、ウェーハ４１の表面４１ａのうち溝１７に対応する位置を、開口４４ａが形成されたマスク４４を用いてウェットエッチングする。
ここでは、ウェーハ４１の表面４１ａのうち直線部２１〜２４に対応する位置に、所望の深さの直線部２１〜２４が形成されるように、ウェットエッチングのエッチングレートを調整する。 Next, as shown in FIG. 3C, the position corresponding to the groove 17 in the surface 41a of the wafer 41 is wet-etched using a mask 44 in which an opening 44a is formed.
Here, the etching rate of the wet etching is adjusted so that the straight portions 21 to 24 having a desired depth are formed at positions corresponding to the straight portions 21 to 24 on the surface 41 a of the wafer 41.

これにより、ウェーハ４１の表面４１ａには、所望の深さの直線部２１〜２４が形成されるとともに、凹部４３には、これら凹部４３の深さと直線部２１〜２４の深さとの和を所望の深さとする角部３１〜３４が形成される。したがって、ウェーハ４１の表面４１ａには、直線部２１〜２４と、深さが直線部２１〜２４より深くかつｐｎ接合１６の端部を露出する角部３１〜３４とからなる略ロの字状の溝１７が形成されることとなる。
その後、マスク４４を除去する。 Thus, the straight portions 21 to 24 having a desired depth are formed on the surface 41 a of the wafer 41, and the sum of the depth of the concave portions 43 and the depth of the straight portions 21 to 24 is desired in the concave portion 43. Corner portions 31 to 34 having a depth of are formed. Therefore, the front surface 41a of the wafer 41 has a substantially square shape including straight portions 21 to 24 and corner portions 31 to 34 having a depth deeper than the straight portions 21 to 24 and exposing the end portions of the pn junction 16. The groove 17 is formed.
Thereafter, the mask 44 is removed.

次いで、図３（ｄ）に示すように、溝１７の内面にパッシベーション膜となるガラス膜１８を形成する。
次いで、ウェーハ４１の表面４１ａの所定位置に、蒸着法や無電界めっき法によりＡｌ、Ｃｕ、Ｐｄ、Ｎｉ等の電極用金属を堆積させ、電極１５を形成する。
以上により、本実施形態のメサプレーナー構造の高信頼性半導体装置１１を作製することができる。 Next, as shown in FIG. 3D, a glass film 18 serving as a passivation film is formed on the inner surface of the groove 17.
Next, an electrode metal such as Al, Cu, Pd, or Ni is deposited at a predetermined position on the surface 41 a of the wafer 41 by vapor deposition or electroless plating to form the electrode 15.
As described above, the highly reliable semiconductor device 11 having the mesa planar structure of this embodiment can be manufactured.

本実施形態のメサプレーナー構造の高信頼性半導体装置１１によれば、ｎ型シリコン基板１２及びベース層１３により形成されたｐｎ接合１６の周縁部に、長尺の直線部２１〜２４と、深さが直線部２１〜２４より深い角部３１〜３４とにより構成される溝１７を形成したので、溝１７の角部３１〜３４における耐圧を直線部２１〜２４における耐圧より高くすることができ、したがって、電界を溝１７の角部３１〜３４に集中することなく、溝１７の角部３１〜３４と直線部２１〜２４とに分散させることができ、その結果、耐圧及び信頼性を向上させることができ、電界による破壊を防止することができる。   According to the highly reliable semiconductor device 11 having the mesa planar structure of the present embodiment, the long straight portions 21 to 24 and the deep portions of the pn junction 16 formed by the n-type silicon substrate 12 and the base layer 13 are formed on the periphery. Since the groove 17 constituted by the corner portions 31 to 34 deeper than the straight portions 21 to 24 is formed, the withstand voltage at the corner portions 31 to 34 of the groove 17 can be made higher than the withstand pressure at the straight portions 21 to 24. Therefore, the electric field can be distributed to the corners 31 to 34 and the straight portions 21 to 24 of the groove 17 without concentrating on the corners 31 to 34 of the groove 17, thereby improving the breakdown voltage and the reliability. And can be prevented from being broken by an electric field.

また、ｐｎ接合１６における整流面積が変わらずに溝１７の角部３１〜３４の深さのみが深くなるので、高信頼性半導体装置１１としての損失が増加する虞はない。
以上により、耐圧及び信頼性の向上と低損失を両立させた高信頼性半導体装置１１を提供することができる。 In addition, since the rectification area in the pn junction 16 is not changed and only the depths of the corner portions 31 to 34 of the groove 17 are increased, there is no possibility that the loss as the highly reliable semiconductor device 11 is increased.
As described above, it is possible to provide the highly reliable semiconductor device 11 that achieves both improved breakdown voltage and reliability and low loss.

本実施形態のメサプレーナー構造の高信頼性半導体装置１１の製造方法によれば、レジスト４２をマスクとして、ウェーハ４１をウェットエッチングし、ウェーハ４１の表面４１ａのうち角部３１〜３４に対応する位置にそれぞれ凹部４３を形成し、次いで、開口４４ａが形成されたマスク４４を用いてウェットエッチングするので、ウェーハ４１の表面４１ａに、直線部２１〜２４と、深さが直線部２１〜２４より深くかつｐｎ接合１６の端部を露出する角部３１〜３４とからなる溝１７を容易に形成することができる。
したがって、耐圧及び信頼性の向上と低損失を両立させた高信頼性半導体装置１１を容易に作製することができる。 According to the method for manufacturing the highly reliable semiconductor device 11 having the mesa planar structure of the present embodiment, the wafer 41 is wet-etched using the resist 42 as a mask, and the positions corresponding to the corner portions 31 to 34 in the surface 41 a of the wafer 41. The recesses 43 are respectively formed in the wafer 41, and then wet etching is performed using the mask 44 in which the openings 44a are formed, so that the straight portions 21 to 24 and the depth are deeper than the straight portions 21 to 24 on the surface 41a of the wafer 41. And the groove | channel 17 which consists of the corner | angular parts 31-34 which expose the edge part of the pn junction 16 can be formed easily.
Therefore, it is possible to easily manufacture the highly reliable semiconductor device 11 that achieves both improved breakdown voltage and reliability and low loss.

なお、本実施形態では、ウェットエッチングによりウェーハ４１の表面４１ａの角部３１〜３４に対応する位置それぞれに凹部４３を形成し、次いで、この表面４１ａの溝１７に対応する位置をウェットエッチングするという２段階のウエットエッチングにより、ウェーハ４１の表面４１ａに、直線部２１〜２４と、深さが直線部２１〜２４の深さより深い角部３１〜３４とにより構成される溝１７を形成することとしたが、レーザの出力を変化させてウェーハ４１の表面４１ａにおけるエッチング深さを個々に変化させることにより、直線部２１〜２４と角部３１〜３４とからなる溝１７を形成することとしてもよい。
特に、グリーンレーザを用いれば、角部３１〜３４を精度良く形成できるので好ましい。
レーザを用いた場合、１回の操作で所望の形状の溝１７を形成することができるので、工程の短縮を図ることができる。 In the present embodiment, the recesses 43 are formed in the positions corresponding to the corners 31 to 34 of the surface 41a of the wafer 41 by wet etching, and then the positions corresponding to the grooves 17 on the surface 41a are wet etched. Forming a groove 17 constituted by straight portions 21 to 24 and corner portions 31 to 34 having a depth greater than the depth of the straight portions 21 to 24 on the surface 41a of the wafer 41 by two-stage wet etching; However, the groove 17 composed of the straight portions 21 to 24 and the corner portions 31 to 34 may be formed by changing the laser output to change the etching depth on the surface 41a of the wafer 41 individually. .
In particular, it is preferable to use a green laser because the corner portions 31 to 34 can be formed with high accuracy.
When a laser is used, the groove 17 having a desired shape can be formed by a single operation, so that the process can be shortened.

［第２の実施形態］
図４は、本発明の第２の実施形態の高信頼性半導体装置を示す平面図、図５は図４のＣ−Ｃ線に沿う断面図である。
本実施形態の高信頼性半導体装置５１が第１の実施形態の高信頼性半導体装置１１と異なる点は、第１の実施形態の高信頼性半導体装置１１では、溝１７の角部３１〜３４の幅と直線部２１〜２４の幅とが一致するように、角部３１〜３４の外側の内壁の曲率半径を内側の内壁の曲率半径より大きくしたのに対し、本実施形態の高信頼性半導体装置５１では、溝５２の角部５３〜５６の幅が直線部２１〜２４の幅より大きくなるように、角部５３〜５６の外側の内壁の曲率半径Ｒ１を内側の内壁の曲率半径Ｒ２より小さくした点である。 [Second Embodiment]
FIG. 4 is a plan view showing a highly reliable semiconductor device according to the second embodiment of the present invention, and FIG. 5 is a sectional view taken along the line CC of FIG.
The highly reliable semiconductor device 51 of the present embodiment is different from the highly reliable semiconductor device 11 of the first embodiment in that in the highly reliable semiconductor device 11 of the first embodiment, the corner portions 31 to 34 of the groove 17. The radius of curvature of the inner wall on the outer side of the corners 31 to 34 is made larger than the radius of curvature of the inner wall on the inner side so that the width of the straight line portions 21 to 24 coincides with the width of the straight portion 21 to 24. in the semiconductor device 51, so that the width of the corner portion 53 to 56 of the groove 52 is greater than the width of the linear portion 21 to 24, the radius of curvature R 1 of the outer inner wall of the corners 53-56 of the inner interior wall curvature radius in that the smaller than R 2.

この高信頼性半導体装置５１では、角部５３〜５６における外側の内壁５３ａ〜５６ａの曲率半径Ｒ１を、内側の内壁５３ｂ〜５６ｂの曲率半径Ｒ２より小さくしたことにより、角部５３〜５６の外側の内壁５３ａ〜５６ａが外側に広がることとなり、角部５３〜５６の面積が外側に向かって拡大されることとなる。
この角部５３〜５６は、エッチングにより形成されるが、エッチングにより溝５２を形成した場合に、面積が広い角部５３〜５６の方が直線部２１〜２４よりエッチング量が多くなり、したがって、角部５３〜５６の深さは、直線部２１〜２４の深さより深くなる。 In the highly reliable semiconductor device 51, the radius of curvature R 1 of the outer inner wall 53a~56a at the corner 53 to 56 is made smaller than the radius of curvature R 2 of the inner interior wall 53B～56b, corners 53 - 56 The inner walls 53a to 56a on the outer side of the outer side are spread outward, and the areas of the corners 53 to 56 are enlarged toward the outer side.
The corner portions 53 to 56 are formed by etching. However, when the groove 52 is formed by etching, the corner portions 53 to 56 having a larger area have a larger etching amount than the straight portions 21 to 24. The depths of the corner portions 53 to 56 are deeper than the depths of the straight portions 21 to 24.

この高信頼性半導体装置５１では、角部５３〜５６における外側の内壁５３ａ〜５６ａの曲率半径Ｒ１を、内側の内壁５３ｂ〜５６ｂの曲率半径Ｒ２より小さくしたことにより、角部５３〜５６の深さが直線部２１〜２４の深さより深くなり、したがって、溝５２の角部５３〜５６における耐圧を直線部２１〜２４における耐圧より高くすることが可能になる。これにより、電界を、溝５２の角部５３〜５６に集中させることなく、角部５３〜５６と直線部２１〜２４とに分散させることが可能になる。
また、ｎ型シリコン基板１２におけるｐｎ接合１６の占有面積が変わらずに、溝５２の角部５３〜５６の深さが深くなるので、高信頼性半導体装置５１としての損失も増加しない。
これにより、耐圧及び信頼性の向上と低損失を両立させることが可能になる。 In the highly reliable semiconductor device 51, the radius of curvature R 1 of the outer inner wall 53a~56a at the corner 53 to 56 is made smaller than the radius of curvature R 2 of the inner interior wall 53B～56b, corners 53 - 56 Thus, the withstand voltage at the corners 53 to 56 of the groove 52 can be made higher than the withstand voltage at the straight portions 21 to 24. Accordingly, the electric field can be distributed to the corner portions 53 to 56 and the straight portions 21 to 24 without being concentrated on the corner portions 53 to 56 of the groove 52.
In addition, since the area occupied by the pn junction 16 in the n-type silicon substrate 12 does not change and the depths of the corners 53 to 56 of the groove 52 are increased, the loss as the highly reliable semiconductor device 51 does not increase.
This makes it possible to achieve both improvement in breakdown voltage and reliability and low loss.

次に、この高信頼性半導体装置５１の製造方法について、図６に基づき説明する。
まず、図６（ａ）に示すように、ｎ型シリコン基板１２の表面の所定位置にベース層１３が形成されたウェーハ４１を用意する。
次いで、ウェーハ４１の表面全面にレジスト６１を塗布し、露光及び現像を行い、レジスト６１のうち溝５２に対応する位置に開口６１ａ、６１ｂを形成する。 Next, a method for manufacturing the highly reliable semiconductor device 51 will be described with reference to FIG.
First, as shown in FIG. 6A, a wafer 41 having a base layer 13 formed at a predetermined position on the surface of the n-type silicon substrate 12 is prepared.
Next, a resist 61 is applied to the entire surface of the wafer 41, exposed and developed, and openings 61a and 61b are formed at positions corresponding to the grooves 52 in the resist 61.

ここでは、開口６１ａが溝５２の角部５３〜５６に対応し、開口６１ｂが溝５２の直線部２１〜２４に対応している。
したがって、開口６１ａの幅ｗ１は溝５２の角部５３〜５６の幅に対応しており、開口６１ｂの幅ｗ２は直線部２１〜２４の幅に対応していることとなる。 Here, the opening 61 a corresponds to the corner portions 53 to 56 of the groove 52, and the opening 61 b corresponds to the straight portions 21 to 24 of the groove 52.
Therefore, the width w 1 of the opening 61a corresponds to the width of the corner portion 53 to 56 of the groove 52, the width w 2 of the opening 61b can be assumed to correspond to the width of the linear portion 21 to 24.

次いで、図６（ｂ）に示すように、ウェーハ４１の表面４１ａを、開口６１ａ、６１ｂが形成されたレジスト６１をマスクとしてウェットエッチングする。
ここでは、開口６１ａの幅ｗ１が溝５２の角部５３〜５６の幅に対応し、開口６１ｂの幅ｗ２が直線部２１〜２４の幅に対応しているので、得られた溝５２は、角部５３〜５６に対応する部分の幅ｗ１が直線部２１〜２４に対応する部分の幅ｗ２より大きくなるように、すなわち、角部５３〜５６に対応する部分の外側の内壁の曲率半径Ｒ１が、内側の内壁の曲率半径Ｒ２より小さくなるように、形成される。 Next, as shown in FIG. 6B, the surface 41a of the wafer 41 is wet-etched using the resist 61 in which the openings 61a and 61b are formed as a mask.
Here, the width w 1 of the opening 61 a corresponds to the width of the corners 53 to 56 of the groove 52, and the width w 2 of the opening 61 b corresponds to the width of the straight portions 21 to 24. Is such that the width w 1 of the portion corresponding to the corner portions 53 to 56 is larger than the width w 2 of the portion corresponding to the straight portions 21 to 24, that is, the inner wall outside the portion corresponding to the corner portions 53 to 56. the radius of curvature R 1 of, so that less than the radius of curvature R 2 of the inner of the inner wall, are formed.

これにより、ウェーハ４１の表面４１ａには、所望の深さの直線部２１〜２４と、外側の内壁５３ａ〜５６ａの曲率半径Ｒ１が内側の内壁５３ｂ〜５６ｂの曲率半径Ｒ２より小さく、深さが直線部２１〜２４より深くかつｐｎ接合１６の端部を露出する角部５３〜５６が形成されることとなる。
その後、マスク６１を除去する。 Thus, on the surface 41a of the wafer 41, a straight portion 21 to 24 of the desired depth, the radius of curvature R 1 of the outer inner wall 53a~56a is smaller than the radius of curvature R 2 of the inner interior wall 53B～56b, deep Corner portions 53 to 56 that are deeper than the straight portions 21 to 24 and that expose the end portions of the pn junction 16 are formed.
Thereafter, the mask 61 is removed.

次いで、図６（ｃ）に示すように、溝５２の内面にパッシベーション膜となるガラス膜１８を形成する。
次いで、ウェーハ４１の表面４１ａの所定位置に、蒸着法や無電界めっき法によりＡｌ、Ｃｕ、Ｐｄ、Ｎｉ等の電極用金属を堆積させ、電極１５を形成する。
以上により、本実施形態のメサプレーナー構造の高信頼性半導体装置５１を作製することができる。 Next, as shown in FIG. 6C, a glass film 18 serving as a passivation film is formed on the inner surface of the groove 52.
Next, an electrode metal such as Al, Cu, Pd, or Ni is deposited at a predetermined position on the surface 41 a of the wafer 41 by vapor deposition or electroless plating to form the electrode 15.
As described above, the highly reliable semiconductor device 51 having the mesa planar structure of this embodiment can be manufactured.

本実施形態のメサプレーナー構造の高信頼性半導体装置５１においても、第１の実施形態のメサプレーナー構造の高信頼性半導体装置１１と同様の効果を奏することができる。   The highly reliable semiconductor device 51 having the mesa planar structure according to the present embodiment can achieve the same effects as the highly reliable semiconductor device 11 having the mesa planar structure according to the first embodiment.

なお、本実施形態では、ウェーハ４１の表面４１ａの溝５２に対応する位置を、開口６１ａが形成されたレジスト６１をマスクとしてウェットエッチングすることとしたが、レーザの出力を変化させてウェーハ４１の表面４１ａにおけるエッチング深さを個々に変化させることにより、直線部２１〜２４と角部５３〜５６とからなる溝５２を形成することとしても、本実施形態のメサプレーナー構造の高信頼性半導体装置５１を作製することができる。   In this embodiment, the position corresponding to the groove 52 on the surface 41a of the wafer 41 is wet-etched using the resist 61 having the opening 61a as a mask, but the laser output is changed to change the position of the wafer 41. Even if the groove 52 including the straight portions 21 to 24 and the corner portions 53 to 56 is formed by individually changing the etching depth on the surface 41a, the highly reliable semiconductor device having the mesa planar structure of the present embodiment. 51 can be produced.

［第３の実施形態］
図７は、本発明の第３の実施形態の高信頼性半導体装置を示す部分断面図である。
本実施形態の高信頼性半導体装置７１が第１の実施形態の高信頼性半導体装置１１と異なる点は、溝の角部７２を、その深さが、ベース層１３とｎ型シリコン基板１２とのｐｎ接合１６の界面近傍に形成された空乏層７３の位置より深くなるように形成した点であり、その他の点については第１の実施形態の高信頼性半導体装置１１と全く同様である。 [Third Embodiment]
FIG. 7 is a partial sectional view showing a highly reliable semiconductor device according to the third embodiment of the present invention.
The highly reliable semiconductor device 71 of the present embodiment is different from the highly reliable semiconductor device 11 of the first embodiment in that the corner 72 of the groove has a depth different from that of the base layer 13 and the n-type silicon substrate 12. This is that it is formed deeper than the position of the depletion layer 73 formed near the interface of the pn junction 16, and the other points are the same as those of the highly reliable semiconductor device 11 of the first embodiment.

空乏層７３は、ｎ型シリコン基板１２及びベース層１３におけるキャリア濃度と、ｐｎ接合１６における不純物拡散濃度とから決定されるので、逆方法にバイアス電圧を印加した場合を考慮すると、溝の角部７２の深さは、空乏層７３より深いことが好ましいということになる。   Since the depletion layer 73 is determined from the carrier concentration in the n-type silicon substrate 12 and the base layer 13 and the impurity diffusion concentration in the pn junction 16, considering the case where a bias voltage is applied to the reverse method, the corner portion of the groove The depth of 72 is preferably deeper than the depletion layer 73.

本実施形態のメサプレーナー構造の高信頼性半導体装置７１においても、第１の実施形態のメサプレーナー構造の高信頼性半導体装置１１と同様の効果を奏することができる。
しかも、溝の角部７２を、その深さがベース層１３とｎ型シリコン基板１２とのｐｎ接合１６の界面近傍に形成された空乏層７３の位置より深くなるように形成したので、溝の角部７２の深さがｐｎ接合１６の界面近傍に形成された空乏層７３の位置より深くなり、したがって、溝７２の角部における耐圧を、溝７２の直線部における耐圧より高くすることができる。その結果、溝７２の角部に電界が集中する虞が無くなり、耐圧及び信頼性をさらに向上させることができ、電界による破壊を防止することができる。 The highly reliable semiconductor device 71 having the mesa planar structure according to the present embodiment can achieve the same effects as the highly reliable semiconductor device 11 having the mesa planar structure according to the first embodiment.
Moreover, since the corner 72 of the groove is formed so that its depth is deeper than the position of the depletion layer 73 formed in the vicinity of the interface of the pn junction 16 between the base layer 13 and the n-type silicon substrate 12, The depth of the corner 72 becomes deeper than the position of the depletion layer 73 formed in the vicinity of the interface of the pn junction 16, so that the breakdown voltage at the corner of the groove 72 can be made higher than the breakdown voltage at the straight portion of the groove 72. . As a result, there is no possibility that the electric field concentrates on the corners of the groove 72, the breakdown voltage and the reliability can be further improved, and the breakdown due to the electric field can be prevented.

以上、本発明ではメサプレーナー構造の高信頼性半導体装置について説明したが、本発明は、第１の導電型の半導体基板及び第２の導電型の半導体層により形成されたｐｎ接合の周縁部にｐｎ接合の端部を露出する溝を形成した構造であればよく、例えば、サイリスタ等に代表されるような、ｐ−ｎ−ｐ−ｎ等のように４層以上の半導体層を積層した構造の半導体装置に対しても適用可能であり、その技術的価値は大きなものである。   As described above, the high reliability semiconductor device having the mesa planar structure has been described in the present invention. Any structure may be used as long as a groove that exposes the end of the pn junction is formed. For example, a structure in which four or more semiconductor layers such as pnpn are stacked, such as a thyristor. The present invention can be applied to other semiconductor devices, and its technical value is great.

１１ 高信頼性半導体装置
１２ ｎ型シリコン基板（第１の導電型の半導体基板）
１２ａ 表面（一主面）
１３ ベース層（第２の導電型の半導体層）
１５ 電極
１６ ｐｎ接合
１７ 溝
１８ ガラス膜
２１〜２４ 直線部
３１〜３４ 角部
４１ ウェーハ
４１ａ 表面
４２ レジスト
４２ａ 開口
４３ 凹部
４４ マスク
４４ａ 開口
５１ 高信頼性半導体装置
５２ 溝
５３〜５６ 角部
５３ａ〜５６ａ 外側の内壁
５３ｂ〜５６ｂ 内側の内壁
６１ レジスト
６１ａ、６１ｂ 開口
７１ 高信頼性半導体装置
７２ 溝の角部
７３ 空乏層 11 Highly reliable semiconductor device 12 n-type silicon substrate (first conductivity type semiconductor substrate)
12a Surface (one main surface)
13 Base layer (second conductivity type semiconductor layer)
DESCRIPTION OF SYMBOLS 15 Electrode 16 pn junction 17 Groove 18 Glass film 21-24 Linear part 31-34 Corner | angular part 41 Wafer 41a Surface 42 Resist 42a Opening 43 Recessed part 44 Mask 44a Opening 51 Highly reliable semiconductor device 52 Groove 53-56 Corner part 53a-56a Outer inner wall 53b to 56b Inner inner wall 61 Resist 61a, 61b Opening 71 High reliability semiconductor device 72 Corner of groove 73 Depletion layer

Claims (2)

第１の導電型の半導体基板の一主面に第２の導電型の半導体層が形成され、前記第１の導電型の半導体基板及び前記第２の導電型の半導体層により形成されたｐｎ接合の周縁部に前記ｐｎ接合の端部を露出する溝を形成してなり、前記溝は、複数の直線部と複数の角部とからなる高信頼性半導体装置の製造方法において、
前記ｐｎ接合の周縁部の角部を選択除去する工程と、
前記角部を含む前記ｐｎ接合の周縁部を選択除去することにより、前記ｐｎ接合部の周縁部に前記溝を形成するとともに、前記溝の角部の深さを、前記溝の直線部の深さより深くする工程と、
を有することを特徴とする高信頼性半導体装置の製造方法。 A second conductivity type semiconductor layer is formed on one main surface of the first conductivity type semiconductor substrate, and a pn junction formed by the first conductivity type semiconductor substrate and the second conductivity type semiconductor layer. A groove exposing the end of the pn junction is formed in a peripheral portion of the semiconductor device, and the groove includes a plurality of linear portions and a plurality of corner portions.
Selectively removing corners of the peripheral edge of the pn junction;
By selectively removing the peripheral portion of the pn junction including the corner portion, the groove is formed in the peripheral portion of the pn junction portion, and the depth of the corner portion of the groove is set to the depth of the linear portion of the groove. A deeper process,
A method for manufacturing a highly reliable semiconductor device, comprising: 第１の導電型の半導体基板の一主面に第２の導電型の半導体層が形成され、前記第１の導電型の半導体基板及び前記第２の導電型の半導体層により形成されたｐｎ接合の周縁部に前記ｐｎ接合の端部を露出する溝を形成してなり、前記溝は、複数の直線部と複数の角部とからなる高信頼性半導体装置の製造方法において、
レーザの出力を変化させて前記ｐｎ接合の周縁部を選択除去することにより、前記溝の角部の深さを前記溝の直線部の深さより深くする工程
を有することを特徴とする高信頼性半導体装置の製造方法。 A second conductivity type semiconductor layer is formed on one main surface of the first conductivity type semiconductor substrate, and a pn junction formed by the first conductivity type semiconductor substrate and the second conductivity type semiconductor layer. A groove exposing the end of the pn junction is formed in a peripheral portion of the semiconductor device, and the groove includes a plurality of linear portions and a plurality of corner portions.
The method includes the step of making the depth of the corner of the groove deeper than the depth of the straight portion of the groove by selectively removing the peripheral portion of the pn junction by changing the laser output. A method for manufacturing a semiconductor device.
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