JP5568543B2 - 平面表示装置用アレイ基板の製造方法 - Google Patents
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- 239000007788 liquid Substances 0.000 claims description 3
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- 239000010409 thin film Substances 0.000 description 2
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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Description
第1方向に沿って延出したゲート配線と、第1方向に直交する第2方向に沿って延出したソース配線と、半導体層、前記ゲート配線と電気的に接続されたゲート電極、前記ソース配線と電気的に接続され前記半導体層にコンタクトしたソース電極及び前記半導体層にコンタクトしたドレイン電極を備えたスイッチング素子と、前記ソース配線及び前記スイッチング素子を覆うとともに前記ドレイン電極を露出するコンタクトホールが形成された絶縁膜と、前記絶縁膜上に形成された画素電極と、を備えた平面表示装置用アレイ基板であって、前記ソース配線と前記ドレイン電極とがショートした画素においては、前記絶縁膜の前記コンタクトホールに充填され前記ドレイン電極と前記画素電極との間に介在する絶縁性の充填部材を備えたことを特徴とする平面表示装置用アレイ基板が提供される。
絶縁基板上に、半導体層、ゲート配線と電気的に接続されたゲート電極、ソース配線と電気的に接続され前記半導体層にコンタクトしたソース電極及び前記半導体層にコンタクトしたドレイン電極を備えたスイッチング素子を形成し、前記ソース配線及び前記スイッチング素子を覆うとともに前記ドレイン電極を露出するコンタクトホールを有する絶縁膜を形成し、前記ソース配線と前記ドレイン電極とがショートした画素においては、前記絶縁膜の前記コンタクトホールに絶縁性の充填部材を充填して前記ドレイン電極を覆い、前記絶縁膜上及び前記充填部材上に画素電極を形成する、ことを特徴とする平面表示装置用アレイ基板の製造方法が提供される。
絶縁基板上に、半導体層、ゲート配線と電気的に接続されたゲート電極、ソース配線と電気的に接続され前記半導体層にコンタクトしたソース電極及び前記半導体層にコンタクトしたドレイン電極を備えたスイッチング素子を形成し、前記スイッチング素子を形成済みの処理基板について、前記ソース配線と前記ドレイン電極とのショートの有無を検査し、前記ショートを検出した場合には、前記処理基板上における前記ショートの位置情報を出力し、前記ソース配線及び前記スイッチング素子を覆うとともに前記ドレイン電極を露出するコンタクトホールを有する絶縁膜を形成し、前記ショートを検出しなかった画素においては、前記絶縁膜上及び前記コンタクトホールに延在し前記ドレイン電極にコンタクトした画素電極を形成し、前記ショートを検出した画素においては、前記位置情報に基づいて前記コンタクトホールに絶縁性の充填部材を充填して前記ドレイン電極を覆い、前記絶縁膜上及び前記充填部材上に画素電極を形成する、ことを特徴とする平面表示装置用アレイ基板の製造方法が提供される。
PE…画素電極 PSL…スリット
CE…共通電極
G…ゲート配線 S…ソース配線 SW…スイッチング素子
FL…充填部材
Claims (1)
- 絶縁基板上に、半導体層、ゲート配線と電気的に接続されたゲート電極、ソース配線と電気的に接続され前記半導体層にコンタクトしたソース電極及び前記半導体層にコンタクトしたドレイン電極を備えたスイッチング素子を形成し、
前記スイッチング素子を形成済みの処理基板について、前記ソース配線と前記ドレイン電極とのショートの有無を検査し、
前記ショートを検出した場合には、前記処理基板上における前記ショートの位置情報を出力し、
前記ソース配線及び前記スイッチング素子を覆うとともに前記ドレイン電極を露出するコンタクトホールを有する絶縁膜を形成し、
前記ショートを検出しなかった画素においては、前記絶縁膜上及び前記コンタクトホールに延在し前記ドレイン電極にコンタクトした画素電極を形成し、
前記ショートを検出した画素においては、前記位置情報に基づいて前記コンタクトホールに絶縁性の充填部材を充填して前記ドレイン電極を覆い、前記絶縁膜上及び前記充填部材上に画素電極を形成する、製造方法であって、
前記充填部材の充填は、前記位置情報に基づいて位置合わせを行い、ディスペンサにより前記コンタクトホールに向けて液状の樹脂材料を塗布した後に、前記樹脂材料を硬化させることにより行うことを特徴とする平面表示装置用アレイ基板の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2011265234A JP5568543B2 (ja) | 2011-12-02 | 2011-12-02 | 平面表示装置用アレイ基板の製造方法 |
US13/680,411 US9082889B2 (en) | 2011-12-02 | 2012-11-19 | Array substrate for flat display device and manufacturing the same |
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JP2011265234A JP5568543B2 (ja) | 2011-12-02 | 2011-12-02 | 平面表示装置用アレイ基板の製造方法 |
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JP2013117644A JP2013117644A (ja) | 2013-06-13 |
JP5568543B2 true JP5568543B2 (ja) | 2014-08-06 |
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Families Citing this family (5)
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JP5997958B2 (ja) * | 2012-07-23 | 2016-09-28 | 株式会社ジャパンディスプレイ | 表示装置及びアレイ基板 |
US10663804B2 (en) * | 2015-09-25 | 2020-05-26 | Sharp Kabushiki Kaisha | Liquid crystal display device comprising a second electrode having an elliptical opening portion with a major axis parallel or perpendicular to an alignment azimuth of liquid crystal molecules |
KR102547501B1 (ko) * | 2016-04-28 | 2023-06-26 | 삼성디스플레이 주식회사 | 표시 장치 및 표시 장치 제조 방법 |
US11294216B2 (en) * | 2017-06-14 | 2022-04-05 | Sharp Kabushiki Kaisha | Display substrate and display device |
JP7175840B2 (ja) * | 2019-04-26 | 2022-11-21 | 株式会社ジャパンディスプレイ | 表示装置 |
Family Cites Families (8)
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JPS61100971A (ja) * | 1984-10-23 | 1986-05-19 | Fujitsu Ltd | 薄膜トランジスタの製造方法 |
JPS6486113A (en) * | 1987-09-29 | 1989-03-30 | Casio Computer Co Ltd | Manufacture of thin film transistor |
JPH07111522B2 (ja) * | 1988-06-16 | 1995-11-29 | カシオ計算機株式会社 | Tftパネルの製造方法 |
JPH0711642B2 (ja) * | 1988-10-27 | 1995-02-08 | シャープ株式会社 | 表示電極基板の製造方法 |
JP5148819B2 (ja) * | 2005-08-16 | 2013-02-20 | エルジー ディスプレイ カンパニー リミテッド | 液晶表示素子 |
JP4439546B2 (ja) | 2007-08-31 | 2010-03-24 | 東芝モバイルディスプレイ株式会社 | 表示装置用アレイ基板及びその製造方法 |
JP2010066546A (ja) * | 2008-09-11 | 2010-03-25 | Sharp Corp | 配線基板製造装置、配線基板における絶縁膜の欠損修正判定方法、絶縁膜の欠損の修正を判定するプログラム、及び、当該プログラムを記録した記録媒体 |
JP5534715B2 (ja) * | 2009-05-27 | 2014-07-02 | 株式会社ジャパンディスプレイ | 電子回路パターンの欠陥修正方法およびその装置 |
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US9082889B2 (en) | 2015-07-14 |
US20130140571A1 (en) | 2013-06-06 |
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