JP5557204B2 - 集積回路パッケージシステムおよびその製造システム - Google Patents
集積回路パッケージシステムおよびその製造システム Download PDFInfo
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- JP5557204B2 JP5557204B2 JP2007251743A JP2007251743A JP5557204B2 JP 5557204 B2 JP5557204 B2 JP 5557204B2 JP 2007251743 A JP2007251743 A JP 2007251743A JP 2007251743 A JP2007251743 A JP 2007251743A JP 5557204 B2 JP5557204 B2 JP 5557204B2
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- package
- integrated circuit
- lead finger
- circuit package
- interconnect
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Geometry (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
。これらの局面は、添付の図面を参照して捉えると、以下の詳細な説明を読むことにより、当業者には明らかになるであろう。
れによりパッケージングの製造歩留まりを向上させる。
ィング122によって第1の装置102に電気的に接続されて示され、第2のリードフィンガシステム120はバンプ接合124によって第2の装置104に電気的に接続されて示される。第1のリードフィンガシステム118および第2のリードフィンガシステム120は、ワイヤボンディング122およびバンプ接合124に導電性であって接合可能な表面を与える、任意の数の材料から作られ得る。たとえば、第1のリードフィンガシステム118および第2のリードフィンガシステム120は、銅合金またはニッケル/パラジウムの組合わせから作られてもよい。
6は、ディープエッチングによって形成することができる「L字型の」構成を有することで特徴付けられ得る。例として、ディープエッチングプロセスは電気的な相互接続システム116から材料を取り除き、それによって、第1のリードフィンガシステム118および第2のリードフィンガシステム120を形成する。
0ミクロンであり、バンプ接合/リード距離「d」が約10ミクロンであるので、集積回路パッケージシステム100および200の幅は、装置の1つの側当たり約190ミクロン減じられて約90にまで減らされることができる。したがって、本発明がバンプ接合/リード距離「d」(すなわち、より小さなギャップ技術)を使用するので、本発明の設置面積は、ワイヤボンディング技術を使用するのみである従来のパッケージシステムの設置面積よりも小さくなる。
る。この成形プロセスは、封止材料126が第1の装置背面112および第2の装置背面114を覆わないように設計することができる。支持構造600はこれらのプロセスステップ中に集積回路パッケージシステム200を安定させる。一般に、この段階は第2のダイの取付けおよび成型の段階と呼ぶことができる。
ここで図10を参照すると、本発明の実施例による集積回路パッケージシステム100および200のための集積回路パッケージ製造システム1000の流れ図が示される。集積回路パッケージ製造システム1000は、ブロック1002において、第1のリードフィンガシステムおよび第2のリードフィンガシステムを含む電気的な相互接続システムを与えることと、ブロック1004において第1の装置をワイヤボンディングで第1のリードフィンガシステムに接続することと、ブロック1006において第1の装置の上に第2の装置を積み重ねることと、ブロック1008において、第2の装置をバンプ接合で第2のリードフィンガシステムに接続することとを含む。
回路を保護することである。
Claims (8)
- 集積回路パッケージシステム(500)の製造システムであって、
それぞれが電気的な相互接続システム(116)を有する第1のパッケージ(402)および第2のパッケージ(404)の各々を形成する手段と、
前記第1のパッケージ(402)を、基板(406)の上面に装着する前に検査する手段と、
基板(406)の上面に、前記検査する手段による検査を受けた前記第1のパッケージ(402)を、接着剤(502)を介在させて装着する手段と、
第1の相互接続(504)によって前記第1のパッケージ(402)の前記電気的な相互接続システム(116)を前記基板(406)に電気的に接続する手段と、
前記第2のパッケージ(404)を、前記第1のパッケージ(402)の上に積み重ねる前に検査する手段と、
前記第1のパッケージ(402)の上に、パッケージ間構造(506)を介在させて、前記検査する手段による検査を受けた第2のパッケージ(404)を積み重ねる手段と、 第2の相互接続(508)によって前記第2のパッケージ(404)の前記電気的な相互接続システム(116)を前記基板(406)に電気的に接続する手段と、
積み重ねた前記第1のパッケージ(402)および前記第2のパッケージ(404)と、前記第1の相互接続(504)および前記第2の相互接続(508)とを、封止材料(510)によって覆う手段とを備え、
前記第1のパッケージ(402)および前記第2のパッケージ(404)の各々を形成する前記手段は、
第1のリードフィンガシステム(118)および第2のリードフィンガシステム(120)を含む前記電気的な相互接続システム(116)を与える手段と、
前記第1のリードフィンガシステム(118)に第1の装置(102)をワイヤボンディング(122)で接続する手段と、
前記第1の装置(102)の上に第2の装置(104)を積み重ねる手段と、
前記第2のリードフィンガシステム(120)に第2の装置(104)をバンプ接合(124)で接続する手段とを含み、
前記電気的な相互接続システム(116)を与える手段は、パッケージの積重ねのために前記第1のリードフィンガシステム(118)および第2のリードフィンガシステム(120)のそれぞれの外側端部に、前記第1のリードフィンガシステム(118)および第2のリードフィンガシステム(120)の上面よりも高くなるように設けられた、スタッキング支持部材(202)を与える手段をさらに含むとともに、前記第2の装置(104)と前記第2のリードフィンガシステム(120)とは、前記第1の装置と前記第2の装置との積重ね方向から見たときに、少なくとも一部が、互いに重なるように配置されてバンプ接合される、集積回路パッケージシステムの製造システム。 - 前記第2の装置(104)を積み重ねる手段は、前記第1の装置の能動側(108)および前記第2の装置の能動側(110)の部分を露出するために前記第2の装置(104)をずらせる手段を含む、請求項1に記載の集積回路パッケージシステムの製造システム。
- 第1の装置背面(112)および第2の装置背面(114)を外部環境に露出するよう集積回路パッケージシステム(100または200)を構成する手段をさらに含む、請求項1に記載の集積回路パッケージシステムの製造システム。
- 前記第1の装置(102)と前記第2の装置(104)との間に装置間構造(106)を与える手段をさらに含む、請求項1に記載の集積回路パッケージシステムの製造システム。
- 基板(406)と、
検査を受けた後に、前記基板(406)の上面に接着剤(502)を介在させて装着された、第1のパッケージ(402)と、
検査を受けた後に、前記第1のパッケージ(402)の上にパッケージ間構造(506)を介在させて積み重ねられた、第2のパッケージ(404)とを備え、
前記第1のパッケージ(402)および前記第2のパッケージ(404)の各々は、第1のリードフィンガシステム(118)および第2のリードフィンガシステム(120)を含む電気的な相互接続システム(116)を有し、
前記第1のパッケージ(402)の前記電気的な相互接続システム(116)は第1の相互接続(504)によって前記基板(406)に電気的に接続され、前記第2のパッケージ(404)の前記電気的な相互接続システム(116)は第2の相互接続(508)によって前記基板(406)に電気的に接続され、
前記第1のパッケージ(402)、前記第2のパッケージ(404)、前記第1の相互接続(504)、および前記第2の相互接続(508)は封止材料(510)で覆われており、
前記第1のパッケージ(402)および前記第2のパッケージ(404)の各々は、さらに
前記第1のリードフィンガシステム(118)および第1の装置(102)の間のワイヤボンディング(122)と、
前記第1の装置(102)の上の第2の装置(104)と、
前記第2の装置(104)および前記第2のリードフィンガシステム(120)の間のバンプ接合(124)とを含み、
前記電気的な相互接続システム(116)は、パッケージの積重ねのために前記第1のリードフィンガシステム(118)および前記第2のリードフィンガシステム(120)のそれぞれの外側端部に、前記第1のリードフィンガシステム(118)および第2のリードフィンガシステム(120)の上面よりも高くなるように設けられた、スタッキング支持部材(202)をさらに含むとともに、前記第2の装置(104)と前記第2のリードフィンガシステム(120)とは、前記第1の装置と前記第2の装置との積重ね方向から見たときに、少なくとも一部が、互いに重なるように配置されてバンプ接合されている、集積回路パッケージシステム。 - 前記第2の装置(104)は、前記第1の装置の能動側(108)および前記第2の装置の能動側(110)の部分を露出するために前記第1の装置(102)からずらされる、請求項5に記載の集積回路パッケージシステム。
- 外部環境に露出された第1の装置背面(112)および第2の装置背面(114)をさらに含む、請求項5に記載の集積回路パッケージシステム。
- 前記第1の装置(102)および前記第2の装置(104)の間に装置間構造(106)をさらに含む、請求項5に記載の集積回路パッケージシステム。
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Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8432026B2 (en) * | 2006-08-04 | 2013-04-30 | Stats Chippac Ltd. | Stackable multi-chip package system |
US7622333B2 (en) * | 2006-08-04 | 2009-11-24 | Stats Chippac Ltd. | Integrated circuit package system for package stacking and manufacturing method thereof |
US7759783B2 (en) * | 2006-12-07 | 2010-07-20 | Stats Chippac Ltd. | Integrated circuit package system employing thin profile techniques |
US8174127B2 (en) * | 2007-06-21 | 2012-05-08 | Stats Chippac Ltd. | Integrated circuit package system employing device stacking |
US7830020B2 (en) * | 2007-06-21 | 2010-11-09 | Stats Chippac Ltd. | Integrated circuit package system employing device stacking |
JP5646830B2 (ja) | 2009-09-02 | 2014-12-24 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体装置の製造方法、及びリードフレーム |
JP6254807B2 (ja) * | 2013-09-27 | 2017-12-27 | ローム株式会社 | 半導体装置および電子機器 |
TWI608564B (zh) * | 2013-12-10 | 2017-12-11 | 艾馬克科技公司 | 半導體裝置 |
TWI550823B (zh) * | 2014-04-10 | 2016-09-21 | 南茂科技股份有限公司 | 晶片封裝結構 |
US20200135632A1 (en) * | 2018-10-24 | 2020-04-30 | Texas Instruments Incorporated | Die isolation on a substrate |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970000214B1 (ko) * | 1993-11-18 | 1997-01-06 | 삼성전자 주식회사 | 반도체 장치 및 그 제조방법 |
JP3129928B2 (ja) * | 1995-03-30 | 2001-01-31 | シャープ株式会社 | 樹脂封止型半導体装置 |
US6492719B2 (en) * | 1999-07-30 | 2002-12-10 | Hitachi, Ltd. | Semiconductor device |
JP3560488B2 (ja) * | 1999-01-29 | 2004-09-02 | ユナイテッド マイクロエレクトロニクス コープ | マルチチップ用チップ・スケール・パッケージ |
KR100421774B1 (ko) * | 1999-12-16 | 2004-03-10 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
JP2001177005A (ja) | 1999-12-17 | 2001-06-29 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2001274316A (ja) | 2000-03-23 | 2001-10-05 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR100559664B1 (ko) * | 2000-03-25 | 2006-03-10 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
US6476474B1 (en) * | 2000-10-10 | 2002-11-05 | Siliconware Precision Industries Co., Ltd. | Dual-die package structure and method for fabricating the same |
US20020127771A1 (en) * | 2001-03-12 | 2002-09-12 | Salman Akram | Multiple die package |
JP2002359345A (ja) | 2001-03-30 | 2002-12-13 | Toshiba Corp | 半導体装置及びその製造方法 |
TW544901B (en) * | 2001-06-13 | 2003-08-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JP3670625B2 (ja) | 2001-06-13 | 2005-07-13 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
US6847105B2 (en) * | 2001-09-21 | 2005-01-25 | Micron Technology, Inc. | Bumping technology in stacked die configurations |
TW523887B (en) * | 2001-11-15 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Semiconductor packaged device and its manufacturing method |
KR100447869B1 (ko) * | 2001-12-27 | 2004-09-08 | 삼성전자주식회사 | 다핀 적층 반도체 칩 패키지 및 이에 사용되는 리드 프레임 |
US20040021230A1 (en) * | 2002-08-05 | 2004-02-05 | Macronix International Co., Ltd. | Ultra thin stacking packaging device |
JP3736516B2 (ja) | 2002-11-01 | 2006-01-18 | 松下電器産業株式会社 | リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法 |
TW556961U (en) * | 2002-12-31 | 2003-10-01 | Advanced Semiconductor Eng | Multi-chip stack flip-chip package |
TWI226689B (en) * | 2003-02-25 | 2005-01-11 | Via Tech Inc | Chip package and process for forming the same |
US6984881B2 (en) * | 2003-06-16 | 2006-01-10 | Sandisk Corporation | Stackable integrated circuit package and method therefor |
JP4580730B2 (ja) * | 2003-11-28 | 2010-11-17 | ルネサスエレクトロニクス株式会社 | オフセット接合型マルチチップ半導体装置 |
TWM250321U (en) * | 2004-01-14 | 2004-11-11 | Optimum Care Int Tech Inc | Lead frame unit structure of chip with hidden position |
JP2006310649A (ja) | 2005-04-28 | 2006-11-09 | Sharp Corp | 半導体装置パッケージおよびその製造方法、ならびに半導体装置パッケージ用一括回路基板 |
US7582960B2 (en) * | 2005-05-05 | 2009-09-01 | Stats Chippac Ltd. | Multiple chip package module including die stacked over encapsulated package |
US7622333B2 (en) * | 2006-08-04 | 2009-11-24 | Stats Chippac Ltd. | Integrated circuit package system for package stacking and manufacturing method thereof |
US7439620B2 (en) * | 2006-08-04 | 2008-10-21 | Stats Chippac Ltd. | Integrated circuit package-in-package system |
US8432026B2 (en) * | 2006-08-04 | 2013-04-30 | Stats Chippac Ltd. | Stackable multi-chip package system |
US7645638B2 (en) * | 2006-08-04 | 2010-01-12 | Stats Chippac Ltd. | Stackable multi-chip package system with support structure |
US7683467B2 (en) * | 2006-12-07 | 2010-03-23 | Stats Chippac Ltd. | Integrated circuit package system employing structural support |
US8304874B2 (en) * | 2006-12-09 | 2012-11-06 | Stats Chippac Ltd. | Stackable integrated circuit package system |
US7635913B2 (en) * | 2006-12-09 | 2009-12-22 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US7772683B2 (en) * | 2006-12-09 | 2010-08-10 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
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