JP5466970B2 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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JP5466970B2
JP5466970B2 JP2010045355A JP2010045355A JP5466970B2 JP 5466970 B2 JP5466970 B2 JP 5466970B2 JP 2010045355 A JP2010045355 A JP 2010045355A JP 2010045355 A JP2010045355 A JP 2010045355A JP 5466970 B2 JP5466970 B2 JP 5466970B2
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靖弘 藤盛
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MegaChips Corp
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Description

本発明は、Caplessタイプ（外付け容量不要型）のレギュレータを内蔵する半導体集積回路に係り、特にそのレギュレータの出力電圧を測定できるようにした半導体集積回路に関する。   The present invention relates to a semiconductor integrated circuit incorporating a regulator of a Capless type (external capacitor unnecessary type), and more particularly to a semiconductor integrated circuit capable of measuring an output voltage of the regulator.

一般のＡＳＩＣに内蔵されるCaplessタイプのレギュレータの出力電圧は、当該ＡＳＩＣ内のアナログ系マクロのように電源ノイズに対してセンシティブな内部回路に供給される。ところが、Caplessタイプのレギュレータには電圧出力ピンが設けられていないので、その出力電圧を確認することができない。   The output voltage of a Capless type regulator built in a general ASIC is supplied to an internal circuit that is sensitive to power supply noise like an analog macro in the ASIC. However, since the voltage output pin is not provided in the Capless type regulator, the output voltage cannot be confirmed.

一方、特許文献１には、常時は内部回路の全部に主電源により電圧供給を行い、その主電源の電圧が降下した場合に、主電源によって常時充電されていた容量からなる補助電源の電圧を内部回路の一部に供給することが記載されている。   On the other hand, in Patent Document 1, the voltage of the auxiliary power source composed of the capacity that is always charged by the main power source is supplied when the voltage of the main power source drops when the voltage of the main power source is constantly supplied to all the internal circuits. It is described that it is supplied to a part of the internal circuit.

特開２００２−３５４７０７号公報JP 2002-354707 A

そこで、この特許文献１の技術をCaplessタイプのレギュレータに適用した場合、主電源の電圧を補助電源を介して確認することはできる。しかし、Caplessタイプのレギュレータから電源供給を受けるノイズに弱い内部回路と他の内部回路を分けることができないので、ノイズに弱い内部回路に悪影響が及ぶ恐れがある。   Therefore, when the technique of Patent Document 1 is applied to a Capless type regulator, the voltage of the main power supply can be confirmed via the auxiliary power supply. However, since the internal circuit that is sensitive to noise that is supplied with power from the Capless type regulator cannot be separated from other internal circuits, there is a possibility that the internal circuit that is sensitive to noise may be adversely affected.

本発明の目的は、Caplessタイプのレギュレータの出力電圧を確認することができ、しかもノイズに弱い内部回路に悪影響を与えないようにした半導体集積回路を提供することである。   An object of the present invention is to provide a semiconductor integrated circuit in which the output voltage of a Capless type regulator can be confirmed, and an internal circuit that is sensitive to noise is not adversely affected.

上記目的を達成するために、請求項１にかかる発明は、第１および第２の内部回路を有する半導体集積回路であって、第１の外部電源の供給を受ける第１の電源ピンと、前記第１の外部電源から第１の動作電源を生成するレギュレータと、前記第１の動作電源を前記第１の内部回路に供給する第１の電源配線と、前記第１の動作電源の電圧と同一電圧を有する第２の動作電源の供給を受ける第２の電源ピンと、前記第２の動作電源を前記第２の内部回路に供給する第２の電源配線と、オン状態において前記第１の電源配線と前記第２の電源配線とを相互に接続するスイッチ回路と、前記第１の内部回路が前記第１の動作電源の供給を受けて動作する通常動作時に、前記スイッチ回路をオフ状態に制御する制御回路と、を備えることを特徴とする。
請求項２にかかる発明は、請求項１に記載の半導体集積回路において、前記制御回路が、前記第１の動作電源の電圧をモニタする試験状態を示す信号が入力されたときに、前記スイッチ回路をオン状態に制御することを特徴とする。
請求項３にかかる発明は、請求項１又は２に記載の半導体集積回路において、前記第１の動作電源の異常を検知したときに検知信号を生成して前記制御回路に入力する検知回路をさらに備え、前記制御回路が、前記検知信号が入力されたときに、前記スイッチ回路をオン状態に制御することを特徴とする。
請求項４にかかる発明は、請求項１ないし３のいずれかに記載の半導体集積回路において、前記第２の電源ピンに安定化容量が接続されていることを特徴とする。 In order to achieve the above object, a first aspect of the present invention is a semiconductor integrated circuit having first and second internal circuits, the first power supply pin receiving a first external power supply, and the first power supply pin. A regulator that generates a first operating power supply from one external power supply, a first power supply wiring that supplies the first operating power supply to the first internal circuit, and the same voltage as the voltage of the first operating power supply A second power supply pin that receives supply of a second operating power supply, a second power supply wiring that supplies the second operating power supply to the second internal circuit, and the first power supply wiring in an on state. A switch circuit that interconnects the second power supply wiring and a control that controls the switch circuit to an off state during a normal operation in which the first internal circuit operates by receiving the supply of the first operating power. And a circuit. .
According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, when the control circuit receives a signal indicating a test state for monitoring the voltage of the first operating power supply, the switch circuit Is controlled to be in an on state.
The invention according to claim 3 is the semiconductor integrated circuit according to claim 1 or 2, further comprising a detection circuit that generates a detection signal and inputs the detection signal to the control circuit when an abnormality of the first operating power supply is detected. And the control circuit controls the switch circuit to an ON state when the detection signal is input.
According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to any one of the first to third aspects, a stabilization capacitor is connected to the second power supply pin.

本発明によれば、レギュレータで生成された第１の動作電源が供給される第１の電源配線と第２の電源ピンに接続される第２の電源配線とを相互に接続するスイッチ回路を設けたので、そのスイッチ回路をオンすることにより、レギュレータで生成された第１の動作電源の電圧を第２の電源ピンにおいて確認することができる。また、通常動作時において、第１の動作電源の異常が発生したときにも、スイッチ回路をオンさせることにより、第２の電源ピンに接続された安定化容量でもって第１の動作電源の電圧の大きな変動を抑えることができる。   According to the present invention, there is provided a switch circuit for mutually connecting a first power supply wiring to which a first operating power generated by a regulator is supplied and a second power supply wiring connected to a second power supply pin. Therefore, by turning on the switch circuit, the voltage of the first operating power supply generated by the regulator can be confirmed at the second power supply pin. In addition, when an abnormality occurs in the first operating power supply during the normal operation, the voltage of the first operating power supply is maintained with the stabilization capacitor connected to the second power supply pin by turning on the switch circuit. It is possible to suppress large fluctuations.

本発明の半導体集積回路の構成を示すブロック図である。It is a block diagram which shows the structure of the semiconductor integrated circuit of this invention. 図１内のスイッチ回路、制御回路および検知回路の構成を示すブロック図である。It is a block diagram which shows the structure of the switch circuit in FIG. 1, a control circuit, and a detection circuit.

図１に本発明の実施例の半導体集積回路を示す。１は第１の外部電源の電圧Ｖ１が入力する第１の電源ピン、２は接地ピン、３は第２の外部電源の電圧Ｖ２が入力する第２の電源ピンである。１０はCaplessタイプのレギュレータであり、電流源Ｉ１、定電圧ダイオードＺＤ、演算増幅器１１、ＰＭＯＳトランジスタＭＰ１、分圧抵抗Ｒ１，Ｒ２からなる。２０はノイズに弱いマクロやコア等の第１の内部回路、３０はノイズに強いマクロやコア等の第２の内部回路である。４０はスイッチ回路であり、レギュレータ１０の出力側と第１の内部回路２０を接続する第１の電源配線４と、第２の電源ピン３と第２の内部回路３０を接続する第２の電源配線５との間をオン／オフして切り替えする。５０はそのスイッチ回路４０のオン／オフ切り替えを制御する制御回路である。６０は第１の外部電源の電圧Ｖ１の異常を検知する検知回路である。Ｃは第２の電源ピン３と接地ピン２との間に外部接続された安定化容量である。   FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention. Reference numeral 1 denotes a first power supply pin to which the voltage V1 of the first external power supply is input, 2 denotes a ground pin, and 3 denotes a second power supply pin to which the voltage V2 of the second external power supply is input. Reference numeral 10 denotes a Capless type regulator, which includes a current source I1, a constant voltage diode ZD, an operational amplifier 11, a PMOS transistor MP1, and voltage dividing resistors R1 and R2. Reference numeral 20 denotes a first internal circuit such as a macro or core that is vulnerable to noise, and reference numeral 30 denotes a second internal circuit such as a macro or core that is resistant to noise. Reference numeral 40 denotes a switch circuit, a first power supply wiring 4 connecting the output side of the regulator 10 and the first internal circuit 20, and a second power supply connecting the second power supply pin 3 and the second internal circuit 30. The wiring 5 is switched on / off. Reference numeral 50 denotes a control circuit that controls on / off switching of the switch circuit 40. Reference numeral 60 denotes a detection circuit that detects an abnormality in the voltage V1 of the first external power supply. C is a stabilizing capacitor externally connected between the second power supply pin 3 and the ground pin 2.

図２にスイッチ回路４０、制御回路５０および検知回路６０の内部構成を示す。スイッチ回路４０は、ＰＭＯＳトランジスタＭＰ２とＮＭＯＳトランジスタＭＮ１を並列接続したアナログスイッチからなる。制御回路５０は、論理和否定回路ＮＯＲとインバータＩＮＶからなる。５１は制御端子であり、テストモード信号ＶＴが入力する。検知回路６０は、排他的論理和否定回路ＥＸＮＯＲ、ＰＭＯＳトランジスタＭＰ３、ＮＭＯＳトランジスタＭＮ２、抵抗Ｒ３，Ｒ４からなり、排他的論理和否定回路ＥＸＮＯＲから検知信号ＶＳを出力する。６１は定電圧ダイオードＺＤの電圧Ｖrefが入力する基準電圧端子である。   FIG. 2 shows the internal configuration of the switch circuit 40, the control circuit 50, and the detection circuit 60. The switch circuit 40 includes an analog switch in which a PMOS transistor MP2 and an NMOS transistor MN1 are connected in parallel. The control circuit 50 includes a logical sum negation circuit NOR and an inverter INV. Reference numeral 51 denotes a control terminal to which a test mode signal VT is input. The detection circuit 60 includes an exclusive OR negation circuit EXNOR, a PMOS transistor MP3, an NMOS transistor MN2, and resistors R3 and R4, and outputs a detection signal VS from the exclusive OR negation circuit EXNOR. Reference numeral 61 denotes a reference voltage terminal to which the voltage Vref of the constant voltage diode ZD is input.

Caplessタイプのレギュレータ１０では、第１の電源ピン１で受けた第１の外部電源の電圧Ｖ１を入力して、分圧抵抗Ｒ１，Ｒ２の共通接続点の電圧Ｖｆが定電圧ダイオードＺＤの電圧Ｖrefに一致するように、演算増幅器１１によってトランジスタＭＰ１が制御される。これによりレギュレータ１０で生成される第１の動作電源の電圧Ｖ３は、
Ｖ３＝Ｖref ×（１＋（Ｒ１／Ｒ２））
となり、第１の電源配線４に出力される。また、第２の電源ピン３に外部入力する第２の動作電源の電圧Ｖ２は、Ｖ２＝Ｖ３であり、第２の電源配線５に供給される。 In the Capless type regulator 10, the voltage V1 of the first external power supply received at the first power supply pin 1 is input, and the voltage Vf at the common connection point of the voltage dividing resistors R1 and R2 is the voltage Vref of the constant voltage diode ZD. So that the transistor MP1 is controlled by the operational amplifier 11. As a result, the voltage V3 of the first operating power source generated by the regulator 10 is
V3 = Vref × (1+ (R1 / R2))
And output to the first power supply wiring 4. The voltage V2 of the second operating power supply externally input to the second power supply pin 3 is V2 = V3 and is supplied to the second power supply wiring 5.

さて、通常動作時は、制御回路５０の論理和否定回路ＮＯＲの出力がＨレベルとなっていて、スイッチ回路４０はオフされており、第１の内部回路２０にはレギュレータ１０が生成する第１の動作電源の電圧Ｖ３が印加し、第２の内部回路３０には第２の電源ピン３に入力する第２の動作電源の電圧Ｖ２が印加する。これにより、第１、第２の内部回路２０、３０は異なる電源系統で動作する。よって、ノイズに弱い第１の内部回路２０が、ノイズに強い第２の内部回路３０が発するクロック等のノイズの影響を受けるようなことは無い。   During normal operation, the output of the logical sum negation circuit NOR of the control circuit 50 is at the H level, the switch circuit 40 is turned off, and the first internal circuit 20 generates the first generated by the regulator 10. The second operating power supply voltage V2 input to the second power supply pin 3 is applied to the second internal circuit 30. Thus, the first and second internal circuits 20 and 30 operate with different power supply systems. Therefore, the first internal circuit 20 that is vulnerable to noise is not affected by noise such as a clock generated by the second internal circuit 30 that is resistant to noise.

レギュレータ１０が生成する第１の動作電源の電圧Ｖ３を確認（モニタ）するときは、制御回路５０の制御端子５１のテストモード電圧ＶＴをＨレベルにする。これにより、論理和否定回路ＮＯＲの出力がＬレベルとなり、スイッチ回路４０のＰＭＯＳトランジスタＭＰ２，ＮＭＯＳトランジスタＭＮ１がオンする。すなわち、スイッチ回路４０がオンする。よって、第１の電源配線４の電圧Ｖ３が第２の電源配線５を経由して、第２の電源ピン３に出力するので、その第２の電源ピン３において、外部からレギュレータ１０の生成する電圧Ｖ３の確認を行うことができる。なお、このときは、第２の内部回路３０はクロックを停止する等により動作させないようにしておく。   When confirming (monitoring) the voltage V3 of the first operating power supply generated by the regulator 10, the test mode voltage VT of the control terminal 51 of the control circuit 50 is set to the H level. As a result, the output of the logical sum negation circuit NOR becomes L level, and the PMOS transistor MP2 and NMOS transistor MN1 of the switch circuit 40 are turned on. That is, the switch circuit 40 is turned on. Therefore, since the voltage V3 of the first power supply wiring 4 is output to the second power supply pin 3 via the second power supply wiring 5, the regulator 10 is generated from the outside at the second power supply pin 3. The voltage V3 can be confirmed. At this time, the second internal circuit 30 is not operated by stopping the clock or the like.

第１の電源ピン１に外部からＥＳＤ等の強い外来ノイズが印加され、レギュレータ１０の基準電圧Ｖreｆが一時的（数μsec以上）に異常に高くなったときは、検知回路６０の基準電圧端子６１の電圧Ｖrefが高くなり、これによって、トランジスタＭＰ３がオフ、トランジスタＭＮ２がオンとなって、抵抗Ｒ３とトランジスタＭＰ３の共通接続点の電圧ＶａがＬレベルに、抵抗Ｒ４とトランジスタＭＮ２の共通接続点の電圧ＶｂもＬレベルとなり、排他的論理和否定回路ＥＸＮＯＲの出力電圧ＶＳがＨレベルとなり、これにより制御回路５０の論理和否定回路ＮＯＲの出力がＬレベルとなって、スイッチ回路４０がオンする。よって、第１の電源配線４が第２の電源ピン３に接続される。この第２の電源ピン３には安定化容量Ｃが接続されているので、レギュレータ１０で生成される第１の動作電源の電圧Ｖ３の変動がその安定化容量Ｃで吸収される。   When strong external noise such as ESD is externally applied to the first power supply pin 1 and the reference voltage Vref of the regulator 10 becomes abnormally high temporarily (several μsec or more), the reference voltage terminal 61 of the detection circuit 60 As a result, the transistor MP3 is turned off, the transistor MN2 is turned on, the voltage Va at the common connection point between the resistor R3 and the transistor MP3 is set to the L level, and the common connection point between the resistor R4 and the transistor MN2 is turned on. The voltage Vb also becomes L level, the output voltage VS of the exclusive OR negation circuit EXNOR becomes H level, thereby the output of the OR sum NOR circuit of the control circuit 50 becomes L level, and the switch circuit 40 is turned on. Therefore, the first power supply wiring 4 is connected to the second power supply pin 3. Since the stabilization capacitor C is connected to the second power supply pin 3, the fluctuation of the voltage V3 of the first operating power supply generated by the regulator 10 is absorbed by the stabilization capacitor C.

また、同様の理由等でレギュレータ１０の基準電圧Ｖreｆが一時的（数μsec以上）に異常に低くなったときは、検知回路６０の基準電圧端子６１の電圧Ｖrefが低くなり、これによって、トランジスタＭＰ３がオン、トランジスタＭＮ２がオフとなって、電圧ＶａがＨレベルに、電圧ＶｂもＨレベルとなり、排他的論理和否定回路ＥＸＮＯＲの出力電圧ＶＳがＨレベルとなり、スイッチ回路４０がオンし、このときも、レギュレータ１０の出力電圧Ｖ３の変動がその安定化容量Ｃで吸収される。   Further, when the reference voltage Vref of the regulator 10 temporarily becomes abnormally low (several μsec or more) for the same reason, the voltage Vref of the reference voltage terminal 61 of the detection circuit 60 becomes low, thereby causing the transistor MP3. Is turned on, the transistor MN2 is turned off, the voltage Va becomes H level, the voltage Vb also becomes H level, the output voltage VS of the exclusive OR negation circuit EXNOR becomes H level, and the switch circuit 40 is turned on. However, the fluctuation of the output voltage V3 of the regulator 10 is absorbed by the stabilization capacitor C.

このように、第１の電源ピン１に入力する第１の外部電源電圧Ｖ１が正常値から異常に高くなったり低くなったりして、基準電圧Ｖｒｅｆが異常に高く、もしくは低くなると、レギュレータ１０が生成する第１の動作電源の電圧Ｖ３も変動し、異常値を示す。すなわち、図２に示した検知回路６０は、基準電圧Ｖｒｅｆを監視することによって第１の動作電源の異常を検知する。   Thus, when the first external power supply voltage V1 input to the first power supply pin 1 becomes abnormally high or low from the normal value, and the reference voltage Vref becomes abnormally high or low, the regulator 10 The voltage V3 of the first operating power supply to be generated also varies and shows an abnormal value. That is, the detection circuit 60 shown in FIG. 2 detects an abnormality in the first operating power supply by monitoring the reference voltage Vref.

もちろん、第１の動作電源の電圧Ｖ３を監視することによって第１の動作電源の異常を検知することも可能である。しかし、基準電圧Ｖｒｅｆを監視することにより、より早いタイミングで第１の動作電源の異常を検知することが可能である。そして、制御回路５０が検知回路６０による検知結果に基づいてスイッチ回路４０を制御することにより、一時的にスイッチ回路４０がオンとなって、安定化容量Ｃが接続される。これによって、レギュレータ１０が生成する第１の動作電源の電圧Ｖ３の変動を抑制することができる。   Of course, it is also possible to detect an abnormality in the first operating power supply by monitoring the voltage V3 of the first operating power supply. However, by monitoring the reference voltage Vref, it is possible to detect an abnormality in the first operating power supply at an earlier timing. The control circuit 50 controls the switch circuit 40 based on the detection result by the detection circuit 60, so that the switch circuit 40 is temporarily turned on and the stabilization capacitor C is connected. As a result, fluctuations in the voltage V3 of the first operating power supply generated by the regulator 10 can be suppressed.

図１に示した例では、第２の内部回路３０に、電源ピン３を利用して外部から供給した電源をそのまま、第２の動作電源として供給した。しかし、レギュレータ１０とは別の第２のレギュレータを半導体集積回路内に設け、第２のレギュレータが生成する電源を、第２の動作電源として第２の内部回路３０に供給することも可能である。ただし、第２のレギュレータはCaplessタイプではなく、外付け容量を必要とするタイプであるとする。この場合、第２の電源配線５は、第２のレギュレータの出力と第２の内部回路３０とを接続する配線であり、電源ピン３は、第２のレギュレータの出力に外付けの容量を接続するためのピンとして使用される。   In the example shown in FIG. 1, the power supplied from the outside using the power pin 3 is supplied to the second internal circuit 30 as it is as the second operating power. However, a second regulator different from the regulator 10 can be provided in the semiconductor integrated circuit, and the power generated by the second regulator can be supplied to the second internal circuit 30 as the second operating power. . However, the second regulator is not a Capless type, but a type that requires an external capacity. In this case, the second power supply wiring 5 is a wiring for connecting the output of the second regulator and the second internal circuit 30, and the power supply pin 3 connects an external capacitor to the output of the second regulator. Used as a pin to do.

１：第１の電源ピン、２：接地ピン、３：第２の電源ピン、４：第１の電源配線、５：第２の電源配線、Ｖ１：第１の外部電源の電圧、Ｖ２：第２の動作電源の電圧、Ｖ３：第１の動作電源の電圧
１０：レギュレータ、１１：演算増幅器
２０：第１の内部回路
３０：第２の内部回路
４０：スイッチ回路
５０：制御回路、５１：制御端子
６０：検知回路、６１：基準電圧端子
1: first power supply pin, 2: ground pin, 3: second power supply pin, 4: first power supply wiring, 5: second power supply wiring, V1: voltage of first external power supply, V2: first power supply wiring Voltage of operating power source 2 V3: Voltage of first operating power source 10: Regulator, 11: Operational amplifier 20: First internal circuit 30: Second internal circuit 40: Switch circuit 50: Control circuit, 51: Control Terminal 60: Detection circuit, 61: Reference voltage terminal

Claims (4)

第１および第２の内部回路を有する半導体集積回路であって、
第１の外部電源の供給を受ける第１の電源ピンと、
前記第１の外部電源から第１の動作電源を生成するレギュレータと、
前記第１の動作電源を前記第１の内部回路に供給する第１の電源配線と、
前記第１の動作電源の電圧と同一電圧を有する第２の動作電源の供給を受ける第２の電源ピンと、
前記第２の動作電源を前記第２の内部回路に供給する第２の電源配線と、
オン状態において前記第１の電源配線と前記第２の電源配線とを相互に接続するスイッチ回路と、
前記第１の内部回路が前記第１の動作電源の供給を受けて動作する通常動作時に、前記スイッチ回路をオフ状態に制御する制御回路と、
を備えることを特徴とする半導体集積回路。 A semiconductor integrated circuit having first and second internal circuits,
A first power supply pin receiving a first external power supply;
A regulator that generates a first operating power supply from the first external power supply;
First power supply wiring for supplying the first operating power supply to the first internal circuit;
A second power supply pin for receiving a second operating power supply having the same voltage as that of the first operating power supply;
A second power supply wiring for supplying the second operating power supply to the second internal circuit;
A switch circuit for connecting the first power supply wiring and the second power supply wiring to each other in an on state;
A control circuit for controlling the switch circuit to an off state during a normal operation in which the first internal circuit operates by receiving the supply of the first operating power;
A semiconductor integrated circuit comprising: 前記制御回路が、前記第１の動作電源の電圧をモニタする試験状態を示す信号が入力されたときに、前記スイッチ回路をオン状態に制御することを特徴とする請求項１に記載の半導体集積回路。   2. The semiconductor integrated circuit according to claim 1, wherein the control circuit controls the switch circuit to an ON state when a signal indicating a test state for monitoring a voltage of the first operating power supply is input. circuit. 前記第１の動作電源の異常を検知したときに検知信号を生成して前記制御回路に入力する検知回路をさらに備え、
前記制御回路が、前記検知信号が入力されたときに、前記スイッチ回路をオン状態に制御することを特徴とする請求項１又は２に記載の半導体集積回路。 A detection circuit for generating a detection signal and inputting the detection signal to the control circuit when an abnormality of the first operating power supply is detected;
3. The semiconductor integrated circuit according to claim 1, wherein the control circuit controls the switch circuit to be in an on state when the detection signal is input. 前記第２の電源ピンに安定化容量が接続されていることを特徴とする請求項１ないし３のいずれかに記載の半導体集積回路。   4. The semiconductor integrated circuit according to claim 1, wherein a stabilization capacitor is connected to the second power supply pin.
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