JP5376706B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP5376706B2 JP5376706B2 JP2007294261A JP2007294261A JP5376706B2 JP 5376706 B2 JP5376706 B2 JP 5376706B2 JP 2007294261 A JP2007294261 A JP 2007294261A JP 2007294261 A JP2007294261 A JP 2007294261A JP 5376706 B2 JP5376706 B2 JP 5376706B2
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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Description
本実施の形態において、陽極又は陰極として機能する導電層の側壁部にサイドウォール絶縁層を有するメモリ素子の構成について説明する。
本実施の形態において、実施の形態1で示したメモリ素子を有する半導体装置の作製工程について図面を用いて説明する。本実施の形態では、メモリ素子を有する半導体装置の例として外部と無線通信が可能な無線チップについて説明する。
本発明を用いた半導体装置の構成例について、図9を参照して説明する。図9に示すように、本発明の半導体装置1520は、非接触でデータを交信する機能を有し、電源回路1511、クロック発生回路1512、データ復調/変調回路1513、他の回路を制御する制御回路1514、インターフェイス回路1515、記憶回路1516、データバス1517、アンテナ1518、センサ1523a、センサ回路1523bを有する。図9において、駆動回路とは、電源回路1511、クロック発生回路1512、データ復調/変調回路1513、他の回路を制御する制御回路1514、及びインターフェイス回路1515を指している。
本発明により無線チップとして機能する半導体装置1520を形成することができる。無線チップの用途は広範にわたるが、例えば、紙幣、硬貨、有価証券類、無記名債券類、証書類(運転免許証や住民票等、図10(A))、包装用容器類(包装紙やボトル等、図10(C))、記録媒体(DVDソフトやビデオテープ等、図10(B))、乗物類(自転車等、図10(D))、身の回り品(鞄や眼鏡等)、食品類、植物類、動物類、衣類、生活用品類、電子機器等の商品や荷物の荷札(図10(E)、図10(F))等の物品に設けて使用することができる。電子機器とは、液晶表示装置、EL表示装置、テレビジョン装置(単にテレビ、テレビ受像機、テレビジョン受像機とも呼ぶ)及び携帯電話等を指す。
また、本発明の半導体装置はワード線やビット線となる配線の交点部分にメモリ素子を作製しても書き込み特性のばらつきを抑えることができるため、小型化、高集積化が容易である。それによって、大容量の記憶回路を有する半導体装置を用いた電子機器を提供することができる。
11 電極
12 サイドウォール絶縁層
13 シリコン膜
14 電極
21 領域
Claims (6)
- 同一基板上に複数の薄膜トランジスタと、複数のメモリ素子とを有する半導体装置の作製方法であって、
絶縁表面を有する基板上に第1の半導体層及び第2の半導体層を形成し、
前記第1の半導体層及び前記第2の半導体層上に第1の絶縁膜を形成し、
前記第1の半導体層上に前記第1の絶縁膜を介して第1の導電層を形成し、
前記第2の半導体層上に前記第1の絶縁膜を介して第2の導電層を形成し、
前記第2の導電層の側壁部に第1の絶縁層を形成し、
前記第1の導電層、前記第2の導電層、及び前記第1の絶縁層を覆う第2の絶縁膜を形成し、
前記第2の絶縁膜をエッチングして、前記第2の導電層、前記第1の絶縁層及び前記第2の半導体層を露出する第1の開口を形成し、
前記第2の導電層上及び前記第1の絶縁層を覆って第3の半導体層を形成し、
前記第2の絶縁膜をエッチングして前記第1の半導体層の一部を露出する第2の開口を形成し、
前記第3の半導体層上に第3の導電層を形成し、
前記第1の半導体層上に第4の導電層を形成し、
前記第2の導電層又は前記第3の導電層を、前記第3の半導体層と合金化する材料で形成し、
前記第1の導電層及び前記第2の導電層を同一工程で形成し、
前記第3の導電層及び前記第4の導電層を同一工程で形成することを特徴とする半導体装置の作製方法。 - 請求項1において、
前記第1の絶縁層を、湾曲している面を有するように形成し、
前記第3の半導体層を、前記第1の絶縁層の湾曲している面で接するように形成することを特徴とする半導体装置の作製方法。 - 請求項1又は請求項2において、
前記第1の導電層の側壁部に第2の絶縁層を、前記第1の絶縁層と同一工程で作製することを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項3のいずれか一項において、
前記第3の導電層及び前記第4の導電層の形成と同じ工程で前記第2の絶縁膜上に第5の導電層を形成し、
前記第5の導電層上に前記第5の導電層と電気的に接続するアンテナを形成することを特徴とする半導体装置の作製方法。 - 請求項1乃至4のいずれか一項において、
前記第2の導電層又は前記第3の導電層のうち少なくともどちらか一方は、Ti、W、Ni、Cr、Mo、Ta、Co、Zr、V、Pd、Hf、Pt、Feから選ばれた少なくとも一の元素を含む材料からなることを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項5のいずれか一項において、
前記絶縁表面を有する基板は、ガラス基板、プラスチック基板、半導体基板、又は紙であ
ることを特徴とする半導体装置の作製方法。
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JP5371400B2 (ja) * | 2007-12-14 | 2013-12-18 | 株式会社半導体エネルギー研究所 | メモリ及び半導体装置 |
US7872934B2 (en) * | 2007-12-14 | 2011-01-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for writing data into memory |
JP5358324B2 (ja) | 2008-07-10 | 2013-12-04 | 株式会社半導体エネルギー研究所 | 電子ペーパー |
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JP5641840B2 (ja) * | 2009-10-01 | 2014-12-17 | 株式会社半導体エネルギー研究所 | 半導体装置 |
WO2011074407A1 (en) * | 2009-12-18 | 2011-06-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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2007
- 2007-10-30 KR KR1020070109342A patent/KR101416876B1/ko active IP Right Grant
- 2007-11-13 US US11/979,992 patent/US8759946B2/en not_active Expired - Fee Related
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JP2008147640A (ja) | 2008-06-26 |
KR101416876B1 (ko) | 2014-07-08 |
US8759946B2 (en) | 2014-06-24 |
US20080116500A1 (en) | 2008-05-22 |
KR20080044763A (ko) | 2008-05-21 |
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