JP5261384B2 - 透明導電ナノ構造膜画素電極およびその製造方法 - Google Patents
透明導電ナノ構造膜画素電極およびその製造方法 Download PDFInfo
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Description
本発明のさらなる実施形態では、ナノ構造膜の層は、デバイス基板の様々な部分の上に異なる厚さで形成されてもよい。このような製造は、選択的なナノ構造膜の付着および/またはパターン形成技術によって達成することができる。
本発明の別の限定されない例示的な実施形態によれば、ナノチューブの相互接続ネットワークを含む透明導電ナノ構造膜を、噴射法によって平坦でない試験表面上に付着した。
本発明の別の特定の限定されない例示的な実施形態によれば、ナノチューブの相互接続ネットワークを含む透明導電ナノ構造膜を、プレス法(あるいは、「転写」と称される)を使用して第2の平坦でない試験表面上に付着させた。
図18Aおよび図18Bを参照して、本発明の実施形態によるナノ構造膜画素電極は、液晶ディスプレイ(LCD)、特に前述した活性マトリクスLCDで使用することができる。このデバイスは、2つの基板の間に注入される液晶材料1830を含み、電極1810、1850、および結晶配向層1820、1840がその基板上に付着されてもよい。少なくとも1つの電極層は、ナノ構造膜画素電極を含むのが好ましい。
図19を参照して、本発明の実施形態によるナノ構造膜画素電極は、エレクトロルミネセンス(EL)デバイスで使用されてもよく、このデバイスでは、活性層材料をドーピングすることによって電子と正孔とが分離している(例えば、有機発光ダイオード(OLED)の場合のようにp−n接合を形成している)。このデバイスは、EL活性層1920(例えば、ポリマーおよび/または小分子に基づく材料)を含むのが好ましく、アノード1910およびカソード1930からそれぞれ正孔および電子がそこに注入され、アノード1910およびカソード1930のうちの少なくとも1つは、透明導電ナノ構造膜を含む。このデバイスは、少なくとも1つの緩衝層1940、1950(例えば、TPD−Si2 、TFB、CuPcおよび/またはCs2 CO3 )をさらに含んでもよい。
Claims (15)
- ナノチューブの相互接続ネットワークを含むナノ構造膜を含む画素電極であって、
前記画素電極が、下にある電極と電気的に接触し、かつ平坦でない表面である薄膜トランジスタ(TFT)基板上に付着され、電気的に導電性であるとともに光学的に透明であり、
前記下にある電極および前記画素電極が、保護層によって隔てられ、
前記下にある電極が、トランジスタのソース電極およびドレイン電極のうちの1つであり、
前記画素電極が、前記保護層のコンタクトホールを介して前記下にある電極と電気的に接触し、かつ前記コンタクトホールの段差を覆って形成される画素電極。 - 請求項1記載の画素電極において、
前記保護層が、シリコン窒化物を含む画素電極。 - 請求項2記載の画素電極において、
前記画素電極が、第1の部分と第2の部分とを含み、前記第1の部分が、前記第2の部分よりも厚い画素電極。 - 請求項3記載の画素電極において、
前記コンタクトホールが、少なくとも300nmの深さである画素電極。 - 請求項4記載の画素電極において、
前記画素電極が、550nmで少なくとも85%の光透過率および少なくとも300オーム/スクエアの対応するシート抵抗を有する画素電極。 - 請求項1〜5に記載の画素電極を含む活性マトリクス画素化デバイスであって、
前記画素電極が、第1のナノ構造膜を含み、
前記画素電極が、保護層のコンタクトホールを介して下にあるトランジスタ電極と電気的に接触する活性マトリクス画素化デバイス。 - 請求項6記載の画素化デバイスにおいて、
補助パッドをさらに含み、前記補助パッドが、第2のナノ構造膜を含み、
前記補助パッドが、前記保護層を貫通するパッドコンタクトホールを介して下にあるパッドと電気的に接触する画素化デバイス。 - 請求項7記載の画素化デバイスにおいて、
前記パッドが、ゲートパッドおよびデータパッドのうちの少なくとも1つであり、
前記補助パッドが、補助ゲートパッドおよび補助データパッドのうちの少なくとも1つであり、
前記下にあるトランジスタ電極が、トランジスタのソース電極およびドレイン電極のうちの1つである画素化デバイス。 - 請求項8記載の画素化デバイスにおいて、
前記第1のナノ構造膜および前記第2のナノ構造膜のうちの少なくとも1つが、ナノチューブの相互接続ネットワークを含む画素化デバイス。 - 請求項6記載の画素化デバイスにおいて、
前記下にあるトランジスタ電極が、第3のナノ構造膜を含む画素化デバイス。 - 平坦でない表面である薄膜トランジスタ基板上にナノ構造膜を付着させるステップおよび前記ナノ構造膜をパターン形成するステップを含む画素電極の作製方法であって、
前記画素電極が、光学的に透明であるとともに電気的に導電性であり、
前記画素電極が、前記画素電極と下にある電極とを隔てる保護層のコンタクトホールを介して前記下にある電極と電気的に接触し、
前記下にある電極が、トランジスタのソース電極およびドレイン電極のうちの1つであり、前記コンタクトホールの段差を覆って形成される画素電極の作製方法。 - 請求項11記載の画素電極において、
前記保護層が、シリコン窒化物を含む画素電極の作製方法。 - 請求項12記載の画素電極において、
前記画素電極が、第1の部分と第2の部分とを含み、前記第1の部分が、前記第2の部分よりも厚い画素電極の作製方法。 - 請求項13記載の画素電極において、
前記コンタクトホールが、少なくとも300nmの深さである画素電極の作製方法。 - 請求項14記載の画素電極において、
前記画素電極が、550nmで少なくとも85%の光透過率および少なくとも300オーム/スクエアの対応するシート抵抗を有する画素電極の作製方法。
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