JP5257539B2 - Circuit board manufacturing method - Google Patents
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本発明は、高密度の導体回路をプリント配線板に形成する回路基板の製造方法に関するものである。 The present invention relates to a circuit board manufacturing method for forming a high-density conductor circuit on a printed wiring board.
このような導体回路を形成する導電材料としては、化学的に安定しており、電気抵抗が小さいことが要求されているが、従来から用いられている導電材料でこれらの条件を満足する材料がなかった。 As a conductive material for forming such a conductor circuit, it is required to be chemically stable and to have a small electric resistance. However, a conductive material that has been used conventionally and satisfies these conditions is used. There wasn't.
このような状況から、化学的に安定しており、電気抵抗が小さい導電材料が要望されている。 Under such circumstances, there is a demand for a conductive material that is chemically stable and has low electrical resistance.
電子部品を搭載するプリント配線板に形成する導体回路に対しては高密度に形成することが要求されており、近年、導電材料をスルーホール或いはビアホール内に埋め込んで上下の配線層の接続を行う、インナービアホール（ＩＶＨ）や、ブラインドビアホール等を高密度に設け、電子部品の高密度な実装が可能なプリント配線板が用いられるようになっている。 Conductor circuits formed on printed wiring boards on which electronic components are mounted are required to be formed with high density. In recent years, conductive materials are embedded in through holes or via holes to connect upper and lower wiring layers. In addition, printed wiring boards capable of mounting electronic components at high density by providing inner via holes (IVH), blind via holes, and the like with high density are used.
このようなプリント配線板に導体回路を形成する方法としては、プリント配線板の全面に導体回路となる金属膜が形成されている材料を、フォトリソグラフィー技術を用いて不要な金属膜をエッチングにより除去して導体回路を形成するサブトラクティブ法が用いられていたが、低コスト化を図るために、銀、銅、カーボン等の導電材料の粒子と、溶剤で溶解したバインダーとを含む導電性ペーストの被膜を、スクリーン印刷によりプリント配線板の表面に形成し、又、インナービアホール（ＩＶＨ）やブラインドビアホール内に形成し、硬化処理により導体回路を形成する方法が用いられるようになっている。 As a method of forming a conductor circuit on such a printed wiring board, a material in which a metal film to be a conductor circuit is formed on the entire surface of the printed wiring board is removed by etching the unnecessary metal film using a photolithography technique. In order to reduce the cost, a conductive paste containing conductive material particles such as silver, copper, and carbon and a binder dissolved in a solvent is used. A method is used in which a film is formed on the surface of a printed wiring board by screen printing or in an inner via hole (IVH) or a blind via hole, and a conductor circuit is formed by a curing process.
また、複数の粒子からなり、各粒子が導電性コーティングを有し、このコーティングが溶融して隣接する粒子上に導電性コーティングを形成し、溶融した粒子の網状構造を形成する、導電性材料が特開平０８−２２７６１３号公報に開示されている。
以上説明した従来のスクリーン印刷によって導体回路を形成する方法においては、導電性ペーストに用いている導電材料が銀の場合には、図５に示すように電気抵抗値が5.0×10-5Ω・cmで導電性は優れているが、硫黄と反応して硫化銀になったり、マイグレーションを起こすという問題点があり、導電性ペーストに用いている導電材料が銅の場合には、図５に示すように電気抵抗値が 2.5×10-4Ω・cmで導電性が銀よりも劣るという問題点があり、導電性ペーストに用いている導電材料がカーボンの場合には、硫黄と反応して硫化したり、マイグレーションを起こすことはないが、図５に示すように電気抵抗値が 3.0×10-2Ω・cmで導電性が銅よりも更に劣るという問題点がある。 In the conventional method of forming a conductor circuit by screen printing as described above, when the conductive material used for the conductive paste is silver, the electric resistance value is 5.0 × 10 −5 Ω · Although the conductivity is excellent at cm, there is a problem that it reacts with sulfur to become silver sulfide or causes migration, and when the conductive material used for the conductive paste is copper, it is shown in FIG. Thus, there is a problem that the electrical resistance value is 2.5 × 10 −4 Ω · cm and the conductivity is inferior to silver, and when the conductive material used in the conductive paste is carbon, it reacts with sulfur and sulfide However, there is a problem that the electrical resistance is 3.0 × 10 −2 Ω · cm and the conductivity is inferior to copper as shown in FIG.
積層セラミック電子部品の端子電極に用いられる導電性の金属ペーストに関する発明が特開平02-46603号により公開されており、この発明においては、銅粉末の表面に亜鉛をコーティングした複合金属粉末を積層セラミック電子部品の端子電極として用いているので、 500〜600 ℃で焼結すると、亜鉛と銅の間で相互拡散が進み、亜鉛部分が黄銅となり密度の高い焼結体を得ることができ、また、銅粉末を黄銅で囲むことにより、銅端子電極表面が酸化するのを防止している。 An invention relating to a conductive metal paste used for a terminal electrode of a multilayer ceramic electronic component has been disclosed in Japanese Patent Application Laid-Open No. 02-46603. In this invention, a composite metal powder coated with zinc on the surface of a copper powder is laminated with a multilayer ceramic. Since it is used as a terminal electrode for electronic parts, when it is sintered at 500 to 600 ° C., interdiffusion proceeds between zinc and copper, and the zinc part becomes brass and a high-density sintered body can be obtained. By surrounding the copper powder with brass, the surface of the copper terminal electrode is prevented from being oxidized.
この公知例は、二種類の金属元素の間で形成される合金の融点は各元素の融点よりも低温になることを利用した発明である。 This known example is an invention that utilizes the fact that the melting point of an alloy formed between two types of metal elements is lower than the melting point of each element.
一方、二種類の金属元素の間で形成される金属間化合物の融点は、二種類の金属元素の低い方の融点よりも高くなる。 On the other hand, the melting point of the intermetallic compound formed between the two types of metal elements is higher than the lower melting point of the two types of metal elements.
本発明は以上のような状況から、プリント配線板の絶縁基板の耐熱温度よりも高い融点を有し、電子部品のはんだ付け温度に耐えることが可能な金属間化合物からなる導体材料を有する回路基板の製造方法の提供を目的としたものである。 In view of the above situation, the present invention provides a circuit board having a conductive material made of an intermetallic compound that has a melting point higher than the heat resistance temperature of the insulating board of the printed wiring board and can withstand the soldering temperature of electronic components. The purpose is to provide a manufacturing method.
本発明の一観点によれば、基板のビアホール内に、第１の金属からなる複数の粒子と、前記第１の金属の融点より低い融点を有する第２の金属からなる複数の粒子とを含む導電性ペーストを供給し、前記基板を加熱して、前記第１の金属と前記第２の金属との金属間化合物内に前記複数の粒子が分散した導体を形成する回路基板の製造方法であって、前記基板にはんだを使用して電子部品を搭載可能であり、前記金属間化合物の融点が前記はんだの溶融温度よりも高いことを特徴とする回路基板の製造方法が提供される。 According to one aspect of the present invention, the via hole of the substrate includes a plurality of particles made of the first metal and a plurality of particles made of the second metal having a melting point lower than the melting point of the first metal. A method of manufacturing a circuit board, comprising supplying a conductive paste and heating the substrate to form a conductor in which the plurality of particles are dispersed in an intermetallic compound of the first metal and the second metal. An electronic component can be mounted on the substrate using solder, and the circuit board manufacturing method is characterized in that the melting point of the intermetallic compound is higher than the melting temperature of the solder.
基板の耐熱温度よりも高い融点を有する導体回路を低温で形成することができる。 A conductor circuit having a melting point higher than the heat resistant temperature of the substrate can be formed at a low temperature.
以下の実施形態においては、導電性ペースト中の導電材料の核となる金属とこの核の表面に被膜として形成されている金属が、プリント配線板の絶縁基板の耐熱温度(260℃)以下の低温で溶融し、結合して金属間化合物が形成されるが、この核となる金属と被膜として形成されていた金属との金属間化合物の融点が、この金属間化合物からなる導体回路を形成したこの絶縁基板の耐熱温度よりも高く、熱的に安定しており、電子部品をプリント配線板に搭載する場合のはんだ付け温度(220℃〜 240℃) では再溶融することはない。また金属間化合物の電気抵抗値はプリント配線板の導体回路として用いることが可能な値を有しているので、以下の実施形態の導電材料及び導電性ペーストを用いて形成した導体回路を備えたプリント配線板に電子部品を搭載することが可能となる。 In the following embodiments, the metal that is the core of the conductive material in the conductive paste and the metal that is formed as a coating on the surface of the core are a low temperature that is not higher than the heat resistance temperature (260 ° C.) of the insulating substrate of the printed wiring board. In this case, the melting point of the intermetallic compound between the core metal and the metal formed as a coating film forms a conductor circuit composed of the intermetallic compound. It is higher than the heat resistance temperature of the insulating substrate and is thermally stable, and it does not remelt at the soldering temperature (220 ° C to 240 ° C) when mounting electronic components on a printed wiring board. Moreover, since the electrical resistance value of the intermetallic compound has a value that can be used as a conductor circuit of a printed wiring board, a conductor circuit formed using the conductive material and conductive paste of the following embodiment is provided. Electronic components can be mounted on the printed wiring board.
また、複数種の金属の粒子からなる導電材料が、プリント配線板の絶縁基板の耐熱温度(260℃) 以下の温度で溶融し、結合して金属間化合物が形成されるが、この複数種の金属のうちの少なくとも二つの金属の金属間化合物の融点が、この金属間化合物からなる導体回路を形成したこの絶縁基板の耐熱温度よりも高く、熱的に安定しており、電子部品をプリント配線板に搭載する場合のはんだ付け温度(220℃〜 240℃) では再溶融することはない。また金属間化合物の電気抵抗値はプリント配線板の導体回路として用いることが可能な値を有しているので、以下の実施形態の導電材料及び導電性ペーストを用いて形成した導体回路を備えたプリント配線板に電子部品を搭載することが可能となる。 In addition, a conductive material composed of a plurality of types of metal particles melts at a temperature equal to or lower than the heat resistance temperature (260 ° C.) of the insulating substrate of the printed wiring board and forms an intermetallic compound. The melting point of the intermetallic compound of at least two of the metals is higher than the heat resistance temperature of the insulating substrate on which the conductor circuit made of the intermetallic compound is formed, and is thermally stable. It does not remelt at the soldering temperature (220 ° C to 240 ° C) when mounted on a plate. Moreover, since the electrical resistance value of the intermetallic compound has a value that can be used as a conductor circuit of a printed wiring board, a conductor circuit formed using the conductive material and conductive paste of the following embodiment is provided. Electronic components can be mounted on the printed wiring board.
以下図１〜図４により本発明の実施例について詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.
図１は本発明の導電材料の構成を示す模式図、図２は本発明の導電材料において形成された金属間化合物の構成を示す模式図、図３は本発明に使用する他の導電材料の構成を示す模式図、図４は本発明の実施例により形成した導体回路の電気抵抗値を示す図である。 FIG. 1 is a schematic diagram showing the configuration of the conductive material of the present invention, FIG. 2 is a schematic diagram showing the configuration of an intermetallic compound formed in the conductive material of the present invention, and FIG. 3 is another conductive material used in the present invention. FIG. 4 is a diagram showing the electrical resistance value of the conductor circuit formed by the embodiment of the present invention.
本発明の第１の実施例においては、径が約５μm の銅の粒子の表面に、厚さ１μm のインジウムの被膜を無電界めっき法にて形成した導電フィラー 900ｇと、ビスフェノールＡ50ｇと、ジアミノジフェニルメタン５ｇ及びエチレングリコールジグリシジルエーテル45ｇを混合して導電性ペーストを作り、この導電性ペーストをスクリーン印刷法によりガラス布基材エポキシ樹脂基板（以下、ガラスエポキシ基板と略称する)(耐熱温度 260℃）の表面に印刷した後、180秒間加熱し、銅とインジウムの金属間化合物からなる線幅150μm 、厚さ10μm の導体回路を形成した。この金属間化合物の融点ははんだの溶融温度(220〜240 ℃) よりもずっと高いので、電子部品をプリント配線板に搭載する場合のはんだ付け温度(220℃〜 240℃) では再溶融することはない。 In the first embodiment of the present invention, 900 g of a conductive filler in which a 1 μm thick indium film is formed on the surface of copper particles having a diameter of about 5 μm by electroless plating, 50 g of bisphenol A, and diaminodiphenylmethane. 5g and 45g of ethylene glycol diglycidyl ether are mixed to make a conductive paste, and this conductive paste is a glass cloth base epoxy resin substrate (hereinafter abbreviated as glass epoxy substrate) by screen printing method (heat-resistant temperature 260 ° C) After printing on the surface, the substrate was heated for 180 seconds to form a conductor circuit made of an intermetallic compound of copper and indium having a line width of 150 μm and a thickness of 10 μm. Since the melting point of this intermetallic compound is much higher than the melting temperature of the solder (220 to 240 ° C), it cannot be remelted at the soldering temperature (220 ° C to 240 ° C) when mounting electronic components on a printed wiring board. Absent.
また、この導電性ペーストを 150μm 径のビアに埋め込み、210 ℃で 180秒間加熱した。 The conductive paste was embedded in a 150 μm diameter via and heated at 210 ° C. for 180 seconds.
この導体回路及びビアを四端子法により測定した値は、図４に示すように5.0 ×10-6Ω・cmであった。 The value of this conductor circuit and via measured by the four probe method was 5.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第２の実施例においては、第１の実施例と同じ銅の粒子の表面に、厚さ１μmの錫の被膜を無電界めっき法にて形成した導電フィラー 900ｇと、第１の実施例と同じ薬品とを混合して導電性ペーストを作り、この導電性ペーストをスクリーン印刷法により第１の実施例と同様に導体回路とビアを形成し、同様にこの導体回路及びビアを四端子法により測定した。その測定値は図４に示すように8.0 ×10-6Ω・cmであった。 In the second embodiment of the present invention, 900 g of a conductive filler in which a 1 μm thick tin film is formed on the surface of the same copper particles as in the first embodiment by an electroless plating method; A conductive paste is made by mixing the same chemicals as in the example, and the conductive paste is formed by screen printing in the same manner as in the first embodiment to form a conductive circuit and a via. Measured by the method. The measured value was 8.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第３の実施例においては、第２の実施例とは異なる銀の粒子の表面に、厚さ１μmのインジウムの被膜を無電界めっき法にて形成した導電フィラー 900ｇと、第１の実施例と同じ薬品とを混合して導電性ペーストを作り、この導電性ペーストをスクリーン印刷法により第１の実施例と同様に導体回路とビアを形成し、同様にこの導体回路及びビアを四端子法により測定した。その測定値は、図４に示すように5.0 ×10-6Ω・cmであった。 In the third embodiment of the present invention, 900 g of a conductive filler in which an indium film having a thickness of 1 μm is formed on the surface of silver particles different from that of the second embodiment by an electroless plating method, A conductive paste is prepared by mixing the same chemicals as in the example, and a conductive circuit and a via are formed by screen printing in the same manner as in the first example. It was measured by the terminal method. The measured value was 5.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第４の実施例においては、第３の実施例と同じ銀の粒子の表面に、厚さ１μmの錫の被膜を無電界めっき法にて形成した導電フィラー 900ｇと、第１の実施例と同じ薬品とを混合して導電性ペーストを作り、この導電性ペーストをスクリーン印刷法により第１の実施例と同様に導体回路とビアを形成し、同様にこの導体回路及びビアを四端子法により測定した。その測定値は、図４に示すように8.0 ×10-6Ω・cmであった。 In the fourth embodiment of the present invention, 900 g of a conductive filler in which a 1 μm thick tin film is formed on the surface of the same silver particles as in the third embodiment by electroless plating, A conductive paste is made by mixing the same chemicals as in the example, and the conductive paste is formed by screen printing in the same manner as in the first embodiment to form a conductive circuit and a via. Measured by the method. The measured value was 8.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第５の実施例においては、ニッケルの粒子の表面に、厚さ１μm のインジウムの被膜を無電界めっき法にて形成した導電フィラー 900ｇと、第１の実施例と同じ薬品とを混合して導電性ペーストを作り、この導電性ペーストをスクリーン印刷法により第１の実施例と同様に導体回路とビアを形成し、同様にこの導体回路及びビアを四端子法により測定した。その測定値は、図４に示すように8.0 ×10-6Ω・cmであった。 In the fifth embodiment of the present invention, 900 g of a conductive filler in which an indium film having a thickness of 1 μm is formed on the surface of nickel particles by an electroless plating method and the same chemical as in the first embodiment are mixed. Then, a conductive paste was prepared, and a conductive circuit and a via were formed by the screen printing method in the same manner as in the first embodiment, and the conductive circuit and the via were similarly measured by a four-terminal method. The measured value was 8.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第６の実施例においては、第５の実施例と同じニッケルの粒子の表面に、厚さ１μm の錫の被膜を無電界めっき法にて形成した導電フィラー 900ｇと、第１の実施例と同じ薬品とを混合して導電性ペーストを作り、この導電性ペーストをスクリーン印刷法により第１の実施例と同様に導体回路とビアを形成し、同様にこの導体回路及びビアを四端子法により測定した。その測定値は、図４に示すように9.0 ×10-6Ω・cmであった。 In the sixth embodiment of the present invention, 900 g of a conductive filler in which a 1 μm-thick tin film is formed on the surface of the same nickel particles as in the fifth embodiment by an electroless plating method; A conductive paste is made by mixing the same chemicals as in the example, and the conductive paste is formed by screen printing in the same manner as in the first embodiment to form a conductive circuit and a via. Measured by the method. The measured value was 9.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第７の実施例においては、第１或いは第２の実施例と同じ銅の粒子の表面に、厚さ１μm のインジウムの被膜を無電界めっき法にて形成した導電フィラー 900ｇと、第１の実施例と同じ薬品とを混合して導電性ペーストを作り、この導電性ペーストで 150μm 径のビアを形成し、同様にこのビアを四端子法により測定した。その測定値は、図４に示すように5.0 ×10-6Ω・cmであった。 In the seventh embodiment of the present invention, 900 g of a conductive filler in which an indium film having a thickness of 1 μm is formed on the surface of the same copper particles as in the first or second embodiment by an electroless plating method, A conductive paste was prepared by mixing the same chemicals as in Example 1, and a via having a diameter of 150 μm was formed from this conductive paste. Similarly, this via was measured by the four-terminal method. The measured value was 5.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第８の実施例においては、第３或いは第４の実施例と同じ銀の粒子の表面に、厚さ１μm のインジウムの被膜を無電界めっき法にて形成した導電フィラー 900ｇと、第１の実施例と同じ薬品とを混合して導電性ペーストを作り、この導電性ペーストで 150μm 径のビアを形成し、同様にこのビアを四端子法により測定した。その測定値は、図４に示すように5.0 ×10-6Ω・cmであった。 In the eighth embodiment of the present invention, 900 g of a conductive filler in which a 1 μm-thick indium film is formed on the surface of the same silver particles as in the third or fourth embodiment by electroless plating, A conductive paste was prepared by mixing the same chemicals as in Example 1, and a via having a diameter of 150 μm was formed from this conductive paste. Similarly, this via was measured by the four-terminal method. The measured value was 5.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第９の実施例においては、第５或いは第６の実施例と同じニッケルの粒子の表面に、厚さ１μm のインジウムの被膜を無電界めっき法にて形成した導電フィラー 900ｇと、第１の実施例と同じ薬品とを混合して導電性ペーストを作り、この導電性ペーストでビアを形成し、同様にこのビアを四端子法により測定した。その測定値は、図４に示すように8.0 ×10-6Ω・cmであった。 In the ninth embodiment of the present invention, 900 g of a conductive filler in which a 1 μm-thick indium film is formed on the surface of the same nickel particles as in the fifth or sixth embodiment by electroless plating, A conductive paste was prepared by mixing the same chemicals as in Example 1, and vias were formed from the conductive paste. Similarly, the vias were measured by the four-terminal method. The measured value was 8.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第１０の実施例においては、径が約５μm の銅の粒子の表面に、厚さ１μm の錫の被膜を無電界めっき法にて形成した導電フィラー 450ｇと、径が約５μm の銀の粒子の表面に、厚さ１μm のインジウムの被膜を無電界めっき法にて形成した導電フィラー 450ｇと、ビスフェノールＡ50ｇと、ジアミノジフェニルメタン５ｇ及びエチレングリコールジグリシジルエーテル45ｇを混合して導電性ペーストを作り、この導電性ペーストをスクリーン印刷法によりガラスエポキシ基板の表面に印刷した後、210℃で 180秒間加熱し、線幅150μm 、厚さ10μm の導体回路を形成した。 In the tenth embodiment of the present invention, 450 g of a conductive filler in which a tin film having a thickness of 1 μm is formed on the surface of a copper particle having a diameter of about 5 μm by an electroless plating method, and silver having a diameter of about 5 μm. A conductive paste was prepared by mixing 450 g of conductive filler formed by electroless plating with a 1 μm thick indium film on the surface of particles, 50 g of bisphenol A, 5 g of diaminodiphenylmethane and 45 g of ethylene glycol diglycidyl ether. After this conductive paste was printed on the surface of the glass epoxy substrate by a screen printing method, it was heated at 210 ° C. for 180 seconds to form a conductor circuit having a line width of 150 μm and a thickness of 10 μm.
また、この導電性ペーストを 150μm 径のビアに埋め込み、210 ℃で 180秒間加熱した。 The conductive paste was embedded in a 150 μm diameter via and heated at 210 ° C. for 180 seconds.
この導体回路及びビアを四端子法により測定した値は、図４に示すように8.0 ×10-6Ω・cmであった。 The value of this conductor circuit and via measured by the four probe method was 8.0 × 10 −6 Ω · cm as shown in FIG.
本発明の第11の実施例においては、径が 0.1〜0.5 μm の銅の粒子600 ｇと、径が 0.1〜0.3 μm の錫の粒子300 ｇと、ビスフェノールＡ50ｇと、ジアミノジフェニルメタン５ｇ及びエチレングリコールジグリシジルエーテル45ｇを混合して導電性ペーストを作り、この導電性ペーストをスクリーン印刷法によりガラスエポキシ基板の表面に印刷した後、210℃で 180秒間加熱し、線幅 150μm 、厚さ10μm の導体回路を形成した。 In an eleventh embodiment of the present invention, 600 g of copper particles having a diameter of 0.1 to 0.5 μm, 300 g of tin particles having a diameter of 0.1 to 0.3 μm, 50 g of bisphenol A, 5 g of diaminodiphenylmethane, and ethylene glycol diester. A conductive paste is made by mixing 45 g of glycidyl ether, and this conductive paste is printed on the surface of the glass epoxy substrate by screen printing, and then heated at 210 ° C for 180 seconds to produce a conductor circuit with a line width of 150 µm and a thickness of 10 µm. Formed.
また、この導電性ペーストを 150μm 径のビアに埋め込み、210 ℃で 180秒間加熱した。この導体回路及びビアを四端子法により測定した値は、図４に示すように9.0 ×10-6Ω・cmであった。 The conductive paste was embedded in a 150 μm diameter via and heated at 210 ° C. for 180 seconds. The value of this conductor circuit and via measured by the four probe method was 9.0 × 10 −6 Ω · cm as shown in FIG.
以上の説明から明らかなように、本発明によれば極めて簡単な構成の導電材料及び導電性ペーストを用いてプリント配線板の絶縁基板上に、この絶縁基板の耐熱温度よりも高い融点を有する導体回路を低温で形成することができる。 As is apparent from the above description, according to the present invention, a conductor having a melting point higher than the heat resistance temperature of the insulating substrate is formed on the insulating substrate of the printed wiring board using the conductive material and conductive paste having a very simple structure. Circuits can be formed at low temperatures.
１ 第１の金属の粒子
２ 第２の金属の被膜
３ 金属間化合物の被膜
４ 第３の金属の粒子
５ 第４の金属の被膜
DESCRIPTION OF SYMBOLS 1
Claims (7)
前記基板にはんだを使用して電子部品を搭載可能であり、前記金属間化合物の融点が前記はんだの溶融温度よりも高いことを特徴とする回路基板の製造方法。 Supplying a conductive paste containing a plurality of particles made of a first metal and a plurality of particles made of a second metal having a melting point lower than the melting point of the first metal into a via hole of the substrate; A circuit board manufacturing method for forming a conductor in which a plurality of particles made of the first metal are dispersed in an intermetallic compound of the first metal and the second metal,
An electronic component can be mounted on the substrate using solder, and the melting point of the intermetallic compound is higher than the melting temperature of the solder.
前記第１の金属は、Ｃｕ、Ｎｉ、Ａｇの少なくとも１つを含み、
前記第２の金属は、前記第１の金属と前記金属間化合物を形成する金属を含むことを特徴とする回路基板の製造方法。 In the manufacturing method of the circuit board according to claim 1,
The first metal includes at least one of Cu, Ni, and Ag,
The method of manufacturing a circuit board, wherein the second metal includes a metal that forms the intermetallic compound with the first metal.
前記第１の金属は、Ｃｕであり、
前記第２の金属は、Ｓｎであることを特徴とする回路基板の製造方法。 In the manufacturing method of the circuit board of Claim 2,
The first metal is Cu;
The method of manufacturing a circuit board, wherein the second metal is Sn.
前記第１の金属は、Ａｇであり、
前記第２の金属は、Ｓｎであることを特徴とする回路基板の製造方法。 In the manufacturing method of the circuit board of Claim 2,
The first metal is Ag;
The method of manufacturing a circuit board, wherein the second metal is Sn.
前記第２の金属は、Ｉｎを含むことを特徴とする回路基板の製造方法。 In the manufacturing method of the circuit board of Claim 2,
The circuit board manufacturing method, wherein the second metal contains In.
前記導電性ペーストは、スクリーン印刷法により前記ビアホール内に供給されることを特徴とする回路基板の製造方法。 In the manufacturing method of a circuit board given in any 1 paragraph of Claims 1 thru / or 5,
The method of manufacturing a circuit board, wherein the conductive paste is supplied into the via hole by a screen printing method.
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| TW340132B (en) * | 1994-10-20 | 1998-09-11 | Ibm | Structure for use as an electrical interconnection means and process for preparing the same |
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