JP5239736B2 - 電子装置 - Google Patents
電子装置 Download PDFInfo
- Publication number
- JP5239736B2 JP5239736B2 JP2008271952A JP2008271952A JP5239736B2 JP 5239736 B2 JP5239736 B2 JP 5239736B2 JP 2008271952 A JP2008271952 A JP 2008271952A JP 2008271952 A JP2008271952 A JP 2008271952A JP 5239736 B2 JP5239736 B2 JP 5239736B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- power element
- heat
- electronic device
- conductive adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/19015—Structure including thin film passive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
第2の基板(20)の一面とは反対側の他面には、電子部品(40)および電子部品(40)よりも駆動時の発熱が大きい発熱素子(41)が、モールド樹脂(50)で封止された状態で搭載されており、第2の基板(20)の一面のうち発熱素子(41)と同じ位置には、放熱部材(90)が熱的に接続されており、発熱素子(41)からの熱を放熱部材(90)により放熱するようになっていることを特徴とする。
図1は、本発明の第1実施形態に係る電子装置100の概略断面構成を示す図である。この電子装置100は、たとえば自動車に搭載され、車両制御用のECUなどの電子装置として用いられる。
図3は、本発明の第2実施形態に係る電子装置100の製造方法を示す工程図であり、各工程におけるワークの断面構成を示している。ここでは、上記第1実施形態の製造方法との相違点を中心に述べることとする。
図4は、本発明の第3実施形態に係る電子装置の概略断面構成を示す図である。本実施形態では、上記第1実施形態との相違点を中心に述べることとする。
図5は、本発明の第4実施形態に係る電子装置の概略断面構成を示す図である。本実施形態では、上記第1実施形態との相違点を中心に述べることとする。
なお、電子装置としては、第1の基板と、第1の基板の一面に搭載されたパワー素子と、一面を第1の基板の一面およびパワー素子に対向させて配置された第2の基板とを備え、第2の基板の一面とパワー素子とを、導電性接着部材を介して直接接着して電気的に接続し、第1の基板、パワー素子、および第2の基板を、モールド樹脂により封止したものであればよく、第2の基板の他面には上記電子部品は無いものであってもよい。
20 第2の基板
30 パワー素子
40 電子部品
41 発熱素子
50 モールド樹脂
60 導電性接着部材
90 放熱部材
Claims (3)
- 第1の基板(10)と、
前記第1の基板(10)の一面に搭載されたパワー素子(30)と、
一面を前記第1の基板(10)の前記一面および前記パワー素子(30)に対向させて配置された第2の基板(20)とを備え、
前記第2の基板(20)の前記一面と前記パワー素子(30)とは、導電性を有する導電性接着部材(60)を介して直接接着されて電気的に接続されており、
前記第1の基板(10)、前記パワー素子(30)、および前記第2の基板(20)は、モールド樹脂(50)により封止されており、
前記第2の基板(20)の前記一面とは反対側の他面には、電子部品(40)および前記電子部品(40)よりも駆動時の発熱が大きい発熱素子(41)が、前記モールド樹脂(50)で封止された状態で搭載されており、
前記第2の基板(20)の前記一面のうち前記発熱素子(41)と同じ位置には、放熱部材(90)が熱的に接続されており、前記発熱素子(41)からの熱を前記放熱部材(90)により放熱するようになっていることを特徴とする電子装置。 - 前記導電性接着部材(60)は、はんだもしくは導電性接着剤であることを特徴とする請求項1に記載の電子装置。
- 前記第2の基板(20)の前記一面とは反対側の他面側にも、前記パワー素子(30)が前記導電性接着部材(60)を介して直接接着されて電気的に接続されるとともに、前記モールド樹脂(50)によって封止されており、
前記第2の基板(20)の前記一面側の前記パワー素子(30)と前記他面側の前記パワー素子(30)とは、同じ位置に設けられていることを特徴とする請求項1または2に記載の電子装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008271952A JP5239736B2 (ja) | 2008-10-22 | 2008-10-22 | 電子装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008271952A JP5239736B2 (ja) | 2008-10-22 | 2008-10-22 | 電子装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010103231A JP2010103231A (ja) | 2010-05-06 |
JP5239736B2 true JP5239736B2 (ja) | 2013-07-17 |
Family
ID=42293645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008271952A Expired - Fee Related JP5239736B2 (ja) | 2008-10-22 | 2008-10-22 | 電子装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5239736B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9093434B2 (en) | 2011-04-04 | 2015-07-28 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
WO2014054212A1 (ja) | 2012-10-01 | 2014-04-10 | 富士電機株式会社 | 半導体装置とその製造方法 |
WO2018138902A1 (ja) * | 2017-01-30 | 2018-08-02 | 三菱電機株式会社 | パワー半導体装置の製造方法およびパワー半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0514519Y2 (ja) * | 1988-08-30 | 1993-04-19 | ||
JP3448159B2 (ja) * | 1996-06-20 | 2003-09-16 | 株式会社東芝 | 電力用半導体装置 |
JP2004088022A (ja) * | 2002-08-29 | 2004-03-18 | Toshiba Corp | 大電力用半導体装置 |
JP4385324B2 (ja) * | 2004-06-24 | 2009-12-16 | 富士電機システムズ株式会社 | 半導体モジュールおよびその製造方法 |
JP5241177B2 (ja) * | 2007-09-05 | 2013-07-17 | 株式会社オクテック | 半導体装置及び半導体装置の製造方法 |
-
2008
- 2008-10-22 JP JP2008271952A patent/JP5239736B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2010103231A (ja) | 2010-05-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4438489B2 (ja) | 半導体装置 | |
JP4453498B2 (ja) | パワー半導体モジュールおよびその製造方法 | |
JP6065973B2 (ja) | 半導体モジュール | |
US20140029201A1 (en) | Power package module and manufacturing method thereof | |
US20060272150A1 (en) | Module and method for fabricating the same | |
JP4254527B2 (ja) | 半導体装置 | |
JP4385324B2 (ja) | 半導体モジュールおよびその製造方法 | |
JP2015009466A (ja) | 電子装置およびその電子装置の製造方法 | |
JP4967701B2 (ja) | 電力半導体装置 | |
JP2008141140A (ja) | 半導体装置 | |
CN113097173A (zh) | 半导体封装及其制造方法 | |
JP2015144216A (ja) | 半導体装置及びその製造方法 | |
JP5239736B2 (ja) | 電子装置 | |
JP2008198921A (ja) | モジュール部品及びその製造方法 | |
JP6354163B2 (ja) | 回路基板および電子装置 | |
JP7088224B2 (ja) | 半導体モジュールおよびこれに用いられる半導体装置 | |
JP6391430B2 (ja) | 電子制御装置およびその製造方法 | |
JP5699006B2 (ja) | 変速機制御装置及び電子回路装置 | |
JP6666048B2 (ja) | 回路基板装置 | |
JP5691794B2 (ja) | 電子制御装置 | |
JP6945513B2 (ja) | 電子制御装置 | |
WO2020189508A1 (ja) | 半導体モジュールおよびこれに用いられる半導体装置 | |
JP2005332918A (ja) | 電子装置 | |
JP2015018860A (ja) | 半導体パッケージの製造方法 | |
JP2015106649A (ja) | 電子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110214 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120104 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121211 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130201 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130305 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130318 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160412 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160412 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |