JP5239217B2 - Manufacturing method of semiconductor mounting substrate - Google Patents
Manufacturing method of semiconductor mounting substrate Download PDFInfo
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- JP5239217B2 JP5239217B2 JP2007150281A JP2007150281A JP5239217B2 JP 5239217 B2 JP5239217 B2 JP 5239217B2 JP 2007150281 A JP2007150281 A JP 2007150281A JP 2007150281 A JP2007150281 A JP 2007150281A JP 5239217 B2 JP5239217 B2 JP 5239217B2
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Description
本発明は、感光性レジストを用いて回路パターンを形成する半導体実装基板の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor mounting substrate in which a circuit pattern is formed using a photosensitive resist.
従来、アディティブ法による半導体実装基板の製造方法では、絶縁性基材の表面に導電層を有する基板材料として、キャリアフィルムと感光性レジストフィルムとカバーフィルムの３層で構成されるドライフィルムを用いて、先ず、キャリアフィルムを剥がしながら基板材料の導電層上にこれをラミネートする。次に、露光工程を経て、ネガティブ型レジストでは露光部分が硬化する。そして、カバーフィルムを剥離し、現像工程を経ることで硬化したレジストが残り、未硬化部分のレジストが除去される。このようにして、レジストにより所定のパターンを形成した後、レジスト間（レジストが除去された部分）に導電性金属層をめっきにより形成し、レジストを剥離し、レジストの剥離により現れた導電層をエッチング処理により除去することで、半導体実装基板を得ていた。 Conventionally, in a method for manufacturing a semiconductor mounting substrate by an additive method, a dry film composed of three layers of a carrier film, a photosensitive resist film and a cover film is used as a substrate material having a conductive layer on the surface of an insulating substrate. First, it is laminated on the conductive layer of the substrate material while peeling off the carrier film. Next, through the exposure process, the exposed portion of the negative resist is cured. And the resist which hardened | cured by peeling a cover film and passing through a image development process remains, and the resist of an unhardened part is removed. In this way, after a predetermined pattern is formed with a resist, a conductive metal layer is formed by plating between the resists (portions where the resist has been removed), and the resist is removed. The semiconductor mounting board was obtained by removing by an etching process.
しかし、現像後に未硬化レジストが除去された導電層面には、レジストの残滓が僅かに残るため、めっきにより形成された導電性金属層の密着性が低下する原因となっていた。このように密着性が低下すると、接合面積が小さいファインピッチの要求には対応できないという状況になっていた。 However, a slight residue of the resist remains on the surface of the conductive layer from which the uncured resist has been removed after development, which has caused a decrease in the adhesion of the conductive metal layer formed by plating. Thus, when adhesiveness fell, it was in the condition which cannot respond to the request | requirement of a fine pitch with a small joining area.
本発明は、このような従来技術の問題点に鑑みてなされたものであり、その目的とするところは、従来のアディティブ法の適用に当たり、レジストパターン間に形成される導電性金属層を安定且つ、高密着性が得られるようにした半導体実装基板の製造方法を提供することにある。 The present invention has been made in view of such problems of the prior art, and the object of the present invention is to provide a stable and conductive metal layer formed between resist patterns in the application of the conventional additive method. Another object of the present invention is to provide a method for manufacturing a semiconductor mounting substrate in which high adhesion can be obtained.
上記目的を達成するため、本発明による半導体基板の製造方法は、基板材料上に所定の回路パターンを形成する、セミアディティブ法による半導体実装基板の製造方法において、導電層の厚さが０．００１ｍｍの感光性レジストが塗布された前記基板材料にマスクを被せて露光し現像し、現像した後、露出した導電層を溶解するエッチング液により現像後に残存している導電層表面の不純物と共に導電層をおよそ０．０００５ｍｍ溶解し、導電層の上にめっきにより形成される導電性金属層との接着面積を増加させることを特徴とする。 In order to achieve the above object, a semiconductor substrate manufacturing method according to the present invention is a method for manufacturing a semiconductor mounting substrate by a semi-additive method in which a predetermined circuit pattern is formed on a substrate material, and the thickness of the conductive layer is 0.001 mm. The substrate material coated with the photosensitive resist is covered with a mask, exposed and developed, and developed, and then the conductive layer is formed together with impurities on the surface of the conductive layer remaining after development with an etching solution that dissolves the exposed conductive layer. Dissolving approximately 0.0005 mm increases the adhesion area with the conductive metal layer formed by plating on the conductive layer .
本発明によれば、セミアディティブ法により形成していた、導電性金属層の接着面積を増加させることが可能となり、半導体素子と半導体実装基板の十分な接合強度を提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to increase the adhesion area of the electroconductive metal layer formed by the semi-additive method, and can provide sufficient joining strength of a semiconductor element and a semiconductor mounting board | substrate.
以下、本発明の実施の形態を実施例に基づき説明する。
本発明による半導体実装基板の製造方法は、絶縁性基材の表面に導電層を有する長尺状の複合材料を用いて、この複合材料の両縁部に位置決め孔となる開口部を所定のピッチで形成する工程と、キャリアフィルムと感光性レジストフィルムとカバーフィルムで構成される帯状ドライフィルムを用いて、キャリアフィルムを剥がしながら複合材料にラミネートする工程と、ドライフィルムがラミネートされた複合材料を用いて、複合材料に開口されている位置決め孔を基準として所定のパターンを露光した後、現像してパターンを形成する工程と、露出した導電層を僅かにエッチングした後、レジストパターン間に硫酸銅水溶液による電解銅めっきの導電性金属層を形成する工程と、形成したレジストパターンを剥離する工程と、レジストパターンを剥離して現れた導電層を除去する工程を備えたことを特徴としている。
Hereinafter, embodiments of the present invention will be described based on examples.
The method for manufacturing a semiconductor mounting substrate according to the present invention uses a long composite material having a conductive layer on the surface of an insulating base material, and openings at both edges of the composite material are provided with positioning holes at a predetermined pitch. Using a belt-shaped dry film composed of a carrier film, a photosensitive resist film and a cover film, laminating the carrier film while laminating it on the composite material, and using a composite material laminated with the dry film Then, after exposing a predetermined pattern on the basis of the positioning hole opened in the composite material, developing the pattern and developing the pattern, and etching the exposed conductive layer slightly, the copper sulfate aqueous solution between the resist patterns Forming a conductive metal layer of electrolytic copper plating by the method, peeling the formed resist pattern, resist pattern It is characterized by comprising a step of removing the conductive layer which appeared by peeling off the down.
通常、レジストを紫外光により露光し、所定の回路パターンを硬化させた後現像を行うと、現像液中のスカム等の有機物が導電層表面に僅かながら付着する。また、紫外光により露光され硬化したレジストも、現像液やその後の水洗により僅かながら溶解するが、導電層近傍のレジストの溶解速度とそれよりも離れた部分のレジストの溶解速度よりも遅いため、薄いレジスト層が不導体層として導電層の上に残滓として残る。そこで、薄く導電層の上に残るこれら不導体層を、導電層と共に溶解除去する。 Usually, when the resist is exposed to ultraviolet light to develop a predetermined circuit pattern and then developed, organic substances such as scum in the developer are slightly adhered to the surface of the conductive layer. Also, the resist exposed and cured by ultraviolet light is slightly dissolved by the developer and subsequent water washing, but because the dissolution rate of the resist in the vicinity of the conductive layer and the dissolution rate of the resist in a part farther than that are slower, A thin resist layer remains as a non-conductive layer on the conductive layer as a residue. Therefore, these nonconductive layers that remain thinly on the conductive layer are dissolved and removed together with the conductive layer.
次に、本発明による半導体実装基板の製造方法の一実施例を説明する。
本発明の方法では、まず位置決め孔形成工程によって、幅２５０ｍｍ、絶縁層厚さ０．０３８ｍｍ、導体層０．００1ｍｍの複合材料の両縁部に孔間距離２４０ｍｍで一対の位置決め孔として直径０．５ｍｍの穿孔を材料送りピッチ３０ｍｍで行った。
Next, an embodiment of a method for manufacturing a semiconductor mounting substrate according to the present invention will be described.
In the method of the present invention, first, a positioning hole forming step forms a pair of positioning holes with a distance of 240 mm between the edges of a composite material having a width of 250 mm, an insulating layer thickness of 0.038 mm, and a conductor layer of 0.001 mm. 5 mm perforations were made at a material feed pitch of 30 mm.
次に、この材料の孔間に幅２２０ｍｍのドライフィルムレジスト（日立化成製RY-3315）を真空ラミネートした後、露光工程でラミネートされたレジスト上に、形成した位置決め孔を基準として位置合わせし、ガラスマスク上から紫外線を照射してガラスマスクに形成されたパターン形状を感光性フィルム上に写し、レジストに３０μｍピッチの回路パターンを形成した材料を準備した。 Next, after vacuum laminating a dry film resist (RY-3315 manufactured by Hitachi Chemical Co., Ltd.) having a width of 220 mm between the holes of this material, the resist is laminated in the exposure process, and aligned with the formed positioning hole as a reference, A material was prepared by irradiating ultraviolet rays from a glass mask to copy the pattern shape formed on the glass mask onto a photosensitive film and forming a circuit pattern with a 30 μm pitch on the resist.
次に、カバーフィルムを剥離して、１％炭酸ナトリウム溶液にて現像を行った後、硫酸過酸化水素水溶液により、現像によってレジストに形成された導電層をおよそ０．０００５ｍｍだけエッチングし、そして、硫酸銅水溶液による電気めっきによりレジストパターン間に導電性金属層を形成した。 Next, after peeling off the cover film and developing with 1% sodium carbonate solution, the conductive layer formed on the resist by development with an aqueous solution of sulfuric acid and hydrogen peroxide is etched by about 0.0005 mm, and A conductive metal layer was formed between the resist patterns by electroplating with an aqueous copper sulfate solution.
この後、２％水酸化ナトリウム溶液によりレジスト層を剥離し、電気銅めっき時のカソードとなった導体層を、硫酸過酸化水素系のエッチング液により除去し、所望の導体回路を形成した。 Thereafter, the resist layer was peeled off with a 2% sodium hydroxide solution, and the conductor layer that became the cathode at the time of electrolytic copper plating was removed with a sulfuric acid hydrogen peroxide etching solution to form a desired conductor circuit.
このようにして製造された実装基板を用いて接続端子の引き剥がし強度を測定したところ、４５０Ｎ／ｍから６５０Ｎ／ｍと密着力の向上が確認された。 When the peel strength of the connection terminal was measured using the mounting substrate thus manufactured, it was confirmed that the adhesion strength was improved from 450 N / m to 650 N / m .
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007150281A JP5239217B2 (en) | 2007-06-06 | 2007-06-06 | Manufacturing method of semiconductor mounting substrate |
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| JP2007150281A JP5239217B2 (en) | 2007-06-06 | 2007-06-06 | Manufacturing method of semiconductor mounting substrate |
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| JP2008305895A JP2008305895A (en) | 2008-12-18 |
| JP5239217B2 true JP5239217B2 (en) | 2013-07-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI312166B (en) * | 2001-09-28 | 2009-07-11 | Toppan Printing Co Ltd | Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board |
| JP2003298205A (en) * | 2002-02-04 | 2003-10-17 | Sumitomo Bakelite Co Ltd | Manufacturing method of printed wiring board |
| JP2005317901A (en) * | 2004-03-31 | 2005-11-10 | Alps Electric Co Ltd | Circuit component module and its manufacturing method |
| JP2005294643A (en) * | 2004-04-01 | 2005-10-20 | Sumitomo Metal Mining Package Materials Co Ltd | Method for manufacturing both-side wiring tape carrier and the same manufactured by the method |
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