JP5209196B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
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- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
最近、高性能MOSトランジスタを実現するため、チャネル領域にチャネルストレスを提供してキャリアの移動度(mobility)を向上させる方法が研究されている(特許文献1,2、非特許文献1,2)。
NMOSトランジスタ上に所定引張ストレスを有するライナ膜を形成し、ライナ膜上に第1層間絶縁膜としてO3-TEOS膜を形成した後、第1層間絶縁膜をFT-IR(Fourier Transform-Infrared Spectrometers)を用いて成分を分析した。引き続き、NMOSトランジスタ上に形成された第1層間絶縁膜をO3プラズマ処理した後、第1層間絶縁膜のFT-IRを用いて成分を分析した。その結果が図10に図示されている。
第1ないし第4NMOSトランジスタ上に所定引張ストレスを有するライナ膜を形成し、ライナ膜上に第1層間絶縁膜としてO3-TEOS膜を形成した後、第1層間絶縁膜のストレス大きさを各々測定した(As-Depo)。引き続き、第1ないし第4NMOSトランジスタ上に形成された第1層間絶縁膜を各々NH3プラズマ処理、O3プラズマ処理、N2プラズマ処理、O3プラズマ処理後、N2プラズマ処理して、第1層間絶縁膜のストレス大きさを各々測定した(Treatment)。その結果が、図11にともに図示されている。
シミュレーションプログラムにNMOSトランジスタ上に所定の引張ストレスを有するライナ膜を位置し、ライナ膜上に所定の引張ストレスを有した第1層間絶縁膜が位置するように設定した。その後、第1層間絶縁膜の厚さを変更させながら、それによる電子の移動度変化(mobility change)をシミュレーションした。その結果が、図12に図示されている。
10 半導体基板
20 素子分離領域
30 第1アクチブ領域
32 Pウェル
40 第2アクチブ領域
42 Nウェル
100 NMOSトランジスタ
110 第1ゲート絶縁膜
120 第1ゲート電極
130 スペーサ
146 チャネル領域
160 ソース/ドレイン領域
200 PMOSトランジスタ
210 第2ゲート絶縁膜
220 第2ゲート電極
230 スペーサ
246 チャネル領域
260 ソース/ドレイン領域
310 第1ライナ膜
312 第2ライナ膜
320 第1層間絶縁膜
400 プラズマ処理
Claims (8)
- 基板上にNMOSトランジスタを形成する工程と、
前記NMOSトランジスタ上に引張ストレスを有するライナ膜を形成する工程と、
前記ライナ膜上に第1層間絶縁膜を形成する工程と、
前記第1層間絶縁膜を脱水素化する工程とを含み、
前記NMOSトランジスタは、ゲート絶縁膜及びゲート電極を含み、前記ゲート絶縁膜、前記ゲート電極及び前記ライナ膜の総厚さをt1とし、前記ライナ膜及び前記第1層間絶縁膜の総厚さをt2とする時、t2/t1≧ 1.14であることを特徴とする半導体装置の製造方法。 - 前記第1層間絶縁膜を脱水素化する工程は、前記第1層間絶縁膜のストレスを変化させることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1層間絶縁膜を脱水素化する工程は、前記第1層間絶縁膜を脱水素化ガス雰囲気でプラズマ処理、UV処理及び/または熱処理する工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記脱水素化ガスは、N2、O2、O3、N2O、H2及び/またはD2と、これらの組合わせを含むことを特徴とする請求項3に記載の半導体装置の製造方法。
- 脱水素化の後、前記第1層間絶縁膜は、少なくとも200MPaの引張ストレスを有することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1層間絶縁膜は、O3-TEOS、NSG、PSG、BSG、BPSG、FSG、SOG及び/またはTOSZを含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1層間絶縁膜を形成した後、前記第1層間絶縁膜内に前記NMOSトランジスタと接続されるコンタクトを形成する工程をさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1層間絶縁膜を脱水素化した後、前記第1層間絶縁膜上に第2層間絶縁膜を形成する工程をさらに含み、前記第2層間絶縁膜は前記第1層間絶縁膜のストレスより小さなストレスを有することを特徴とする請求項1に記載の半導体装置の製造方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2005-0106096 | 2005-11-07 | ||
KR1020050106096A KR100678636B1 (ko) | 2005-11-07 | 2005-11-07 | 반도체 집적 회로 장치의 제조 방법 및 그에 의해 제조된반도체 집적 회로 장치 |
KR1020060073912A KR100834737B1 (ko) | 2006-08-04 | 2006-08-04 | 반도체 집적 회로 장치의 제조 방법 및 그에 의해 제조된반도체 집적 회로 장치 |
KR10-2006-0073912 | 2006-08-04 |
Publications (3)
Publication Number | Publication Date |
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JP2007134712A JP2007134712A (ja) | 2007-05-31 |
JP2007134712A5 JP2007134712A5 (ja) | 2009-12-24 |
JP5209196B2 true JP5209196B2 (ja) | 2013-06-12 |
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JP2006301719A Active JP5209196B2 (ja) | 2005-11-07 | 2006-11-07 | 半導体装置の製造方法 |
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US (2) | US7867867B2 (ja) |
JP (1) | JP5209196B2 (ja) |
TW (1) | TWI338335B (ja) |
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---|---|---|---|---|
JP2007324391A (ja) * | 2006-06-01 | 2007-12-13 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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