JP5199189B2 - 半導体装置、及び半導体装置の製造方法 - Google Patents
半導体装置、及び半導体装置の製造方法 Download PDFInfo
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- 229920002120 photoresistant polymer Polymers 0.000 description 9
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Description
以下、本発明を実施するための第1実施形態を図面に基づき説明する。
図1(A)は本発明の第1の実施形態における半導体装置10を外部端子側から見た平面図であり、図1(B)は図1(A)のB1−B1線断面図であり、図1(C)は図1(A)のC1部の部分断面拡大図である。
次に、半導体装置10の製造方法について説明する。
まず、図2に示すように、電子回路を有する基板12上全面に例えばポリイミド等の絶縁層14をスピンコート等により形成する。そして、図3(A)及び図3(B)に示すように、絶縁層14の表面に絶縁層側X軸目盛り部70及び絶縁層側Y軸目盛り部72を形成する。このとき絶縁層14の各電子回路の近傍となる部位に図示しない貫通穴を形成する。その後、貫通穴内に電子回路と電気的に接続される図示しない導電層を形成する。
以下、本発明に含まれない参考形態の半導体装置80を図面に基づき説明する。なお、第1の実施形態の半導体装置と同一部材については、同一符号を付して説明を省略する。
次に、半導体装置80の製造方法について説明する。
なお、第1の実施形態の半導体装置の製造方法と同一工程については、説明を省略する。
まず、図2に示すように、電子回路を有する基板12上全面に例えばポリイミド等の絶縁層14をスピンコート等により形成する。そして、図11に示すように、絶縁層14の表面に第1凹部82、第2凹部84を形成する。このとき絶縁層14の各電子回路の近傍となる部位に図示しない貫通穴を形成する。その後、貫通穴内に電子回路と電気的に接続される図示しない導電層を形成する。
12 基板
14 絶縁層
16 再配線
18 柱状電極
20 封止樹脂層
22 外部端子
34 台座部
40 線状部(第1分岐配線)
42 線状部(第1分岐配線)
44 配線側X軸目盛り部(第1分岐配線)
46 線状部(第2分岐配線)
48 線状部(第2分岐配線)
50 配線側Y軸目盛り部(第2分岐配線)
60 溝部(凹部)
62 溝部(凹部)
64 溝部(凹部)
66 溝部(凹部)
70 絶縁層側X軸目盛り部(第1目盛り部)
72 絶縁層側Y軸目盛り部(第2目盛り部)
80 半導体装置
82 第1凹部
84 第2凹部
90 再配線
92 台座部
96 第1切り欠き
98 第2切り欠き
102 マスク
106 マスク
Claims (4)
- 基板上に設けられ、複数の凹部が形成された絶縁層と、
前記絶縁層上に設けられた配線と、
前記配線から分岐し、平面視で前記複数の凹部とそれぞれ重なる複数の分岐配線と、
前記配線上に形成された導電部と、
前記導電部上に形成された外部端子と、
前記配線及び前記導電部を封止する封止樹脂層と、
を有し、
前記配線は、前記絶縁層の一方向へ延びる第1配線部と、前記第1配線部の一端部から前記絶縁層の一方向と直交する方向へ延びる第2配線部と、を備え、
前記分岐配線は、前記第1配線部から分岐して前記直交する方向へ延び出す第1分岐配線と、前記第2配線部から分岐して前記一方向へ延び出す第2分岐配線とからなり、
前記第1分岐配線は、前記一方向へ等間隔で複数本設けられて配線側第1目盛り部を形成し、
前記第2分岐配線は、前記直交方向へ等間隔で複数本設けられて配線側第2目盛り部を形成する半導体装置。 - 前記凹部は、前記配線及び前記分岐配線を形成するためのマスクにおいて前記分岐配線を形成するための分岐配線部を重ねて前記マスクの位置合わせを行なうためのアライメントマークである請求項1に記載の半導体装置。
- 前記複数の凹部は、前記一方向に等間隔で配列された絶縁層側第1目盛り部と、前記直交する方向に等間隔で配列された絶縁層側第2目盛り部と、で構成される請求項2に記載の半導体装置。
- 基板上に絶縁層を形成し、該絶縁層上に複数の凹部を形成する工程と、
前記複数の凹部をアライメントマークとして前記絶縁層上に配線を形成する工程と、
前記配線上に導電部を形成する工程と、
前記配線及び前記導電部の側面を覆うように、前記絶縁層上に封止樹脂層を形成する工程と、
前記導電部上に外部端子を形成する工程と、
を有し、
前記複数の凹部は、前記絶縁層の一方向に等間隔で配列された絶縁層側第1目盛り部と、前記一方向と直交する方向に等間隔で配列された絶縁層側第2目盛り部と、で構成され、
前記配線は、前記絶縁層の一方向へ延びる第1配線部と、前記第1配線部の一端部から前記絶縁層の一方向と直交する方向へ延びる第2配線部と、を備え、
前記第1配線部には、該第1配線部から分岐して前記直交する方向へ延び出す第1分岐配線が前記一方向へ等間隔で複数本設けられ、
前記第2配線部には、該前記第2配線部から分岐して前記一方向へ延び出す第2分岐配線が前記直交方向へ等間隔で複数本設けられ、
前記配線、前記第1分岐配線及び前記第2分岐配線を形成するためのマスクにおいて、平面視で前記第1分岐配線を形成するための第1分岐配線部と前記第1目盛り部とを重ね、前記第2分岐配線を形成するための第2分岐配線部と前記第2目盛り部とを重ねて前記マスクの位置合わせを行なう半導体装置の製造方法。
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US12/792,036 US8436482B2 (en) | 2009-06-29 | 2010-06-02 | Semiconductor device, and method of fabricating semiconductor device |
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