JP5153265B2 - Semiconductor device, electronic device and hybrid integrated circuit device using metal substrate - Google Patents

Semiconductor device, electronic device and hybrid integrated circuit device using metal substrate Download PDF

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JP5153265B2
JP5153265B2 JP2007226087A JP2007226087A JP5153265B2 JP 5153265 B2 JP5153265 B2 JP 5153265B2 JP 2007226087 A JP2007226087 A JP 2007226087A JP 2007226087 A JP2007226087 A JP 2007226087A JP 5153265 B2 JP5153265 B2 JP 5153265B2
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metal substrate
groove
semiconductor device
semiconductor element
semiconductor
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JP2009059909A (en
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雅彦 水谷
充 野口
佳史 池田
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for mounting a metal substrate on a curved surface even when the reverse surface shape of the metal substrate is flat. <P>SOLUTION: Grooves Ct and Cb are formed on the top and reverse of the metal substrate 1 respectively and a radius of a remaining portion is left, so that operations such as mounting an element can be performed while maintaining flatness of the whole. Excellent processability for bending the metal substrate through the grooves is obtained. The plurality of metal substrates are connected leaving the grooves, so that modules can be mounted along the curved surface. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、金属基板を用いた半導体装置に関するものである。 The present invention relates to a semiconductor device using a metal substrate.

近年、環境破壊、地球温暖化の予兆、そして新聞紙上でこの温暖化の原因について報道がされている。その原因は、数多く存在するが、電力消費の増大が一つある。この電気は、枯渇しつつある石油に依存するところが多く、その石油を燃焼させる事による炭酸ガスの大気圏放出が問題である。また自動車もガソリン車が殆どであり、原因の一つである。   In recent years, environmental destruction, signs of global warming, and the cause of this warming have been reported in newspapers. There are many reasons for this, but there is one increase in power consumption. This electricity often depends on oil that is being depleted, and the problem is the release of carbon dioxide into the atmosphere by burning that oil. Also, automobiles are mostly gasoline cars, which is one of the causes.

前者の電気は、当然世界中にある電子機器を動かすために必要である。洗濯機、エアコン、携帯機器等の電源となり、地球上の人間が文化的な生活を維持する上で必要であり、解決するに非常に難しいテーマである。   The former electricity is of course necessary to move electronic devices around the world. It becomes a power source for washing machines, air conditioners, portable devices, etc., and it is necessary for people on the planet to maintain their cultural life, and it is a very difficult theme to solve.

一方、自動車は、高機能になり、社内でＴＶ会議ができたり、カーナビで目的地までの誘導が可能になったり、またカーエアコンで涼しくしたり、ヘッドライトで明るく鮮明に照らしたりと、その機能は、益々高機能になり、それを消費者は、競って購入する。つまり昔と違い、車内で色々な機能を使ってドライブすることで、結局はエネルギーの消費を拡大している。   On the other hand, automobiles are becoming more sophisticated and can be used for in-house video conferences, guided to the destination by car navigation, cooled by car air conditioners, brightly and clearly illuminated by headlights, etc. Features become increasingly sophisticated, and consumers buy it competitively. In other words, unlike the past, driving with various functions in the car eventually increased energy consumption.

これらの機能を実現するに半導体装置、所謂ＩＣ、ＬＳＩと言われる半導体デバイスが採用され、それを例えばプリント基板等の実装基板に実装し、電子機器のセットに実装している。この事を考えると、半導体デバイスも消費電力削減が非常に重要に成ってきる。   In order to realize these functions, semiconductor devices, so-called ICs and semiconductor devices called LSIs, are employed, which are mounted on a mounting board such as a printed circuit board and mounted on a set of electronic devices. Considering this, it is very important for semiconductor devices to reduce power consumption.

しかしながら、この電子機器、特に半導体デバイスは、動作することで発熱し、温度が上昇し、その結果、駆動能力が低下する。そしてその駆動能力を上げようとすれば、益々エネルギーを消費していることになる。   However, this electronic device, particularly a semiconductor device, generates heat when it operates and the temperature rises, resulting in a decrease in driving capability. And if you try to increase its driving ability, you are consuming more and more energy.

つまり何らかの形で半導体デバイスの熱を放出させて、半導体デバイス自身が消費する電力を削減する必要がある。   In other words, it is necessary to reduce the power consumed by the semiconductor device itself by releasing the heat of the semiconductor device in some form.

この傾向が強いものは、例えばパワー駆動が可能なパワーＭＯＳデバイス、発光素子であるレーザー、ＥＬ、ＬＥＤ等は、放熱の工夫が必要になる。   For those having a strong tendency, for example, power MOS devices that can be driven by power, lasers such as light emitting elements, EL, LEDs, and the like need to devise heat dissipation.

そのため、最近では、洗濯機、冷蔵庫等で用いられるインバータモジュール、プラズマディスプレイに用いられる駆動モジュール、ＬＥＤを用いた発光素子等の放熱が必要なデバイスは、積極的に金属基板に実装し、放熱させていた。   Therefore, recently, devices that require heat dissipation, such as inverter modules used in washing machines and refrigerators, drive modules used in plasma displays, and light emitting elements using LEDs, are actively mounted on metal substrates to dissipate heat. It was.

例えば特開２００１−６８７４２号公報は、ＬＥＤで植物栽培をするもので、ＬＥＤの駆動能力低下を防止するために、Ａｌ基板に実装するものである。   For example, Japanese Patent Application Laid-Open No. 2001-68742 cultivates plants with LEDs, and is mounted on an Al substrate in order to prevent a reduction in LED driving capability.

この公報の図７には、ユニットとして金属基板モジュールを用意し、光を収束させるために、それぞれがバラバラに成っている複数の金属基板モジュールを並べ、夫々の角度を調整し、光を収束させようとする技術が開示されている。   In FIG. 7 of this publication, a metal substrate module is prepared as a unit, and in order to converge light, a plurality of metal substrate modules each arranged separately are arranged, the respective angles are adjusted, and the light is converged. A technique to be disclosed is disclosed.

一方、特許第３８９６０２９号公報は、最近の金属基板の構造および製造方法を説明するものである。これの金属基板は、短冊状に多数のユニットが形成され、ここのユニットを従来は、プレス、またはパンチングと言われる切断方法にて個々のユニット、つまり１つの金属基板に加工される。しかしプレスによる加工方法では、金属基板を押さえるためのマージンが切断領域の両サイドに必要なため、実際の実装エリアが狭くなってしまう問題があった。そのため、ダイシングに用いられるようなブレードでＶ溝を掘り、その溝を介して分離していた。
特開２００１−６８７４２号公報 特許第３８９６０２９号公報 On the other hand, Japanese Patent No. 3896029 describes a recent structure and manufacturing method of a metal substrate. A large number of strips are formed on the metal substrate, and these units are conventionally processed into individual units, that is, one metal substrate by a cutting method called pressing or punching. However, the processing method using a press has a problem that an actual mounting area becomes narrow because margins for pressing the metal substrate are required on both sides of the cutting region. Therefore, the V-groove is dug with a blade used for dicing and separated through the groove.
JP 2001-68742 A Japanese Patent No. 3896029

前述したように金属基板を用いた半導体装置、混成集積回路装置またモジュールは、金属基板は、あくまでもフラットであり、フラットな状態の基板に素子を実装し、必要によって封止していた。 As described above, in a semiconductor device, a hybrid integrated circuit device, or a module using a metal substrate, the metal substrate is flat, and elements are mounted on the flat substrate and sealed if necessary.

図１０Ａは、その一例であり、セット側に何か直方体の凸状体１があり、ここに２つの半導体装置２、３を実装するモジュールを示すものである。ここでは金属基板がフラットであり、どうしても金属基板を用いた半導体装置は、２つ用意され、平面４、５にそれぞれ実装し、電気的接続手段を施していた。   FIG. 10A is an example of this, and shows a module in which there are some cuboid convex bodies 1 on the set side and two semiconductor devices 2 and 3 are mounted thereon. Here, the metal substrate is flat, and two semiconductor devices using the metal substrate are inevitably prepared, and are mounted on the planes 4 and 5, respectively, and provided with electrical connection means.

一方、図１０Ｂは、Ｌ字状の壁で、複数の半導体装置２、３・・・を実装する前の概略図を示すものである。これも金属基板を用いた半導体装置、混成集積回路装置は、裏面にある金属基板はフラットであり、どうしても個別で実装することになる。   On the other hand, FIG. 10B shows a schematic diagram before mounting a plurality of semiconductor devices 2, 3... With an L-shaped wall. Also in this semiconductor device and hybrid integrated circuit device using a metal substrate, the metal substrate on the back surface is flat and must be mounted individually.

この様な凸状体、Ｌ字状の壁、湾曲した面（図４を参照）等の実装面は、セットの形で様々である。しかしながら金属基板を用いた半導体装置は、裏面がフラットであるため、どうしても隙間無く実装することが難しかった。また金属基板は、放熱性を特徴としているため、できる限り金属基板の裏面を当接させる必要がある。しかし例えば、図４の様な湾曲した実装面では、熱的な結合が難しく、改善が求められていた。   Such mounting surfaces such as convex bodies, L-shaped walls, and curved surfaces (see FIG. 4) vary in the form of a set. However, a semiconductor device using a metal substrate has a flat back surface, so it is difficult to mount without any gap. Moreover, since the metal substrate is characterized by heat dissipation, it is necessary to make the back surface of the metal substrate contact as much as possible. However, for example, the curved mounting surface as shown in FIG. 4 is difficult to be thermally coupled, and improvement has been demanded.

本発明の金属基板を用いた半導体装置は、少なくとも表面が絶縁処理された金属基板と、前記金属基板の表面に設けられた導電材料から成る複数の導電パターンと、前記導電パターンと電気的に接続され、前記金属基板に実装された半導体素子と、前記金属基板の表面および前記半導体素子を封止する封止手段とから成る金属基板を用いた半導体装置であり、前記金属基板の第１の側辺と平行に設けられ、前記第１の側辺と直交関係の一対の側辺に到る溝が設けられ、前記溝を介して前記金属基板は曲折され、前記溝を境界として、前記金属基板は複数の平坦な区画領域に区画され、前記区画領域毎に前記半導体素子が前記封止手段により封止されることを特徴とする。
A semiconductor device using a metal substrate according to the present invention includes a metal substrate having an insulating surface at least, a plurality of conductive patterns made of a conductive material provided on the surface of the metal substrate, and electrically connected to the conductive pattern. A semiconductor device using a metal substrate comprising a semiconductor element mounted on the metal substrate, a surface of the metal substrate and a sealing means for sealing the semiconductor element, and a first side of the metal substrate A groove is provided in parallel with the side and reaches a pair of sides orthogonal to the first side, the metal substrate is bent through the groove, and the metal substrate is formed with the groove as a boundary. Is partitioned into a plurality of flat partition regions, and the semiconductor element is sealed by the sealing means for each partition region .

図５に示すように、溝を形成することで、ある形状、例えば湾曲面に沿って曲げることができる。よって別々に何個も半導体装置を用意して接続することなく実装することができる。 As shown in FIG. 5, by forming the groove, it can be bent along a certain shape, for example, a curved surface. Therefore, it is possible to mount several semiconductor devices without preparing and connecting them.

以下、本発明の実施の形態を説明する前に、本発明の概要を述べる。
本発明は、図５に示すように、金属基板１０の少なくとも一方の面に直線状の溝Ｃを形成し、この溝Ｃに沿って折り曲げることで、金属基板１０を或る形状に沿って加工することができる。これは、例えば画用紙をきれいに加工する際、例えば３角柱、４角柱・・・、先が尖った三角錐、四角錐・・・、また図１１に示すような折り曲げでは、ナイフで浅く切り込みを入れるときれいに折れる。これを利用したものである。実際、ＡｌまたはＣｕを主材料とする金属基板を強制的に折り曲げようとすれば、どうしても折り曲げ部分に負荷が加わり、曲げた部分は湾曲になりやすい。しかも、基板は、厚みがある。 Hereinafter, before describing embodiments of the present invention, an outline of the present invention will be described.
In the present invention, as shown in FIG. 5, a straight groove C is formed on at least one surface of the metal substrate 10, and the metal substrate 10 is processed along a certain shape by bending along the groove C. can do. For example, when a drawing paper is processed neatly, for example, a triangular prism, a quadrangular prism, a triangular pyramid with a sharp point, a quadrangular pyramid, and the like, and when bending as shown in FIG. It breaks nicely. This is used. Actually, if a metal substrate mainly made of Al or Cu is to be bent forcibly, a load is inevitably applied to the bent portion, and the bent portion tends to be bent. Moreover, the substrate has a thickness.

例えば一般的にＡｌ基板として採用されているものは１．５ｍｍ、２ｍｍであり、必要によって０．５ｍｍ〜５ｍｍ程度のものも採用される。これを採用するとなると結構大変な作業となる。   For example, those generally employed as the Al substrate are 1.5 mm and 2 mm, and those having a thickness of about 0.5 mm to 5 mm are also employed if necessary. If this is adopted, it will be a very difficult task.

また別の表現をすれば、実質矩形の区画領域１１、１２、１３が横に並べられ、その境界で角度を持たせたもので、例えばカードや短冊を複数枚用意し、溝Ｃに相当する側辺を当接接着したようなもので、夫々の区画領域は、実質フラットである。図４は、図５において、Ｃ１の溝から３つ右の溝（ここでは図示されてない）をフルカットし、区画領域１１、１２、１３を折り曲げたものである。すれば、この３面体の金属基板１０自体は、その湾曲形状に沿って、区画領域１１、１２、１３のフラット性を維持しながら、溝の部分が折り曲げられる。   In other words, the substantially rectangular divided areas 11, 12, and 13 are arranged horizontally and have an angle at the boundary. For example, a plurality of cards and strips are prepared and correspond to the groove C. Each of the partition areas is substantially flat. FIG. 4 is obtained by fully cutting the right three grooves (not shown here) from the groove C1 in FIG. 5 and bending the partition regions 11, 12, and 13. FIG. In this case, in the trihedral metal substrate 10 itself, the groove portion is bent along the curved shape while maintaining the flatness of the partition regions 11, 12, and 13.

また溝の深さは、その加工、つまり折り曲げ角度、強度が考慮され、金属基板１０の厚みに対して、符号Ｒの部分が１０％〜５０％程度の厚みが残るように施されている。例えば金属基板の厚みが１．５ｍｍとし、裏表に溝Ｃｔ、Ｃｂを形成する場合、夫々の溝は、０．４〜０．６程度とし、表溝Ｃｔと裏溝Ｃｂの間の非切削部Ｒ（別の言い方をすれば残存部）は、０．２〜０．６ｍｍ程度残存させている。この厚みにすることで、３つの金属基板１１、１２、１３の一体物は、素子の実装等の作業中に於いて、全体のフラット性を維持しつつ作業できる。また溝を介して折り曲げる際、加工性が良い。
当然、溝の本数は、この限りではなく、本数が増加すればするほど、なだらかな多面体、つまり湾曲形状に近づくことになる。 The depth of the groove is determined so that the processing, that is, the bending angle and the strength are taken into consideration, and the portion of the symbol R with respect to the thickness of the metal substrate 10 remains about 10% to 50%. For example, when the thickness of the metal substrate is 1.5 mm and the grooves Ct and Cb are formed on the front and back surfaces, each groove is about 0.4 to 0.6, and the non-cut portion between the front groove Ct and the back groove Cb R (in other words, the remaining part) is left about 0.2 to 0.6 mm. With this thickness, the integrated body of the three metal substrates 11, 12, and 13 can be operated while maintaining the entire flatness during the operation of mounting the elements. In addition, workability is good when bending through the groove.
Of course, the number of grooves is not limited to this, and as the number of grooves increases, the number of grooves approaches a gentle polyhedron, that is, a curved shape.

これを説明するのが図１〜図４である。   This is illustrated in FIGS.

図１は、金属基板１０に溝Ｃ１、Ｃ２を５本ずつ形成し、夫々の区画領域で個別封止したものである。この場合は、封止した後で金属基板１０自体を折り曲げられるメリットを有する。   In FIG. 1, five grooves C1 and C2 are formed in a metal substrate 10 and sealed individually in each partition region. In this case, there is an advantage that the metal substrate 10 itself can be bent after sealing.

図２は、金属基板１０全体を一体モールドするもので、金属基板１０の溝Ｃｔ、Ｃｂを介して折り曲げ、素子の実装をし、その湾曲形状に沿った支持台において、一体封止するものである。   FIG. 2 shows an example in which the entire metal substrate 10 is integrally molded. The metal substrate 10 is bent through the grooves Ct and Cb of the metal substrate 10 to mount an element, and is integrally sealed on a support base along the curved shape. is there.

また図３は、平面図として見ても、断面図として見ても良い。平面的に見れば、金属基板１０は折り曲げてなる二つの区画領域がつい立の様に立っている。また断面と見たら、水平に延在された金属基板にもう一つの基板が垂直に立てられた形となっている。
更に図４は、例えばポールの如き円柱２０の面に沿って溝が沿って曲げられたものである。 3 may be viewed as a plan view or a cross-sectional view. When viewed in plan, the metal substrate 10 stands in a standing manner with two partitioned regions formed by bending. When viewed as a cross section, another substrate is vertically erected on a horizontally extending metal substrate.
Further, FIG. 4 shows a groove bent along the surface of a cylinder 20 such as a pole.

では図５を用いて具体的に説明していく。   Then, it demonstrates concretely using FIG.

まず金属基板は、Ｃｕ、ＡｌまたはＦｅを主材料としたもので、導電パターン２１の形成のため、少なくとも表面に絶縁被膜が施される。例えばＡｌは、陽極酸化により硬い緻密な膜２２を形成可能で、表裏に形成しても良い。そして更に表面に樹脂からなる絶縁性被膜２３が形成される。陽極酸化膜２２は、基板１０表面の傷を防止する目的がメインであるため、省略をしても良い。また熱抵抗を小さくするためにシリコン酸化膜、アルミナ等のフィラーが絶縁性被膜２３に混入されても良い。   First, the metal substrate is made of Cu, Al, or Fe as a main material, and at least a surface is provided with an insulating film in order to form the conductive pattern 21. For example, Al can form a hard and dense film 22 by anodic oxidation and may be formed on the front and back sides. Further, an insulating film 23 made of resin is formed on the surface. The main purpose of the anodic oxide film 22 is to prevent scratches on the surface of the substrate 10 and may be omitted. Further, a filler such as a silicon oxide film or alumina may be mixed into the insulating coating 23 in order to reduce the thermal resistance.

続いてこの絶縁性被膜２３の上には、Ｃｕを主材料とした導電パターン２１が形成される。これは上に固着される回路素子の種類、規模により色々なパターンとなるが、一般的には、半導体素子等が設けられるアイランド２４、パッド２５、受動素子用の電極２６、またこれらをつなぐ配線、更には外部との電気的接続に必要なリード端子等が設けられる。つづいて、前記アイランド２４に半導体素子２７が設けられる。半導体基板裏面がフローティングまたはアース接地等で絶縁性接着剤、導電性接着剤、半田固着または共晶結合が選択される。電気的接続は、金属細線、バンプ電極、ロウ材等が選択される。半導体素子がフェイスアップでは、金属細線と前記パッドが接続され、フェイスダウンでは、バンプやロウ材等で接続される。   Subsequently, a conductive pattern 21 made mainly of Cu is formed on the insulating film 23. This has various patterns depending on the type and scale of the circuit element to be fixed thereon. In general, the island 24, the pad 25, the passive element electrode 26 on which the semiconductor element or the like is provided, and the wiring connecting these elements Furthermore, lead terminals and the like necessary for electrical connection with the outside are provided. Subsequently, a semiconductor element 27 is provided on the island 24. Insulating adhesive, conductive adhesive, solder fixation, or eutectic bonding is selected when the back surface of the semiconductor substrate is floating or grounded. For the electrical connection, a fine metal wire, a bump electrode, a brazing material, or the like is selected. When the semiconductor element is face-up, the fine metal wire and the pad are connected, and when face-down, the semiconductor element is connected by a bump or a brazing material.

また熱効率を求めるインバータ回路を構成するパワーＢｉｐＴｒ、パワーＭＯＳＴｒは、チップ裏面とアイランドとの間にヒートシンクが配置される。   In addition, in the power BipTr and the power MOS Tr constituting the inverter circuit for obtaining thermal efficiency, a heat sink is arranged between the chip back surface and the island.

受動素子であるチップコンデンサ、チップ抵抗等は、半田を介して接続される。
更に発光素子としてＬＥＤの実装も可能である。これはダイオードであるのでチップ裏面のアノードまたはカソード電極がアイランドに電気的に接続され、表面のカソード電極またはアノード電極が金属細線にて接続される。ただしデバイスによっては、表面にアノード、カソード電極があるものもある。 Chip capacitors, chip resistors, and the like, which are passive elements, are connected via solder.
Further, an LED can be mounted as a light emitting element. Since this is a diode, the anode or cathode electrode on the back surface of the chip is electrically connected to the island, and the cathode electrode or anode electrode on the surface is connected by a thin metal wire. However, some devices have anode and cathode electrodes on the surface.

本発明は、半導体装置としたが、これは半導体素子が少なくともひとつ以上設けられて完成しているものである。例えば、ＬＥＤから成る発光モジュールは、駆動回路を載せなければ、半導体素子で完結する。よってこれは、半導体装置とした。   The present invention is a semiconductor device, which is completed by providing at least one semiconductor element. For example, a light emitting module composed of LEDs is completed with a semiconductor element unless a driving circuit is mounted. Therefore, this was a semiconductor device.

またインバータ回路でトランジスタ素子、コンデンサや抵抗も含めて完結するものは、半導体装置でもあり、また混成集積回路装置でもある。
続いて溝の構成について説明する。溝の形成方法により、区画領域間の電気的接続が決まる。 A complete inverter circuit including a transistor element, a capacitor, and a resistor is a semiconductor device or a hybrid integrated circuit device.
Next, the configuration of the groove will be described. The method of forming the groove determines the electrical connection between the partition regions.

前述したように溝は、非切削部Ｒ（別の言い方をすれば残存部）は、０．２〜０．６ｍｍ程度残存させることで、一連の区画領域を平面に維持して作業が可能である。そのため、図１３を参照し、二つのケースに分けて説明する。ここでは、溝の両側はフラットで図示しているが、実際はこの溝に沿って曲げられているものである。
Ａのケース
このＡのケースは、下面に接着剤が塗られた導電箔３１（ここでは例えばＣｕ箔）を貼り合わせる前に溝を形成し、その後にこの導電箔を貼り合わせ、パターニングする場合である。１は、両面に溝が、２は、上に溝が形成され、溝の形成が先であるため、溝の上の開口部に導電パターンが延在する。また３は、溝が裏面に形成されるので、そのまま曲折部にパターンが延在するものである。 As described above, the non-cutting portion R (in other words, the remaining portion) remains about 0.2 to 0.6 mm so that the groove can be operated while maintaining a series of partitioned regions on a plane. is there. Therefore, with reference to FIG. 13, it demonstrates by dividing into two cases. Here, both sides of the groove are illustrated as being flat, but actually, the groove is bent along the groove.
Case A This case A is a case where a groove is formed before the conductive foil 31 (for example, Cu foil in this case) having an adhesive coated on the lower surface is bonded, and then the conductive foil is bonded and patterned. is there. 1 is a groove on both sides, 2 is a groove formed on the top, and since the groove is formed first, the conductive pattern extends to the opening above the groove. In 3, since the groove is formed on the back surface, the pattern extends as it is in the bent portion.

例えばＣｕ材は、延性があり、若干の角度の折り曲げであれば、導電パターンを断線することなく、その曲げ部に沿って延在させることができる。また曲折部に熱を加えればよりスムーズにパターンを伸ばすことができる。
Ｂのケース
このＢのケースは、導電パターンをパターニングした後、溝を形成する場合である。また導電パターンをパターニングし、回路素子の実装、電気的接続をした後に溝を形成するものである。 For example, the Cu material is ductile and can be extended along the bent portion without breaking the conductive pattern if it is bent at a slight angle. Further, if heat is applied to the bent portion, the pattern can be extended more smoothly.
Case B This case B is a case where a groove is formed after the conductive pattern is patterned. In addition, the conductive pattern is patterned, and after the circuit elements are mounted and electrically connected, grooves are formed.

どちらにしても仮に曲折部に導電パターンが存在すれば、溝が形成されるためにこの導電パターンか切除される。よって別途接続手段を用意しないといけない。また溝の両側に設けられる導電パターンは、溝の切除面と実質セルフアライメントされた状態であると、溝を介して下に凸に折り曲げると、両側の導電パターンが接触する。これはその固定をロウ材と固定すれば、安定しているが、固定しないと接触が不安定であり、この場合は、パターン３２は、溝の形成位置から離間するようにパターニングする必要がある。   In either case, if there is a conductive pattern in the bent portion, the conductive pattern is cut out because a groove is formed. Therefore, a separate connection means must be prepared. Further, when the conductive patterns provided on both sides of the groove are substantially self-aligned with the cut surface of the groove, the conductive patterns on both sides come into contact with each other when bent downwardly through the groove. This is stable if the fixing is fixed to the brazing material, but if not fixed, the contact is unstable. In this case, the pattern 32 needs to be patterned so as to be separated from the groove forming position. .

４、５、６は、そのためのもので、導電パターンは溝から離間されて設けられている。４は、その離間した導電パターンに金属細線で接続されるものである。金属細線３３は、溝の上を延在するため、ある程度の曲折に対して電気的固定を維持しながら変形が可能である。   4, 5 and 6 are for that purpose, and the conductive pattern is provided apart from the groove. 4 is connected to the separated conductive pattern with a fine metal wire. Since the fine metal wire 33 extends over the groove, it can be deformed while maintaining electrical fixation against a certain degree of bending.

５、６は、フレキシブル性の樹脂基板３４に導電パターン３５が形成され、導電パターン３５が下に向くように位置し、金属基板側に位置する導電パターンと電気的に接続されるものである。樹脂基板は、ＴＡＢに採用される様な薄地で変形が容易なものが良い。例えばポリイミド、エポキシ樹脂が好ましい。また樹脂基板側のパターンは、Ｃｕを主材料とすれば、延性があり変形に対して応ずる。   Nos. 5 and 6 are those in which a conductive pattern 35 is formed on a flexible resin substrate 34, the conductive pattern 35 is positioned downward, and is electrically connected to the conductive pattern positioned on the metal substrate side. The resin substrate is preferably thin and easily deformed as used in TAB. For example, polyimide and epoxy resin are preferable. The pattern on the resin substrate side is ductile and responds to deformation if Cu is the main material.

７は、３の場合と同じになるので説明は省略する。   7 is the same as 3 and will not be described.

続いて図６に示すように、封止する。載置された回路素子２７の形状、この半導体装置がセットされる雰囲気によっては、封止手段を省略しても良い。
ここでは、区画領域の周囲を囲い、中が中空のケースで封止しても良いし、トランスファーモールド、インジェクション、ポッティング等での封止方法が考えられる。ここでは基板の表に封止樹脂が形成され、剥離が考慮されて貫通孔４０が形成され、アンカー効果を持たせても良い。また直線状の溝に沿って貫通されたスリットが形成されていれば、裏面にも封止が可能である
図７は、区画領域５０、５１、５２毎に封止された金属基板は、セットの曲面がトレースされた基板５３を用意し、それに金属基板５４を押圧させることで、変形が可能である。また全体が水平な状態でセット側に納入し、セット側で変形しても良い。 Subsequently, as shown in FIG. The sealing means may be omitted depending on the shape of the mounted circuit element 27 and the atmosphere in which the semiconductor device is set.
Here, the periphery of the partition region may be enclosed and sealed with a hollow case, or a sealing method such as transfer molding, injection, or potting may be considered. Here, a sealing resin may be formed on the surface of the substrate, and the through hole 40 may be formed in consideration of peeling, and may have an anchor effect. In addition, if the slit penetrating along the linear groove is formed, the back surface can be sealed. FIG. 7 shows that the metal substrate sealed for each of the partition regions 50, 51, 52 is set. The substrate 53 on which the curved surface is traced is prepared, and the metal substrate 54 is pressed against the substrate 53, whereby deformation is possible. Alternatively, the entire product may be delivered to the set side in a horizontal state and deformed on the set side.

図８は、３つの区画領域６０、６１、６２が１ユニットである金属基板６３を一体封止する例を説明するものである。下の金型６４がセット側の設置面に変形されていることで、半導体装置の裏面を変形できる。樹脂圧を考えると、夫々の区画領域に対応する金属基板は、全域がフラットであるため、下金型も同じ形状にする必要がある。
ここでも図６で説明した貫通孔またはスリットにより樹脂を侵入させ、アンカーを持たせたり、裏面に樹脂を延在させても良い。 FIG. 8 illustrates an example of integrally sealing a metal substrate 63 in which three partition regions 60, 61, and 62 are one unit. Since the lower mold 64 is deformed to the installation surface on the set side, the back surface of the semiconductor device can be deformed. Considering the resin pressure, the entire area of the metal substrate corresponding to each partition region is flat, so that the lower mold must also have the same shape.
Again, the resin may be intruded through the through holes or slits described with reference to FIG. 6 to provide an anchor, or the resin may extend on the back surface.

図９は、ＡまたはＢの方向に曲げられる事を説明している。
以上説明したように、カードの様な平面物を隙間無く並べ、当接した部分で曲げたようなもので、或る程度の曲げ加工が可能であり、図１０の如き設置面、湾曲面に設置できる。
よって金属基板を用いた半導体装置または混成集積回路装置は、より応用範囲が増加し、それにより内蔵される半導体素子の駆動能力を向上でき、それにより無駄な電力消費を抑制できる。 FIG. 9 illustrates the bending in the direction A or B.
As described above, flat objects such as cards are arranged without gaps and bent at the abutting portion, and can be bent to a certain extent. Can be installed.
Therefore, a semiconductor device or a hybrid integrated circuit device using a metal substrate has a wider application range, thereby improving the driving capability of a built-in semiconductor element, thereby suppressing wasteful power consumption.

図１１は、金属基板７０を実線の如き十字型にプレスして用意し、点線の部分で折り曲げれば、箱の如きモジュールが可能である。すれば右下の直方体７１の頭にスッポリと入るものが可能である。   In FIG. 11, a module like a box is possible by preparing a metal substrate 70 by pressing it into a cross shape like a solid line and bending it at the dotted line. By doing so, it is possible to insert a slippery head in the lower right rectangular parallelepiped 71.

図１２では、左右の飛び出している部分８０，８１に位置する６本の溝Ｃを用意すれば、或る程度の湾曲を持たせることができる。   In FIG. 12, if six grooves C located in the left and right protruding portions 80 and 81 are prepared, a certain degree of curvature can be provided.

本発明の第１の実施形態の半導体装置を示す図である。1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. 本発明の第２の実施形態を説明する図である。It is a figure explaining the 2nd Embodiment of this invention. 本発明の第３の実施形態を説明する図である。It is a figure explaining the 3rd Embodiment of this invention. 本発明の第４の実施形態を説明する図である。It is a figure explaining the 4th Embodiment of this invention. 本発明の溝の形成を説明する図である。It is a figure explaining formation of the groove | channel of this invention. 本発明の金属基板に封止する方法を説明する図である。It is a figure explaining the method to seal on the metal substrate of this invention. 本発明の金属基板に封止する方法を説明する図である。It is a figure explaining the method to seal on the metal substrate of this invention. 本発明の金属基板に封止する方法を説明する図である。It is a figure explaining the method to seal on the metal substrate of this invention. 本発明の金属基板に封止する方法を説明する図である。It is a figure explaining the method to seal on the metal substrate of this invention. 従来の実装形態を説明する図である。It is a figure explaining the conventional mounting form. 本発明の金属基板の折り曲げ方法を説明する図である。It is a figure explaining the bending method of the metal substrate of this invention. 本発明の金属基板の折り曲げ方法を説明する図である。It is a figure explaining the bending method of the metal substrate of this invention. 本発明の金属基板の折り曲げ方法を説明する図である。It is a figure explaining the bending method of the metal substrate of this invention.

符号の説明Explanation of symbols

１０：金属基板
Ｃ１、Ｃ２、Ｃ３：溝 10: Metal substrate C1, C2, C3: Groove

Claims (8)

少なくとも表面が絶縁処理された金属基板と、前記金属基板の表面に設けられた導電材料から成る複数の導電パターンと、前記導電パターンと電気的に接続され、前記金属基板に実装された半導体素子と、前記金属基板の表面および前記半導体素子を封止する封止手段とから成る金属基板を用いた半導体装置であり、
前記金属基板の第１の側辺と平行に設けられ、前記第１の側辺と直交関係の一対の側辺に到る溝が設けられ、前記溝を介して前記金属基板は曲折され、
前記溝を境界として、前記金属基板は複数の平坦な区画領域に区画され、
前記区画領域毎に前記半導体素子が前記封止手段により封止されることを特徴とする金属基板を用いた半導体装置。 A metal substrate having at least a surface insulated, a plurality of conductive patterns made of a conductive material provided on the surface of the metal substrate, and a semiconductor element electrically connected to the conductive pattern and mounted on the metal substrate; A semiconductor device using a metal substrate comprising a surface of the metal substrate and a sealing means for sealing the semiconductor element,
A groove is provided in parallel with the first side of the metal substrate and reaches a pair of sides orthogonal to the first side, and the metal substrate is bent through the groove,
With the groove as a boundary, the metal substrate is partitioned into a plurality of flat partition regions,
A semiconductor device using a metal substrate , wherein the semiconductor element is sealed by the sealing means for each partition region . 前記溝は、金属基板の少なくとも一方に設けられることを特徴とする請求項１に記載の金属基板を用いた半導体装置。 The groove, a semiconductor device using the metal substrate according to claim 1, characterized in that provided on at least one of the metal substrate. 前記導電パターンには、前記半導体素子としてパワー用のトランジスタまたは発光素子が実装されることを特徴とする請求項１または請求項２に記載の金属基板を用いた半導体装置。 3. The semiconductor device using a metal substrate according to claim 1 , wherein a power transistor or a light emitting element is mounted on the conductive pattern as the semiconductor element. 前記溝を境にして両側にケース材が配置されることを特徴とする請求項１から請求項３のいずれかに記載の金属基板を用いた半導体装置。 4. A semiconductor device using a metal substrate according to claim 1, wherein a case material is disposed on both sides of the groove. 前記溝を境にして両側に封止樹脂が設けられることを特徴とする請求項１から請求項３のいずれかに記載の金属基板を用いた半導体装置。 4. A semiconductor device using a metal substrate according to claim 1, wherein a sealing resin is provided on both sides of the groove. 前記金属基板は、ＡｌまたはＣｕを主材料とする導電材料からなることを特徴とする請求項１から請求項５のいずれかに記載の金属基板を用いた半導体装置。 The semiconductor device using the metal substrate according to any one of claims 1 to 5, wherein the metal substrate is made of a conductive material mainly composed of Al or Cu. 請求項１から請求項６の何れかに記載の金属基板を用いた半導体装置と、
平面以外の面を有する電子機器と電気的に接続される実装手段とを具備し
前記半導体装置の前記金属基板が前記実装手段の面の形状に沿って配置されたことを特徴とする電子機器。 A semiconductor device using the metal substrate according to any one of claims 1 to 6,
A mounting means electrically connected to an electronic device having a surface other than a plane.
Electronic apparatus, characterized in that said metal substrate of said semiconductor device is disposed along a shape of the surface of the mounting means. 少なくとも表面が絶縁処理された金属基板と、前記金属基板の表面に設けられた導電材料から成る複数の導電パターンと、前記導電パターンと電気的に接続され、前記金属基板に実装された半導体素子と、前記金属基板の表面および前記半導体素子を封止する封止手段とから成り、  A metal substrate having at least a surface insulated, a plurality of conductive patterns made of a conductive material provided on the surface of the metal substrate, and a semiconductor element electrically connected to the conductive pattern and mounted on the metal substrate; A sealing means for sealing the surface of the metal substrate and the semiconductor element,
前記金属基板の第１の側辺と平行に設けられ、前記第１の側辺と直交関係の一対の側辺に到る溝が設けられ、前記溝を介して前記金属基板は曲折され、  A groove is provided in parallel with the first side of the metal substrate and reaches a pair of sides orthogonal to the first side, and the metal substrate is bent through the groove,
前記溝を境界として、前記金属基板は複数の平坦な区画領域に区画され、  With the groove as a boundary, the metal substrate is partitioned into a plurality of flat partition regions,
前記区画領域毎に前記半導体素子が前記封止手段により封止されることを特徴とする混成集積回路装置。  The hybrid integrated circuit device, wherein the semiconductor element is sealed by the sealing means for each partition region.
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