JP5136799B2 - Manufacturing method of tape carrier for semiconductor device - Google Patents

Manufacturing method of tape carrier for semiconductor device Download PDF

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JP5136799B2
JP5136799B2 JP2009070717A JP2009070717A JP5136799B2 JP 5136799 B2 JP5136799 B2 JP 5136799B2 JP 2009070717 A JP2009070717 A JP 2009070717A JP 2009070717 A JP2009070717 A JP 2009070717A JP 5136799 B2 JP5136799 B2 JP 5136799B2
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plating
copper foil
copper
tape carrier
copper plating
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JP2010225795A (en
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宣明 宮本
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Description

本発明は、半導体素子を外部基板等に接続する際の接続媒体として用いられる半導体装置用テープキャリアの製造方法に関し、特に、ＢＧＡ型のパッケージに用いられる半導体装置用テープキャリアの製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device tape carrier used as a connection medium when connecting a semiconductor element to an external substrate or the like, and more particularly to a method for manufacturing a semiconductor device tape carrier used for a BGA type package. is there.

ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ：ボール グリッド アレイ）型のパッケージを用いた半導体装置は、多ピン化及び高密度実装化に適している。ＢＧＡ型パッケージを表す図４、および半導体装置用テープキャリア１０２の上面を表す図５ならびにその下面を表す図６に示されるように、特に、リール・トゥ・リールの工法で製造されるテープキャリア１０２は、形成される導体パターン１０３のファインピッチ化を達成できる。   A semiconductor device using a BGA (Ball Grid Array) type package is suitable for high pin count and high density mounting. As shown in FIG. 4 showing the BGA type package, FIG. 5 showing the upper surface of the tape carrier 102 for a semiconductor device, and FIG. 6 showing the lower surface thereof, in particular, the tape carrier 102 manufactured by the reel-to-reel method. The fine pitch of the formed conductor pattern 103 can be achieved.

具体的には、従来の半導体装置用テープキャリアの製造順序を示す図（断面図）である図７に示されるように、基板となるポリイミドフィルム１１０上に接着剤層１１１を設け（図７（ａ））、この接着剤層１１１付きポリイミドフィルム１１０を厚さ方向に貫通するビアホールを１１２設け（図７（ｂ））、ロール１１４ａ，１１４ｂにて銅箔１１３を貼り合わせる（図７（ｃ）（ｄ））。次に、銅箔１１３をフォトエッチング法により導体パターン１１５に形成する（図７（ｅ））。そして、導体パターン１１５にマスキングテープ１１６を貼り付け、ビアホール１１２に対して銅めっき１１７を充填し、ビアホールの深さを小にする（図７（ｆ））。その後、マスキングテープ１１６を剥がし（図７（ｇ））、ソルダーレジスト１１９を所定の形状に形成したのち、表面めっき処理層１１８を設ける（図７（ｈ））。この一連の工程により、半導体装置用テープキャリア１２０を製造する。   Specifically, as shown in FIG. 7 which is a diagram (cross-sectional view) showing a manufacturing order of a conventional tape carrier for a semiconductor device, an adhesive layer 111 is provided on a polyimide film 110 serving as a substrate (FIG. 7 ( a)), 112 is provided with a via hole penetrating through the polyimide film 110 with the adhesive layer 111 in the thickness direction (FIG. 7B), and the copper foil 113 is bonded with the rolls 114a and 114b (FIG. 7C). (D)). Next, a copper foil 113 is formed on the conductor pattern 115 by a photoetching method (FIG. 7E). Then, a masking tape 116 is attached to the conductor pattern 115, and the copper plating 117 is filled into the via hole 112 to reduce the depth of the via hole (FIG. 7 (f)). Thereafter, the masking tape 116 is peeled off (FIG. 7G), and the solder resist 119 is formed in a predetermined shape, and then the surface plating layer 118 is provided (FIG. 7H). Through this series of steps, the semiconductor device tape carrier 120 is manufactured.

まとめると、厚さ方向に貫通された開口（ビアホール）を有するポリイミドフィルム１１０上に導体パターン１１５が形成されたテープキャリア１２０の上面側において、図４〜図６に示されるように導体パターン１０３と半導体素子１０４の電極１０５とを金線等のボンディングワイヤ１０６で接続して封止樹脂１０７でモールドした後、テープキャリア１０２の下面側において、ビアホール１０８を介してはんだボール１０９を導体パターン１０３と接続して半導体装置１０１とする構成が挙げられる。この場合、薄型化と小型化、すなわち高密度化が図れる利点がある。   In summary, on the upper surface side of the tape carrier 120 in which the conductor pattern 115 is formed on the polyimide film 110 having an opening (via hole) penetrating in the thickness direction, as shown in FIGS. After the electrode 105 of the semiconductor element 104 is connected with a bonding wire 106 such as a gold wire and molded with a sealing resin 107, the solder ball 109 is connected to the conductor pattern 103 via the via hole 108 on the lower surface side of the tape carrier 102. Thus, a configuration of the semiconductor device 101 can be given. In this case, there is an advantage that thinning and downsizing, that is, high density can be achieved.

更なる高密度化を推進するためには、上面側の導体パターン１０３のファインピッチ化のみならず、外部接続端子となる下面側にはんだボール１０９を搭載するビアホール１０８のファインピッチ化も進める必要がある。
そのためにはビアホール１０８の径を小さくする必要があるが、ビアホール１０８の径を単に小さくしただけでは、はんだボール１０９と導体パターン１０３との接合に不具合が生じるおそれがある。 In order to promote further higher density, it is necessary not only to increase the fine pitch of the conductor pattern 103 on the upper surface side, but also to increase the fine pitch of the via holes 108 on which the solder balls 109 are mounted on the lower surface side serving as external connection terminals. is there.
For this purpose, it is necessary to reduce the diameter of the via hole 108, but simply reducing the diameter of the via hole 108 may cause a problem in joining the solder ball 109 and the conductor pattern 103.

そこで、はんだボール１０９が搭載されるビアホール１０８を金属めっき層によって埋め、ビアホール１０８の深さを小にすることにより、その不具合の解決が図られている（例えば、特許文献１、２参照）。なお、関連技術として、この金属めっき層を施す際に用いられる添加剤の添加量を、添加剤の成分毎に分けて変化させるものが知られている（例えば、特許文献３参照）。   Therefore, the problem is solved by filling the via hole 108 in which the solder ball 109 is mounted with a metal plating layer and reducing the depth of the via hole 108 (for example, see Patent Documents 1 and 2). In addition, as related art, what changes the addition amount of the additive used when applying this metal plating layer for every component of an additive is known (for example, refer patent document 3).

特許３２３８０７４号Japanese Patent No. 3238074 特許３５１０２１９号Japanese Patent No. 3510219 特開２００１−１５２３９８号公報JP 2001-152398 A

一方、上述のようにビアホールに対して金属めっきを行う場合、金属めっきを行う際の電流密度について考慮する必要がある。
例えば、前記テープキャリアのうちの一つであるＴＡＢテープキャリア等で一般的に行なわれている硫酸銅めっき液系による光沢電気銅めっきの場合、めっき液製造メーカは銅めっき時の電流密度を１〜５Ａ／ｄｍ２程度とするよう推奨している。
さらに、リール・トゥ・リールで製造するというＴＡＢテープの工法上、電極間距離を近接できないなど銅めっき装置の構造にも制約があること、不均一な形状の導体パターンによるめっき厚分布への影響、細い導体パターンにより許容電流が小さくなることなどを考慮すると、結果的にめっき時の電流密度を１〜５Ａ／ｄｍ２から上昇させることは難しい。 On the other hand, when metal plating is performed on the via hole as described above, it is necessary to consider the current density when performing metal plating.
For example, in the case of bright electrolytic copper plating by a copper sulfate plating solution system generally performed on a TAB tape carrier which is one of the tape carriers, the plating solution manufacturer sets the current density at the time of copper plating to 1 It is recommended to be about ˜5 A / dm 2 .
Furthermore, because of the TAB tape manufacturing method, which is manufactured reel-to-reel, there are restrictions on the structure of the copper plating equipment, such as the distance between the electrodes cannot be close, and the influence on the plating thickness distribution due to the non-uniform conductor pattern Considering that the allowable current is reduced due to the thin conductor pattern, it is difficult to increase the current density during plating from 1 to 5 A / dm 2 as a result.

このように電流密度を高くできない場合、リール・トゥ・リール工法では、搬送速度を低くして時間をかけてめっきを行うか、搬送速度を高く維持しつつもめっき槽を長くしてめっきを行う必要がある。後者の場合は設備費用が膨大になるためあまり現実的ではなく、前者が選択されるケースが多い。なお、深さ５０μｍの開口を、電流密度５Ａ／ｄｍ２にて銅めっきで埋め込む場合には、およそ４５分程度を要す計算となる。 When the current density cannot be increased in this way, in the reel-to-reel method, plating is performed over time by lowering the conveying speed, or plating is performed by extending the plating tank while maintaining the conveying speed high. There is a need. In the latter case, the equipment cost becomes enormous, so it is not so realistic, and the former is often selected. In the case where an opening having a depth of 50 μm is embedded by copper plating at a current density of 5 A / dm 2 , the calculation takes about 45 minutes.

また、上述のように時間をかけて銅めっきを行う場合、通常、ビアホール内の前記銅めっきと導体パターンとは製造方法において異なり、ひいては物性が異なるため、前記銅めっきと導体パターンとの接合について考慮する必要がある。特に、ＴＡＢテープキャリアで使用する導体パターンの形成用銅箔が電解銅箔であるとき、この接合について考慮する必要がある。   In addition, when copper plating is performed over time as described above, the copper plating and the conductor pattern in the via hole are usually different in the manufacturing method, and consequently have different physical properties. It is necessary to consider. In particular, when the copper foil for forming a conductor pattern used in the TAB tape carrier is an electrolytic copper foil, it is necessary to consider this bonding.

例えば、電解銅箔製造メーカが銅箔を作製する場合、ドラムめっき工法上、対向する電極を近接させることが可能であり、リール・トゥ・リール工法におけるめっき時の電流密度１〜５Ａ／ｄｍ２に比してドラムめっき工法では１５〜６０Ａ／ｄｍ２程度の高電流密度での稼動を達成している。例えば、厚さ５０μｍの電解銅箔を、電流密度６０Ａ／ｄｍ２にて形成する場合には、およそ４分程度を要す計算となる。 For example, when an electrolytic copper foil manufacturer manufactures a copper foil, the opposing electrodes can be brought close to each other in the drum plating method, and the current density during plating in the reel-to-reel method is 1 to 5 A / dm 2. In contrast, the drum plating method achieves operation at a high current density of about 15 to 60 A / dm 2 . For example, when an electrolytic copper foil having a thickness of 50 μm is formed at a current density of 60 A / dm 2 , the calculation takes about 4 minutes.

このため、ＴＡＢテープ製造工程において使用される銅箔と、ＴＡＢテープ製造工程において施される銅めっきとではめっき電流密度が異なることになり、金属としては同じ銅を用いていながらも、結晶配向等の物性が異なった状態となっている。   Therefore, the plating current density is different between the copper foil used in the TAB tape manufacturing process and the copper plating applied in the TAB tape manufacturing process, and while using the same copper as the metal, crystal orientation, etc. The physical properties are different.

このように銅箔と銅めっきとで結晶配向等の物性が異なる半導体装置においては、折り曲げ等の機械的なストレスや過度な環境負荷（温度、湿度等）がかかった場合を想定して、銅箔と銅めっきとの間の接合を強化することが望まれる。   As described above, in semiconductor devices having different physical properties such as crystal orientation between copper foil and copper plating, it is assumed that mechanical stress such as bending and excessive environmental load (temperature, humidity, etc.) are applied. It is desirable to strengthen the bond between the foil and the copper plating.

本発明の目的は、従来よりも高い電流密度での開口ヘの銅めっき充填を可能とすることにより、テープキャリアの生産性を向上させ、接続信頼性を高める半導体装置用テープキャリアの製造方法を提供することである。   An object of the present invention is to provide a method for manufacturing a tape carrier for a semiconductor device, which improves the productivity of the tape carrier and improves the connection reliability by enabling the filling of the opening with copper plating at a higher current density than before. Is to provide.

本発明の第一の態様は、絶縁フィルムを厚さ方向に貫通する開口を設ける工程と、前記絶縁フィルムの上面に電解銅箔を貼り合わせることにより、前記絶縁フィルムの下面に前記開口越しにて前記電解銅箔を露出させる工程と、前記電解銅箔の上面にマスキングを施した後に、電解めっき方式により前記電解銅箔の下面における前記開口越しに露出した部分に対して銅めっきを行うことにより、前記開口の深さを小とするめっき充填工程と、前記めっき充填工程の後に、前記マスキングが除去された電解銅箔を上面側からフォトエッチングすることにより、導体パターンを形成する工程と、前記導体パターンに表面めっき処理層を形成する工程と、を有し、前記めっき充填工程をリール・トゥ・リール方式で行い、前記リール・トゥ・リール方式にて使用する銅めっき槽における銅めっき液の噴流圧力を０．１ＭＰａ以上とし、前記めっき充填工程における電流密度を１５〜６０Ａ／ｄｍ 2 にすることにより前記めっき充填工程における電流密度と前記電解銅箔を形成する際の電流密度との差を小さくするように前記銅めっきを行うことを特徴とする。 The first aspect of the present invention includes a step of providing an opening penetrating the insulating film in the thickness direction, and bonding an electrolytic copper foil to the upper surface of the insulating film, thereby allowing the lower surface of the insulating film to pass through the opening. a step of exposing the electrolytic copper foil, after performing masking on the upper surface of the electrodeposited copper foil, by performing copper plating to the electroless portion exposed in the opening over the lower surface of the copper foil through electroplating A plating filling step for reducing the depth of the opening, and a step of forming a conductive pattern by photoetching the electrolytic copper foil from which the masking has been removed from the upper surface side after the plating filling step, and possess a step of forming a surface plating layer on the conductive pattern, and performs the plated filling step in reel-to-reel method, the reel-to-reel The jet pressure of the copper plating solution as above 0.1MPa in the copper plating bath to be used in the formula, the current density in the plating filling step electrolysis by a current density in the plating filling step 15~60A / dm 2 The copper plating is performed so as to reduce the difference from the current density when forming the copper foil .

本発明の第二の態様は、第一の態様に記載の発明において、前記めっき充填工程時に使用する銅めっき液は硫酸銅系の電解銅めっき液であり、添加剤成分として界面活性剤および／または光沢剤を含むことを特徴とする。 According to a second aspect of the present invention, in the invention described in the first aspect, the copper plating solution used in the plating filling step is a copper sulfate-based electrolytic copper plating solution, and a surfactant and / or an additive component Or it contains a brightener.

本発明の第三の態様は、第一または第二の態様に記載の発明において、前記銅めっき槽を１槽とし、前記めっき充填工程の前処理として、前記電解銅箔の下面における前記開口越しに露出した部分の防錆皮膜を化学研摩液により除去することを特徴とする。 A third aspect of the present invention is the invention according to the first or second aspect, wherein then copper plating tank 1 tank, a pre-treatment before Symbol plating filling step, the under surface of the electrodeposited copper foil opening It is characterized in that the portion of the rust preventive film exposed over the surface is removed with a chemical polishing liquid.

本発明によれば、従来よりも高い電流密度での開口ヘの銅めっき充填を可能とすることにより、テープキャリアの生産性を向上させ、接続信頼性を高める半導体装置用テープキャリアの製造方法を提供することができる。   According to the present invention, there is provided a method for manufacturing a tape carrier for a semiconductor device that improves the productivity of the tape carrier and increases the connection reliability by enabling the copper plating filling of the opening at a higher current density than before. Can be provided.

本発明の一実施形態における半導体装置用テープキャリアの製造順序を示す断面図である。It is sectional drawing which shows the manufacture order of the tape carrier for semiconductor devices in one Embodiment of this invention. 本発明の一実施形態におけるめっき充填工程に用いられる銅めっき装置の概略平面図である。It is a schematic plan view of the copper plating apparatus used for the plating filling process in one Embodiment of this invention. 本実施例及び比較例における評価結果を示す図である。It is a figure which shows the evaluation result in a present Example and a comparative example. ＢＧＡ型パッケージを示す断面図である。It is sectional drawing which shows a BGA type package. テープキャリアの１単位分を上面側から見た場合の説明図である。It is explanatory drawing at the time of seeing 1 unit of tape carriers from the upper surface side. テープキャリアの１単位分を下面側から見た場合の説明図である。It is explanatory drawing at the time of seeing one unit of tape carriers from the lower surface side. 従来の半導体装置用テープキャリアの製造順序を示す断面図である。It is sectional drawing which shows the manufacture order of the conventional tape carrier for semiconductor devices.

本発明者らは、従来よりも高い電流密度での開口ヘの銅めっき充填を可能とする半導体装置用テープキャリアの製造方法について種々検討した。
その結果、発明者らは、開口ヘの銅めっき充填を行った後において、導体パターンを形成することによって、従来よりも高い電流密度での開口ヘの銅めっき充填を行うことができることを見出した。 The inventors of the present invention have studied various methods for manufacturing a semiconductor device tape carrier that can fill the opening with copper plating at a higher current density than before.
As a result, the inventors have found that after the copper plating is filled into the opening, the copper pattern can be filled into the opening at a higher current density than before by forming a conductor pattern. .

以下に、本発明の一実施形態に係る半導体装置用テープキャリアの製造方法について説明する。   Below, the manufacturing method of the tape carrier for semiconductor devices which concerns on one Embodiment of this invention is demonstrated.

図１は、本発明の一実施形態における半導体装置用テープキャリアの製造順序を示す断面図である。
本発明の一実施形態に係る半導体装置用テープキャリアの製造においては、まず、絶縁フィルム２１上に接着剤層２２を設ける（図１（ａ））。
前記絶縁フィルム２１は、絶縁性を有するものであればよく、例えばポリイミドフィルムが挙げられる。その外形は、基板として使用できるものならばどのような形状でもよく、例えば長尺の矩形形状が挙げられる。
前記接着剤層２２は、後述する銅箔２４と前記絶縁フィルム２１との間に位置し、前記接着剤層２２を介して銅箔２４と前記絶縁フィルム２１を接着できるものであればよく、例えばエポキシ樹脂系接着剤層が挙げられる。 FIG. 1 is a cross-sectional view showing the manufacturing sequence of a semiconductor device tape carrier according to an embodiment of the present invention.
In the manufacture of the tape carrier for a semiconductor device according to one embodiment of the present invention, first, the adhesive layer 22 is provided on the insulating film 21 (FIG. 1A).
The insulating film 21 only needs to have insulating properties, and examples thereof include a polyimide film. The outer shape may be any shape as long as it can be used as a substrate, for example, a long rectangular shape.
The adhesive layer 22 may be located between the copper foil 24 and the insulating film 21, which will be described later, as long as it can adhere the copper foil 24 and the insulating film 21 via the adhesive layer 22. An epoxy resin adhesive layer is mentioned.

次に、この接着剤層２２付きポリイミドフィルム２１に、厚さ方向に貫通するビアホール２３（以降、開口２３ともいう）を、金型パンチにより設ける（図１（ｂ））。   Next, via holes 23 (hereinafter also referred to as openings 23) penetrating in the thickness direction are provided in the polyimide film 21 with the adhesive layer 22 by a mold punch (FIG. 1B).

その後、前記絶縁フィルム２１の上面側に前記銅箔２４を貼り合わせる（図１（ｃ）（ｄ））。この貼り合わせは、前記接着剤層２２を介して行われ、ロール２５ａ，２５ｂを用いたラミネート法が用いられる。
このように、前記絶縁フィルム２１の上面に銅箔２４を貼り合わせることにより、前記絶縁フィルム２１の下面に前記開口２３越しにて前記銅箔２４を露出させる。
上述のように設けられた前記開口２３は、前記絶縁フィルム２１の上面側を銅箔２４で塞がれた形状のはんだボール搭載用ビアホールとなる。
なお、前記銅箔２４は電解銅箔であることが好ましい。前記銅箔２４を形成する際の電流密度と、後述する銅充填めっき２７（以降、銅めっきともいう）を形成する際の電流密度との差を小さくすることにより、結晶配向等の物性に相違が生ずるのを抑制でき、銅箔２４と銅めっき２７との間の接合を強化することができるためである。 Thereafter, the copper foil 24 is bonded to the upper surface side of the insulating film 21 (FIGS. 1C and 1D). This bonding is performed through the adhesive layer 22, and a laminating method using rolls 25a and 25b is used.
Thus, the copper foil 24 is exposed to the lower surface of the insulating film 21 through the opening 23 by bonding the copper foil 24 to the upper surface of the insulating film 21.
The opening 23 provided as described above becomes a solder ball mounting via hole having a shape in which the upper surface side of the insulating film 21 is closed with the copper foil 24.
The copper foil 24 is preferably an electrolytic copper foil. By reducing the difference between the current density when forming the copper foil 24 and the current density when forming copper-filled plating 27 (hereinafter also referred to as copper plating) to be described later, physical properties such as crystal orientation are different. This is because it is possible to suppress the occurrence of the occurrence of the problem and to strengthen the bonding between the copper foil 24 and the copper plating 27.

この後、リール・トゥ・リール方式の銅めっき装置において、前記銅箔２４の上面に微粘着のテープ２６でマスキングを施した後に、前記銅箔２４の下面における前記開口２３越しに露出した部分に対して銅めっき２７を行い、前記開口２３を充填し、前記開口２３の深さを小とする（図１（ｅ））（以降、この工程をめっき充填工程ともいう）。なお、本実施形態では銅めっきを行っているが、他の適切な金属においても代替可能である。   Thereafter, in a reel-to-reel type copper plating apparatus, the upper surface of the copper foil 24 is masked with a slightly adhesive tape 26 and then exposed to the portion exposed through the opening 23 on the lower surface of the copper foil 24. On the other hand, copper plating 27 is performed to fill the opening 23 and reduce the depth of the opening 23 (FIG. 1E) (hereinafter, this process is also referred to as a plating filling process). In addition, although copper plating is performed in the present embodiment, other appropriate metals can be substituted.

従来では通常、めっき充填工程前に、導体パターンの形成が行われている。それに対して本実施形態では、前記めっき充填工程後に、マスキングテープ２６を剥がし（図１（ｆ））、フォトエッチング法により導体パターン２８を形成している（図１（ｇ））。
本実施形態のように導体パターン２８の形成前に銅めっき２７を施す場合と、図７に示される従来技術のように導体パターン１１５の形成後に銅めっき１１７を施す場合とでは、銅めっき時の銅箔２４の断面積が異なる。上述の通り、銅箔２４の下面における前記開口２３越しに露出した部分に対して銅めっき２７が施されるが、導体パターン２８形成前に銅めっきを行う場合の方が、エッチングを未だ行っていない分、銅めっき２７が施される銅箔２４の断面積が大きい。銅箔２４の断面積が大きいことにより、めっき充填工程における許容電流が高くなり、結果的に高い電流密度でのめっきに有利な条件となる。 Conventionally, the conductor pattern is usually formed before the plating filling step. On the other hand, in this embodiment, after the plating filling step, the masking tape 26 is peeled off (FIG. 1 (f)), and the conductor pattern 28 is formed by a photoetching method (FIG. 1 (g)).
When the copper plating 27 is applied before the formation of the conductor pattern 28 as in this embodiment, and when the copper plating 117 is applied after the formation of the conductor pattern 115 as in the prior art shown in FIG. The cross-sectional area of the copper foil 24 is different. As described above, the copper plating 27 is applied to the exposed portion of the lower surface of the copper foil 24 through the opening 23. However, the etching is still performed when the copper plating is performed before the conductor pattern 28 is formed. Therefore, the cross-sectional area of the copper foil 24 to which the copper plating 27 is applied is large. Since the cross-sectional area of the copper foil 24 is large, the allowable current in the plating filling process is high, and as a result, it is a favorable condition for plating at a high current density.

また、前記めっき充填工程は電解めっき方式で行われ、その際の電流密度は１５〜６０Ａ／ｄｍ２とすることが好ましい。上述の通り、本実施形態では従来よりも高い電流密度での開口２３ヘの銅めっき２７の充填が可能となるため、電解めっき方式を用いる場合、めっき充填工程にかける時間を短縮することができ、テープキャリアの生産性を向上させることができるためである。また、電解銅箔作成時の電流密度と近い電流密度を選択できるため、電解銅箔と同等の物性（例えば結晶配向等）とすることができ、銅箔とめっきとの界面の接合信頼性が向上する。 Further, the plating filling process is carried out in electroplating, the current density at that time is preferably set to 15~60A / dm 2. As described above, in this embodiment, the copper plating 27 can be filled into the opening 23 at a higher current density than in the prior art. Therefore, when the electrolytic plating method is used, the time required for the plating filling process can be shortened. This is because the productivity of the tape carrier can be improved. Moreover, since the current density close to the current density at the time of electrolytic copper foil creation can be selected, the physical properties equivalent to the electrolytic copper foil (for example, crystal orientation) can be obtained, and the bonding reliability at the interface between the copper foil and the plating is high. improves.

また、前記めっき充填工程時に使用する銅めっき液は硫酸銅系の電解銅めっき液であることが好ましい。   Moreover, it is preferable that the copper plating solution used at the time of the said plating filling process is a copper sulfate type electrolytic copper plating solution.

さらに、銅めっき液への添加剤成分として界面活性剤および／または光沢剤を含んでいるのが好ましい。前記界面活性剤としては、例えばＰＥＧ（ポリエチレングリコール）やＰＰＧ（ポリプロピレングリコール）が挙げられる。また、前記光沢剤としては、例えばＳＰＳ（ビス（３−スルホプロピル）ジスルファイド２ナトリウム）が挙げられる。   Furthermore, it is preferable to contain a surfactant and / or a brightener as an additive component to the copper plating solution. Examples of the surfactant include PEG (polyethylene glycol) and PPG (polypropylene glycol). Examples of the brightener include SPS (bis (3-sulfopropyl) disulfide disodium).

最後に、導体パターン２８上面および側面にニッケル、金の順で表面めっき処理層２９としての最終めっきを施す（図１（ｈ））。この一連の工程により、半導体装置用テープキャリア３１を製造する。
なお、前記表面めっき処理層２９は接合方式に応じて、スズ、はんだ等、別の金属めっきを選択してもよい。また、前記表面めっき処理層２９を設ける際に、絶縁層としてソルダーレジスト３０を所定の形状に設けてもよい。 Finally, final plating as a surface plating layer 29 is performed on the upper and side surfaces of the conductor pattern 28 in the order of nickel and gold (FIG. 1 (h)). Through this series of steps, the tape carrier 31 for semiconductor devices is manufactured.
The surface plating layer 29 may be selected from another metal plating such as tin or solder according to the bonding method. Further, when the surface plating layer 29 is provided, a solder resist 30 may be provided in a predetermined shape as an insulating layer.

ここで、本発明の一実施形態に係る半導体装置用テープキャリアの製造工程内のめっき充填工程について詳細を説明する。   Here, the plating filling process in the manufacturing process of the semiconductor device tape carrier according to the embodiment of the present invention will be described in detail.

図２は、本発明の一実施形態におけるめっき充填工程に用いられる銅めっき装置の概略平面図である。
図２に示されるように、前記絶縁フィルム２１の上面に銅箔２４を貼り合わせている図１（ｄ）の状態のテープキャリア３２は、巻き出し部３３においてリール３４から巻き出されるリール・トゥ・リール方式にて行うのが好ましい。 FIG. 2 is a schematic plan view of a copper plating apparatus used in the plating filling process in one embodiment of the present invention.
As shown in FIG. 2, the tape carrier 32 in the state of FIG. 1D in which the copper foil 24 is bonded to the upper surface of the insulating film 21 is reel-toe unwound from the reel 34 at the unwinding portion 33. -It is preferable to use the reel method.

次に、前側給電ロール（カソード側）３５にテープキャリア３２の銅箔２４上面を接触させた後、マスキングテープ貼付装置３６によって微粘着のマスキングテープをテープキャリア３２の銅箔２４上面に貼り合わせる。   Next, after the upper surface of the copper foil 24 of the tape carrier 32 is brought into contact with the front power supply roll (cathode side) 35, a slightly adhesive masking tape is bonded to the upper surface of the copper foil 24 of the tape carrier 32 by the masking tape applying device 36.

めっき充填工程の前処理として、酸性脱脂槽３７にてテープキャリア３２を洗浄し、その後、酸洗槽３８にて過酸化水素−硫酸系の化学研摩液で開口２３内の銅箔２４面をエッチングする。このように、前記銅箔２４の下面における前記開口２３越しに露出した部分の防錆皮膜を化学研摩液により除去するのが好ましい。前記銅箔２４の下面における前記開口２３越しに露出した部分は通常、防錆皮膜としてニッケル、亜鉛等の異種金属が付着している。この状況下において、異種金属の混入による接合信頼性の低下を防ぐ目的から、この防錆皮膜層は銅めっきの前処理において化学研摩液で除去しておく必要があるためである。
なお、図２には図示していないけれども、槽間においてテープキャリア３２の水洗処理を行っている。以降の工程においても、同様の処理を行っている。 As a pretreatment of the plating filling process, the tape carrier 32 is washed in an acid degreasing tank 37, and then the surface of the copper foil 24 in the opening 23 is etched with a hydrogen peroxide-sulfuric acid type chemical polishing liquid in an acid washing tank 38. To do. As described above, it is preferable to remove the portion of the anticorrosive film exposed through the opening 23 on the lower surface of the copper foil 24 with the chemical polishing liquid. A portion of the lower surface of the copper foil 24 exposed through the opening 23 is usually attached with a different metal such as nickel or zinc as a rust preventive film. This is because the rust preventive coating layer needs to be removed with a chemical polishing solution in the pretreatment of the copper plating in order to prevent a decrease in bonding reliability due to the mixing of different metals under this situation.
Although not shown in FIG. 2, the tape carrier 32 is washed with water between the tanks. Similar processing is performed in the subsequent steps.

そして、テープキャリア３２に対してめっき充填工程の前処理を行った後、銅めっき槽３９を通過させる。
前記銅めっき槽３９は、銅めっき装置において多段槽ではなく１槽のみ設けられているのが好ましい。多段槽とする場合、槽を移動する際に銅めっきを中断することになるため、銅めっきが多段の層となるように形成されてしまい、結果的に脆い界面が形成されてしまうためである。 And after performing the pre-process of a plating filling process with respect to the tape carrier 32, the copper plating tank 39 is passed.
It is preferable that the copper plating tank 39 is not a multi-stage tank but only one tank in the copper plating apparatus. In the case of a multi-stage tank, copper plating is interrupted when the tank is moved, so that the copper plating is formed to be a multi-stage layer, and as a result, a brittle interface is formed. .

前記銅めっき槽３９には硫酸銅からなる銅めっき液４１が満たされており、さらにその内部には不溶性の電極（アノード側）４０が配置されている。さらに、本実施形態では、噴流攪拌を行うための噴流ノズル４２が配置されている。噴流ノズル４２が設けられてい
なくとも、銅めっき槽３９内においては攪拌が行われ、さらにテープキャリア３２自身が搬送されることにより若干の攪拌状態となっているが、これに加え銅めっき液の攪拌状態をさらに強力にすることができ、ひいては電流密度向上に有利となるようにするためである。なお、噴流ノズル４２の噴流圧力は０．ｌＭＰａ以上とするのが好ましい。これにより、めっき部近傍の攪拌を良好に行うことができ、従来に比べて高い電流密度においても銅イオンの供給が円滑に行なわれるためである。 The copper plating tank 39 is filled with a copper plating solution 41 made of copper sulfate, and further, an insoluble electrode (anode side) 40 is disposed therein. Furthermore, in this embodiment, the jet nozzle 42 for performing jet stirring is arrange | positioned. Even if the jet nozzle 42 is not provided, stirring is performed in the copper plating tank 39, and the tape carrier 32 itself is further transported to form a slight stirring state. This is because the agitation state can be further increased, which is advantageous for improving the current density. The jet pressure of the jet nozzle 42 is 0. It is preferable to be 1 MPa or more. This is because the vicinity of the plated portion can be satisfactorily stirred, and copper ions can be supplied smoothly even at a higher current density than in the past.

まとめると、この銅めっき槽３９内では、不溶性の電極（アノード側）４０によって電界をかけながら、噴流ノズル４２によって銅めっき液４１をテープキャリア３２に噴流させる。
これにより、テープキャリア３２が銅めっき槽３９を通過する際、前記銅箔２４の下面における前記開口２３越しに露出した部分に対して銅めっき２７を施す。なお、銅箔２４の他の部分については、そもそも銅箔２４が露出していないため、または、マスキングテープ２６によりマスキングが施されているため、銅めっき２７は施されない。 In summary, in this copper plating tank 39, the copper plating solution 41 is jetted onto the tape carrier 32 by the jet nozzle 42 while applying an electric field by the insoluble electrode (anode side) 40.
Thereby, when the tape carrier 32 passes through the copper plating tank 39, the copper plating 27 is applied to the portion exposed through the opening 23 on the lower surface of the copper foil 24. In addition, about the other part of the copper foil 24, since the copper foil 24 is not exposed to the first place, or since it is masked by the masking tape 26, the copper plating 27 is not performed.

銅めっき槽３９通過後、後洗浄槽４３で銅めっき液４１を洗い流す。そして、マスキングテープ剥離装置４４によりマスキングテープ２６を剥離し、後側給電ロール（カソード側）４５に銅箔２４の上面を接触させる。
さらに後水洗浄槽４６で水洗浄後、乾燥槽４７で乾燥して巻き取り部４８でリール４９に巻き取られる。 After passing through the copper plating tank 39, the copper plating solution 41 is washed away in the post-cleaning tank 43. Then, the masking tape 26 is peeled off by the masking tape peeling device 44, and the upper surface of the copper foil 24 is brought into contact with the rear power supply roll (cathode side) 45.
Further, after washing with water in the post-water washing tank 46, it is dried in the drying tank 47 and taken up on the reel 49 by the take-up unit 48.

上述の通り、本実施形態によれば、従来よりも高い電流密度での開口２３ヘの銅めっき２７の充填を可能とすることにより、テープキャリアの生産性を向上させ、接続信頼性を高めることができる。本実施形態によって製造された半導体装置用テープキャリアは、半導体装置、特にファインピッチのＢＧＡ型パッケージ（Ｆ−ＢＧＡ）に好適である。   As described above, according to the present embodiment, it is possible to improve the productivity of the tape carrier and increase the connection reliability by enabling the copper plating 27 to be filled in the opening 23 at a higher current density than before. Can do. The tape carrier for a semiconductor device manufactured according to the present embodiment is suitable for a semiconductor device, particularly a fine pitch BGA type package (F-BGA).

以下に、本発明の実施例を、図１を用いて説明する。
（実施例１）
まず、基板となるポリイミドフィルム２１（ユーピレックスＳ：厚さ５０μｍ）上に接着剤層２２（巴川Ｘ：厚さ１２μｍ）を設け（図１（ａ））、この接着剤層２２付きポリイミドフィルム２１を厚さ方向に貫通するビアホール２３（φ２８０μｍ）を設け（図１（ｂ））、ロール２５ａ，２５ｂにて銅箔２４（ＶＬＰ箔：厚さ１８μｍ）を貼り合わせた（図１（ｃ）（ｄ））。
そして、銅箔２４にマスキングテープ２６を貼り付け、ビアホール２３に対して銅めっき２７を、４０μｍ充填した（図１（ｅ））。
このとき、銅めっき液の噴流圧力を０．１ＭＰａとし、銅めっき時の電流密度は１５Ａ／ｄｍ２とした。
めっき充填工程の後、マスキングテープ２６を剥がし（図１（ｆ））、銅箔２４をフォトエッチングすることにより導体パターン２８を形成した（図１（ｇ））。
最後に、絶縁性を有するソルダーレジスト３０を所定の形状に形成したのち、金とニッケルからなる表面めっき処理層２９を設けた（図１（ｈ））。この一連の工程により、本実施例における半導体装置用テープキャリア３１を作製した。 An embodiment of the present invention will be described below with reference to FIG.
Example 1
First, an adhesive layer 22 (Yodogawa X: thickness 12 μm) is provided on a polyimide film 21 (Upilex S: thickness 50 μm) serving as a substrate (FIG. 1A), and the polyimide film 21 with the adhesive layer 22 is attached. A via hole 23 (φ280 μm) penetrating in the thickness direction was provided (FIG. 1B), and copper foil 24 (VLP foil: thickness 18 μm) was bonded by rolls 25a and 25b (FIGS. 1C and 1D). )).
And the masking tape 26 was affixed on the copper foil 24, and the copper plating 27 was filled with 40 micrometer with respect to the via hole 23 (FIG.1 (e)).
At this time, the jet pressure of the copper plating solution was 0.1 MPa, and the current density during copper plating was 15 A / dm 2 .
After the plating filling step, the masking tape 26 was peeled off (FIG. 1 (f)), and the copper foil 24 was photoetched to form a conductor pattern 28 (FIG. 1 (g)).
Finally, a solder resist 30 having insulating properties was formed into a predetermined shape, and then a surface plating layer 29 made of gold and nickel was provided (FIG. 1 (h)). Through this series of steps, the semiconductor device tape carrier 31 in this example was manufactured.

（実施例２〜３）
実施例２においては、銅めっき時の電流密度を３０Ａ／ｄｍ２とした以外は、実施例１と同様に半導体装置用テープキャリア３１を作製した。
実施例３においては、銅めっき時の電流密度を６０Ａ／ｄｍ２とした以外は、実施例１と同様に半導体装置用テープキャリア３１を作製した。 (Examples 2-3)
In Example 2, a tape carrier 31 for a semiconductor device was produced in the same manner as in Example 1 except that the current density at the time of copper plating was 30 A / dm 2 .
In Example 3, a tape carrier 31 for a semiconductor device was produced in the same manner as in Example 1 except that the current density at the time of copper plating was 60 A / dm 2 .

（比較例１〜２）
図７に示すように、比較例１においては、めっき充填工程の前に、導体パターン１１５を形成し、その後でめっき充填工程を行い、銅めっき時の電流密度を３０Ａ／ｄｍ２とした以外は、実施例１と同様に半導体装置用テープキャリア１２０を作製した。
比較例２においては、めっき充填工程の前に、導体パターン１１５を形成し、その後でめっき充填工程を行い、銅めっき時の電流密度を５Ａ／ｄｍ２とし、銅めっき液の噴流を行わなかった以外は、実施例１と同様に半導体装置用テープキャリア１２０を作製した。 (Comparative Examples 1-2)
As shown in FIG. 7, in Comparative Example 1, the conductive pattern 115 is formed before the plating filling step, and then the plating filling step is performed, and the current density at the time of copper plating is set to 30 A / dm 2. In the same manner as in Example 1, a semiconductor device tape carrier 120 was produced.
In Comparative Example 2, the conductor pattern 115 was formed before the plating filling step, and then the plating filling step was performed. The current density during copper plating was 5 A / dm 2 and the copper plating solution was not jetted. Except for the above, a semiconductor device tape carrier 120 was produced in the same manner as in Example 1.

以上のようにして作製した実施例および比較例の試料について、めっき所要時間、めっき外観と電流効率、および接続信頼性を評価した。その結果を図３に示す。
なお、前記電流効率は、めっき電流と、めっき時間と、めっき充填工程前後における試料の重量差すなわちめっき析出量とから算出した。具体的には、めっき析出量が理論析出量であれば電流効率１００％として、電流効率を算出した。また、前記接続信頼性は、温度サイクル試験後における銅箔２４と銅めっき２７との間のクラック発生の有無から判断した。この温度サイクル試験は、低温側を−６５℃、高温側を１５０℃とし、各設定温度のホールド時間を３０分とし、１００サイクルを行った。 About the sample of the Example and comparative example produced as mentioned above, plating required time, plating appearance and current efficiency, and connection reliability were evaluated. The result is shown in FIG.
The current efficiency was calculated from the plating current, the plating time, and the weight difference of the sample before and after the plating filling step, that is, the plating deposition amount. Specifically, if the plating deposition amount is the theoretical deposition amount, the current efficiency was calculated assuming that the current efficiency was 100%. The connection reliability was judged from the presence or absence of cracking between the copper foil 24 and the copper plating 27 after the temperature cycle test. In this temperature cycle test, the low temperature side was −65 ° C., the high temperature side was 150 ° C., the hold time of each set temperature was 30 minutes, and 100 cycles were performed.

評価結果を示す図３より、実施例１〜３では、比較例に比べて高電流密度化が可能となり、めっきの所要時間は従来の１／３〜１／１２に短縮できた。また、めっき外観および電流効率は正常であり、銅箔２４と銅めっき２７との間のクラックの発生も確認できなかった。   From FIG. 3 showing the evaluation results, in Examples 1 to 3, it was possible to increase the current density compared to the comparative example, and the time required for plating could be shortened to 1/3 to 1/12 of the conventional case. Moreover, the plating appearance and current efficiency were normal, and the occurrence of cracks between the copper foil 24 and the copper plating 27 could not be confirmed.

比較例１では、めっき異常（ヤケめっき）が発生した。実施例２と同じ電流密度であるものの、導体パターン１１５作製後に銅めっき１１７を施したため、許容電流値が小さくなったことが原因と推定される。
比較例２では、めっき外観および電流効率は正常であるが、めっき時間が本実施例に比べて長時間を要すこと、銅箔１１３と銅めっき１１７との間のクラックが発生頻度５％の割合で発生したことから、本実施例と比較して劣っていると判断した。 In Comparative Example 1, a plating abnormality (discoloration plating) occurred. Although it is the same current density as Example 2, since the copper plating 117 was performed after conductor pattern 115 preparation, it is estimated that the allowable current value became small.
In Comparative Example 2, the plating appearance and current efficiency are normal, but the plating time requires a long time compared with the present example, and the occurrence frequency of cracks between the copper foil 113 and the copper plating 117 is 5%. Since it occurred at a rate, it was judged to be inferior to the present example.

２１ 絶縁フィルム
２２ 接着剤層
２３ 開口
２４ 銅箔
２５ ロール
２６ マスキングテープ
２７ 銅めっき
２８ 導体パターン
２９ 表面めっき処理層
３０ ソルダーレジスト
３１ 半導体装置用テープキャリア
３２ テープキャリア
３３ 巻き出し部
３４ リール
３５ 前側給電ロール（カソード）
３６ マスキングテープ貼付装置
３７ 酸性脱脂槽
３８ 酸洗槽
３９ 銅めっき槽
４０ 不溶性電極（アノード）
４１ 銅めっき液
４２ めっき液噴流ノズル
４３ 後洗浄槽
４４ マスキングテープ剥離装置
４５ 後側給電ロール（カソード）
４６ 後水洗浄槽
４７ 乾燥槽
４８ 巻き取り部
４９ リール
１０１ 半導体装置
１０２ テープキャリア
１０３ 導体パターン
１０４ 半導体素子
１０５ 電極
１０６ ボンディングワイヤ
１０７ 封止樹脂
１０８ ビアホール
１０９ はんだボール
１１０ ポリイミドフィルム
１１１ 接着剤層
１１２ 開口
１１３ 銅箔
１１４ ロール
１１５ 導体パターン
１１６ マスキングテープ
１１７ 銅めっき
１１８ 表面めっき処理層
１１９ ソルダーレジスト
１２０ 半導体装置用テープキャリア 21 Insulating film 22 Adhesive layer 23 Opening 24 Copper foil 25 Roll 26 Masking tape 27 Copper plating 28 Conductive pattern 29 Surface plating layer 30 Solder resist 31 Tape carrier 32 for semiconductor device Tape carrier 33 Unwinding part 34 Reel 35 Front power supply roll (Cathode)
36 Masking tape application device 37 Acidic degreasing bath 38 Pickling bath 39 Copper plating bath 40 Insoluble electrode (anode)
41 Copper Plating Solution 42 Plating Solution Jet Nozzle 43 Back Washing Tank 44 Masking Tape Peeling Device 45 Rear Feed Roll (Cathode)
46 Post-water washing tank 47 Drying tank 48 Winding part 49 Reel 101 Semiconductor device 102 Tape carrier 103 Conductive pattern 104 Semiconductor element 105 Electrode 106 Bonding wire 107 Sealing resin 108 Via hole 109 Solder ball 110 Polyimide film 111 Adhesive layer 112 Opening 113 Copper foil 114 Roll 115 Conductor pattern 116 Masking tape 117 Copper plating 118 Surface plating layer 119 Solder resist 120 Tape carrier for semiconductor device

Claims (3)

絶縁フィルムを厚さ方向に貫通する開口を設ける工程と、
前記絶縁フィルムの上面に電解銅箔を貼り合わせることにより、前記絶縁フィルムの下面に前記開口越しにて前記電解銅箔を露出させる工程と、
前記電解銅箔の上面にマスキングを施した後に、電解めっき方式により前記電解銅箔の下面における前記開口越しに露出した部分に対して銅めっきを行うことにより、前記開口の深さを小とするめっき充填工程と、
前記めっき充填工程の後に、前記マスキングが除去された電解銅箔を上面側からフォトエッチングすることにより、導体パターンを形成する工程と、
前記導体パターンに表面めっき処理層を形成する工程と、
を有し、
前記めっき充填工程をリール・トゥ・リール方式で行い、
前記リール・トゥ・リール方式にて使用する銅めっき槽における銅めっき液の噴流圧力を０．１ＭＰａ以上とし、前記めっき充填工程における電流密度を１５〜６０Ａ／ｄｍ 2 にすることにより前記めっき充填工程における電流密度と前記電解銅箔を形成する際の電流密度との差を小さくするように前記銅めっきを行う
ことを特徴とする半導体装置用テープキャリアの製造方法。 Providing an opening penetrating the insulating film in the thickness direction;
A step of exposing the electrolytic copper foil through the opening to the lower surface of the insulating film by bonding an electrolytic copper foil to the upper surface of the insulating film;
After masked on the upper surface of the electrodeposited copper foil, by performing copper plating to the portion exposed in the opening over the lower surface of the electrodeposited copper foil through electroplating, and a small depth of the opening Plating filling process;
After the plating filling step, by photoetching the electrolytic copper foil from which the masking has been removed from the upper surface side, a step of forming a conductor pattern;
Forming a surface plating layer on the conductor pattern;
I have a,
The plating filling process is performed by a reel-to-reel method,
The plating filling step by the jet pressure of the copper plating solution as above 0.1MPa in the copper plating bath for use in a reel-to-reel method, the current density in the plating filling step 15~60A / dm 2 The method of manufacturing a tape carrier for a semiconductor device , wherein the copper plating is performed so as to reduce a difference between a current density in the step and a current density at the time of forming the electrolytic copper foil . 前記めっき充填工程時に使用する銅めっき液は硫酸銅系の電解銅めっき液であり、添加剤成分として界面活性剤および／または光沢剤を含むことを特徴とする請求項１に記載の半導体装置用テープキャリアの製造方法。 2. The semiconductor device according to claim 1, wherein the copper plating solution used in the plating filling step is a copper sulfate-based electrolytic copper plating solution, and includes a surfactant and / or a brightener as an additive component. Tape carrier manufacturing method. 前記銅めっき槽を１槽とし、
前記めっき充填工程の前処理として、前記電解銅箔の下面における前記開口越しに露出した部分の防錆皮膜を化学研摩液により除去する
ことを特徴とする請求項１または２に記載の半導体装置用テープキャリアの製造方法。 The copper plating tank is one tank ,
As pre-treatment before Symbol plating filling step, the semiconductor device according to claim 1 or 2, characterized in that the removal by chemical polishing liquid rust preventing film of the exposed portion in the opening over the lower surface of the electrodeposited copper foil Tape carrier manufacturing method.
JP2009070717A 2009-03-23 2009-03-23 Manufacturing method of tape carrier for semiconductor device Expired - Fee Related JP5136799B2 (en)

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