JP5135004B2 - 不揮発性半導体記憶装置、及びディプレッション型mosトランジスタ - Google Patents
不揮発性半導体記憶装置、及びディプレッション型mosトランジスタ Download PDFInfo
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- JP5135004B2 JP5135004B2 JP2008050066A JP2008050066A JP5135004B2 JP 5135004 B2 JP5135004 B2 JP 5135004B2 JP 2008050066 A JP2008050066 A JP 2008050066A JP 2008050066 A JP2008050066 A JP 2008050066A JP 5135004 B2 JP5135004 B2 JP 5135004B2
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- 239000004065 semiconductor Substances 0.000 title claims description 61
- 239000012535 impurity Substances 0.000 claims description 61
- 238000009792 diffusion process Methods 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 24
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 46
- 108091006146 Channels Proteins 0.000 description 41
- 229910052785 arsenic Inorganic materials 0.000 description 12
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 238000002513 implantation Methods 0.000 description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 238000009826 distribution Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101150110971 CIN7 gene Proteins 0.000 description 1
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 1
- 101150110298 INV1 gene Proteins 0.000 description 1
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 1
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
従来、半導体記憶装置の一つとして、電気的書き替えを可能とした不揮発性半導体記憶装置が知られている。なかでも、メモリセルを複数個直列接続してNANDセルブロックを構成するNAND型フラッシュメモリは、高集積化ができるものとして広く用いられている。
電圧切換回路54Aは、出力ノードN10と電源ノードVRDECとの間に、トランジスタHND1と、これにノードN2(トランジスタHND1のソース)でトランジスタHND1と直列に接続されたトランジスタHPとを備えている。トランジスタHND1は、高耐圧でディプリッション型(D型)のnチャネル型MOSトランジスタであり、その閾値電圧Vth(HND1)は負の値を有する。トランジスタHPは、高耐圧でエンハンスメント型(E型)のPチャネルMOSトランジスタであり、その閾値電圧Vth(HP)は負の値を有する。
またこの電圧切換回路54Aでは、入力電圧INPUTが入力されるノードN9と出力ノードN10との間に、インバータ回路INV1、INV2、低耐圧でD型(すなわち、負の閾値電圧Vth(LND)を有する)のNチャネルMOSトランジスタLND、及び高耐圧でD型のNチャネルMOSトランジスタHND2(負の閾値電圧Vth(HND2)を有する)が直列接続されている。トランジスタLND、及びトランジスタHND2は、制御信号BSTONをそのゲートに印加され、全体としてスイッチング回路を構成している。
Claims (6)
- 半導体基板上にゲート絶縁膜を介して形成された電荷蓄積層を具備するメモリセルトランジスタを配列してなるメモリセルアレイと、
前記メモリセルトランジスタを駆動するための周辺回路とを備え、
前記周辺回路は、少なくとも第1のトランジスタを含み、
前記第1のトランジスタは、
半導体層と、
半導体層の表面にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極の直下近傍の前記半導体層の表面に形成され第1の不純物濃度を有する第1導電型のチャネル領域と、
前記ゲート電極に対し自己整合的に前記半導体層の表面に形成され前記第1の不純物濃度よりも大きな第2の不純物濃度を有する第1導電型のソース・ドレイン拡散領域と、
前記チャネル領域と前記ソース・ドレイン拡散領域とが重複する前記ゲート電極直下の前記半導体層の表面に形成され前記第2の不純物濃度よりも大きな第3の不純物濃度を有する第1導電型の重複領域とを備える
ことを特徴とする不揮発性半導体記憶装置。 - 前記周辺回路は、前記第1のトランジスタに加え第2のトランジスタを備え、
前記第2のトランジスタは、
前記半導体層の表面にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極の直下を含む前記半導体層の表面に形成され第4の不純物濃度を有する第1導電型のチャネル領域と、
前記ゲート電極に対し自己整合的に前記チャネル領域内に形成され前記第4の不純物濃度よりも大きな第5の不純物濃度を有する第1導電型のソース・ドレイン拡散領域と
を備えたことを特徴とする請求項1記載の不揮発性半導体記憶装置。 - 前記第1のトランジスタは、前記ソース・ドレイン拡散領域の表面の少なくとも一部に形成され前記第2の不純物濃度よりも大きな第6の不純物濃度を有する第1導電型のコンタクト領域を更に備えた請求項1または請求項2に記載の不揮発性半導体記憶装置。
- 前記チャネル領域において注入される不純物は、前記ソース・ドレイン拡散領域に注入される不純物とは種類が異なることを特徴とする請求項1乃至請求項3のいずれかに記載の不揮発性半導体記憶装置。
- 半導体層と、
半導体層の表面にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極の直下近傍の前記半導体層の表面に形成され第1の不純物濃度を有する第1導電型のチャネル領域と、
前記ゲート電極に対し自己整合的に前記半導体層の表面に形成され前記第1の不純物濃度よりも大きな第2の不純物濃度を有する第1導電型のソース・ドレイン拡散領域と、
前記チャネル領域と前記ソース・ドレイン拡散領域とが重複する前記ゲート電極直下の前記半導体層の表面に形成され前記第2の不純物濃度よりも大きな第3の不純物濃度を有する第1導電型の重複領域と、
を備えたことを特徴とするディプレッション型MOSトランジスタ。 - 前記第1の不純物濃度と前記第4の不純物濃度が同じであり、
前記第3の不純物濃度と前記第5の不純物濃度が同じであることを特徴とする請求項2に記載の不揮発性半導体記憶装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008050066A JP5135004B2 (ja) | 2008-02-29 | 2008-02-29 | 不揮発性半導体記憶装置、及びディプレッション型mosトランジスタ |
US12/359,643 US8093664B2 (en) | 2008-02-29 | 2009-01-26 | Non-volatile semiconductor memory device and depletion-type MOS transistor |
KR1020090016801A KR101110538B1 (ko) | 2008-02-29 | 2009-02-27 | 불휘발성 반도체 메모리 장치 및 공핍형 mos 트랜지스터 |
US13/211,928 US20110300680A1 (en) | 2008-02-29 | 2011-08-17 | Non-volatile semiconductor memory device and depletion-type mos transistor |
Applications Claiming Priority (1)
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JP2008050066A JP5135004B2 (ja) | 2008-02-29 | 2008-02-29 | 不揮発性半導体記憶装置、及びディプレッション型mosトランジスタ |
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JP2009206450A JP2009206450A (ja) | 2009-09-10 |
JP5135004B2 true JP5135004B2 (ja) | 2013-01-30 |
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US (2) | US8093664B2 (ja) |
JP (1) | JP5135004B2 (ja) |
KR (1) | KR101110538B1 (ja) |
Cited By (1)
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JP7403502B2 (ja) | 2017-05-29 | 2023-12-22 | 株式会社Ihi | 燃焼炉及びボイラ |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5135004B2 (ja) * | 2008-02-29 | 2013-01-30 | 株式会社東芝 | 不揮発性半導体記憶装置、及びディプレッション型mosトランジスタ |
CN104270748B (zh) * | 2008-03-31 | 2018-09-04 | 爱立信电话股份有限公司 | 为小区转发接入信道状态中的增强型专用信道处理标识符 |
JP2011009695A (ja) * | 2009-05-29 | 2011-01-13 | Toshiba Corp | 不揮発性半導体記憶装置及びディプレッション型mosトランジスタ |
US8547738B2 (en) * | 2010-03-15 | 2013-10-01 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
KR20110120044A (ko) * | 2010-04-28 | 2011-11-03 | 삼성전자주식회사 | 안티퓨즈, 이를 포함하는 안티퓨즈 회로, 및 안티퓨즈 제조 방법 |
JP5487034B2 (ja) * | 2010-07-20 | 2014-05-07 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP2012204435A (ja) * | 2011-03-24 | 2012-10-22 | Toshiba Corp | 不揮発性半導体記憶装置 |
US9368619B2 (en) | 2013-02-08 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for inducing strain in vertical semiconductor columns |
CN104009078B (zh) * | 2013-02-26 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | 无结晶体管及其制造方法 |
US8999805B1 (en) * | 2013-10-05 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device with reduced gate length |
US9564493B2 (en) | 2015-03-13 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
US10886405B2 (en) | 2016-12-07 | 2021-01-05 | Macronix International Co., Ltd. | Semiconductor structure |
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JP2006100693A (ja) | 2004-09-30 | 2006-04-13 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2006196061A (ja) * | 2005-01-12 | 2006-07-27 | Toshiba Corp | 電圧切換回路、及びこれを用いた半導体記憶装置 |
JP5135004B2 (ja) * | 2008-02-29 | 2013-01-30 | 株式会社東芝 | 不揮発性半導体記憶装置、及びディプレッション型mosトランジスタ |
-
2008
- 2008-02-29 JP JP2008050066A patent/JP5135004B2/ja not_active Expired - Fee Related
-
2009
- 2009-01-26 US US12/359,643 patent/US8093664B2/en active Active
- 2009-02-27 KR KR1020090016801A patent/KR101110538B1/ko not_active IP Right Cessation
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2011
- 2011-08-17 US US13/211,928 patent/US20110300680A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7403502B2 (ja) | 2017-05-29 | 2023-12-22 | 株式会社Ihi | 燃焼炉及びボイラ |
Also Published As
Publication number | Publication date |
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US20090218637A1 (en) | 2009-09-03 |
US20110300680A1 (en) | 2011-12-08 |
KR101110538B1 (ko) | 2012-01-31 |
US8093664B2 (en) | 2012-01-10 |
JP2009206450A (ja) | 2009-09-10 |
KR20090093872A (ko) | 2009-09-02 |
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