JP5120653B2 - 半田層及びそれを用いたデバイス接合用基板並びに該デバイス接合用基板の製造方法 - Google Patents
半田層及びそれを用いたデバイス接合用基板並びに該デバイス接合用基板の製造方法 Download PDFInfo
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- JP5120653B2 JP5120653B2 JP2008510881A JP2008510881A JP5120653B2 JP 5120653 B2 JP5120653 B2 JP 5120653B2 JP 2008510881 A JP2008510881 A JP 2008510881A JP 2008510881 A JP2008510881 A JP 2008510881A JP 5120653 B2 JP5120653 B2 JP 5120653B2
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- solder layer
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- Die Bonding (AREA)
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- Wire Bonding (AREA)
Description
一方、300℃以下の温度で半田接合を行なった場合には、デバイスへの熱負荷が小さくなるので、デバイスの損傷が生じる可能性は低くなるが、半田接合の初期接合強度が弱く、落下等により半田接合が外れてしまうおそれがあることから、デバイスを実装した基板の取扱いに注意が必要である。従って、半田接合の接合強度を短期間に増大させることが課題となっている。また、近年のデバイスの高出力化や小型化に伴い、デバイスから発生する熱を効果的に逃すことがデバイス特性や信頼性向上に必須となっている。現在、デバイスとパッケージとの間に接合基板を配置することでデバイスから発生する熱を放熱している。接合基板は、半田層と高熱伝導率を有する基板とから構成され、サブマウントと呼ばれている。しかしながら、従来の半田層では、半田層とデバイスとの間の接触抵抗による電気抵抗や熱抵抗が大きいためにデバイス特性が想定どおりに向上しないといった課題もあった。
上記構成によれば、半田層表面を均一に溶解することが可能となり、半田層の溶解凝固後にも平衡状態となるため、デバイスと半田層とで形成される半田接合の初期接合強度を安定させることができる。また、デバイスとの初期接合強度が高い半田層を得ることができる。また、熱抵抗をも小さくできるので、半田接合した後のデバイス特性及びその信頼性を向上させることができる。したがって、従来の携帯電話や民生機器等の小型モジュールのみならず、熱的に負荷が大きい用途、例えば、自動車用途、パワーデバイス用途にも十分使用することができる。
上記構成によれば、半田層とデバイスとの初期接合強度が高いデバイス接合用基板を提供することができる。
本発明の方法によれば、半田層内に複数の層を分離させて形成することができ、半田層を平衡状態にすることが可能となり、デバイスと半田層との初期接合強度が高くかつ熱抵抗の小さいデバイス接合用基板を製造することができる。
2:基板
3:密着層
3a:表面側密着層
3b:裏面側密着層
4,13:電極層
4a:表面側電極層
4b:裏面側電極層
5,14:半田層
5a:表面側半田層
5b:裏面側半田層
5c:半田層のデバイス接合面側の半田層(Au5 Sn)
5d:半田層の基板接合面側の半田層(AuSn)
5e:液相
5f:溶解開始温度が高い相
7,15:半導体装置(デバイス)
11:金属基板
12:セラミック層(セラミック薄膜)
15a:半導体装置の上部電極
15b:半導体装置の下部電極
16:Au線
22:ステム
24:低温半田(導電ペースト)
図1は本発明によるデバイス接合用基板の構造を模式的に示す断面図である。図1に示すように、デバイス接合用基板1は、基板2上に密着層3を介して形成される電極層4とこの上に形成される半田層5とから構成される。第一の実施形態では、密着層3、電極層4及び半田層5はそれぞれ基板2の表裏両面に形成されている。即ち、基板2を挟んで表側と裏側にはそれぞれ、密着層3a,3bを介して表面側電極層4aと裏面側電極層4bが形成され、各電極層の所定箇所に表面側半田層5aと裏面側半田層5bとが積層されて形成されている。ここで、電極層4は、上記基板2の全面に形成してもよいし、電極パターンとして形成してもよい。また、電極層4の一部には、金線を接続して電気回路を形成してもよい。なお、密着層3、電極層4及び半田層5は、基板2の片面のみに形成されていてもよい。上記密着層3は半田層5と電極層4との密着度を向上するために用いるが、両者の密着度が良好であれば、密着層3を介することなく直接これらを貼着などで積層してもよい。
図5は、図1に示したデバイス接合用基板1に半導体装置7を実装した構造を模式的に示す断面図である。図5に示すように、デバイス接合用基板1において、半導体装置7は表面側の半田層5aにより半田接合をすることができる。
なお、図5及び図6においては実装するデバイスとして半導体装置7,15を示しているが、受動素子、スイッチ等や各種能動素子を含む、所謂電子デバイスであれば何でもよく、複数のデバイスが基板上の半田層5,14に半田接合されてもよい。
図7(A)に示すように、本発明の表面側の半田層5aは、その溶解前には、溶解開始温度の異なる相が2層5c,5dに分離されて平衡状態になっている。図7(B)は図7(A)の半田層5aを加熱して半田接合温度とした状態、すなわち半田層5aが溶解した状態を、液相5eとして示している。このとき、デバイスの接合面側である半田層の上層5cは相対的に低い溶解開始温度のAu5Sn相であり、半田層の下層5dは相対的に高い溶解開始温度のAuSn相であるので、デバイスの接合面側のAu5Sn相5cが先に溶解状態となる。すなわち、本発明の半田層5aは上層5cに相対的に低融点のAu5Snが分離されているため、デバイス接合面側を均一に溶解させることができる。従って、半田層5aの均一な濡れ性を確保することができるため、デバイス7の接合部全体を、半田層5aを介して基板2と接合することができる。さらには、半田層5aのAu5Sn上層5cのみを溶解させて接合するため、図7(C)に示すように、半田層5aを冷却してデバイス接合した後も、半田層が2層5c,5dに分離した平衡状態に維持することができ、初期接合強度を向上させることができる。本発明の半田層5aを用いてデバイス7を接合させることで、半田接合の初期接合強度を30MPa以上とすることができ、安定的な初期接合強度を得ることができる。
図8(A)に示す状態から、図8(B)に示す半田層5aの接合温度に上昇させて、半田層5aを溶解すると、AuとSnとの溶解開始温度が高い相5f(図の粒状物)がデバイス接合面付近にも存在するため、一部が半田層5aの表面にまで飛び出ている状態となり、デバイス接合面側の半田層5aを均一に溶解することができない。そのため、半田層5aの溶解している箇所とデバイス7との接触面積を小さくし、デバイス7と半田層5aとの接合が局所的に阻害されるため、良好な半田接合強度が得られなくなる。なお、図8(B)及び(C)の半田層の下層5dはAu−Sn層である。
図9は、図1のデバイス接合用基板の製造工程を順次に示すフローチャートである。
ステップST1にて、AlNから成る基板2を用意する。ステップST2にて、上記基板2の表面をラップ,ポリッシュ等の工程により研削及び研磨した後、ステップST3にて、フォトリソグラフィ法等によりパターニングを行ない、電極層4が形成される領域のみを露出させる。
次にステップST6にて、上記基板上に半田層5を各種の蒸着法を用いて形成し、さらにリフトオフ工程により、上記半田層5の所定のパターンのみを残して、他の部分を除去する。
以上の工程により、半田層5を複数の固相に分離させることができる。この場合、熱処理温度は、加熱に用いる炉を一定温度に保つように温度制御されることが好ましい。
最初に、デバイス接合用基板1の製造方法について、この基板1をサブマウントに適用した実施例について説明する。
AlNからなる基板2の両面を洗浄して表面清浄化を行ない、この基板2の表面上に厚さ0.05μmのTi密着層3、密着層3上に厚さが0.2μmのPtと厚さが0.5μmのAuから成る電極層4、電極層4上の一部に、厚さ3μmで組成比としてAu:Sn=70:30(重量比)から成る単層の半田層5を真空蒸着法により形成した。成膜条件は真空度を1×10-4Pa、基板温度を80℃とした。
上記の加工を施した基板2を、大気雰囲気中において、共晶反応温度の278℃未満の220℃で、それぞれ、0.1,1,5,10時間の半田層5の熱処理を施し、実施例1のサブマウント1を製造した。
次に、サブマウント1の半田層5の密着強度を調べるためのテープ剥離テストを行なった。テープ剥離試験で半田層5が剥離しなかったサブマウント1をダイシング装置で所定の形状に切断した。切断したサブマウント1に発光ダイオード7を半田接合した。具体的には、サブマウント1をランプ加熱し、大気雰囲気中において300℃で発光ダイオード7と半田層5を接合し、室温まで急冷した。なお、テープ剥離テストは、一般に金属の密着強度測定に用いられる手法と同じであり、剥離を評価するために所定の粘着力を有するテープを使用した。
(比較例1)
実施例1と同様にして、半田層5に熱処理を施さない比較例1のサブマウントを製造した。テープ剥離テストを行なった後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。
半田層5の熱処理温度を150℃とした以外は実施例1と同様にして、比較例2のサブマウントを製造した。テープ剥離テストを行なった後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。
半田層5の熱処理温度を280℃に設定して半田層を溶解させた以外は、実施例1と同様にして、比較例3のサブマウントを製造した。テープ剥離テストを行なった後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。
上記測定で得た荷重及び変位から、接合強度τ(Pa)及びせん断歪γを、それぞれ、下記(1)及び(2)式で算出した。
熱抵抗は、作製したサブマウント1から任意の個数を抜き出し、発光ダイオード7を実装し、テクノローグ社で開発された熱抵抗測定法を用いて測定した。
図10は、発光ダイオード7を実装したサブマウント1aをステムに実装した様子を示す模式的な断面図である。図10に示すように、発光ダイオード7が半田接合されたサブマウント1aは、ステム22上に低温半田やAgペースト24を用いて接着することで搭載されており、任意の温度Tja1に保持した恒温槽内に設置される。図においては、発光ダイオード7への配線は示していない。この発光ダイオード7に発熱が無視できる定電流I、例えば1mAを通電し、このときの発光ダイオード7の順方向電圧Vfa1を測定する。次に、恒温槽の温度をTja2に変化させて維持し、定電流Iを通電したときの発光ダイオード7の順方向電圧Vfa2を測定する。恒温槽の温度を変化させて同様の測定を繰り返すことで、発光ダイオード7の周囲温度Tjと順方向電圧Vfの関係が得られる。
このように求めた発光ダイオード7の順方向電圧Vfの温度特性から、その温度依存性(ΔVf/ΔTj)を求める。
図12は、発光ダイオード7に直流定電流を流したときのタイムチャートを示し、縦軸は順方向電圧Vf(任意目盛)、横軸は時間(任意目盛)である。図12に示すように、発光ダイオード7には直流定電流をIf1,If2,If1の順に印加し、このときの順方向電圧をオシロスコープなどで測定する。電流をIf1からIf2、次に、If2からIf1に変化させるときには過渡電圧が生じる。このため、図示するように、If2の通電時間及びIf2からIf1に戻した際のIf1の通電時間は、それぞれ定常状態のVf2及びVf1値が得られるまで通電した。電流値をIf2からIf1に変化させた際に、測定電圧として、最初に電流値If1を通電したときの順方向電圧Vf1よりも低い値(Vf3)を経た後、一定時間経過後にVf1に安定する。発光ダイオード7の順方向電圧の最低値Vf3と、Vf1の差をΔVfとする。
予め求めておいた発光ダイオード7のVfの温度依存性(ΔVf/ΔTj)より、ΔTjを導出する。ここで、熱抵抗の定義である単位電力当りの温度上昇から、下記(4)式のように、発光ダイオード7の熱抵抗Rを求めることができる。
図13は、本発明のサブマウント1aを用いないで、発光ダイオード7をステム22に直接実装した様子を示す模式的な断面図である。図13に示すように、上記の熱抵抗測定を行ったサブマウント1aを搭載した同じステム22に低温半田やAgペースト等の導電ペースト24により発光ダイオード7を直接実装した。この場合の熱抵抗を上記と同じ方法で測定した。ステム22に直接発光ダイオード7を実装したときの熱抵抗とステム22にサブマウント1aを介して発光ダイオード7を実装したときの熱抵抗との差が、半田層5を含む本発明のサブマウント1aの熱抵抗となる。
半田層5に熱処理を施さないで比較例4のサブマウントを準備した。これ以外は実施例5と同様にしてテープ剥離テストを行なった後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。
厚さが0.033μmで組成がAu:Sn=5:1の原子比から成る層と厚さが0.117μmで組成がAu:Sn=1:1の原子比から成る層とを交互に20回繰り返し積層し、厚さが3μmの半田層を形成し、半田層に熱処理を施さないで比較例5のサブマウントを準備した。これ以外は実施例5と同様にしてテープ剥離テストを行なった後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。
厚さが0.92μmで組成がAu:Sn=50:50の原子比から成る層を成膜後、厚さ2.03μmで組成がSnのみから成る層を成膜し、合計厚さが2.95μmの半田層を形成した後、厚さが0.05μmなるAuのみからなる半田保護層を形成した。半田層および半田保護層全体での厚みを3μmとし、組成として原子比でAu:Sn=20:80、重量比で29.3:70.7とした。半田層に熱処理を施さないで比較例6のサブマウントを準備し、これ以外は実施例5と同様にしてテープ剥離テストを行なった後、剥離不良の無かったサブマウント1の半田層に300℃で発光ダイオード7を接合した。
図23は、実施例5及び比較例4,5,6に係るサブマウントの半田層5の300℃での表面光学写真像を示す図である。図23から明らかなように、実施例5のサブマウントでは、その中央部の半田層5が一様に溶解していて、半田層5の表面全体が均一に濡れていることが分かる。
一方、比較例4の場合には、周辺部などに局所的に凹凸が多い部分が観察され、半田層が均一に濡れていないことが分かる。比較例5の場合にも、半田層の表面全体に凹凸が多く、均一に濡れていないことが分かった。比較例4及び5において、濡れ性の悪い、すなわち、凹凸状の領域ができるのは、何れも溶解しているAu5 Sn相中に介在しているAuSnの影響であると考えられる。比較例6の場合には、溶解性はよいものの、半田層の表面全体が凹凸状となっていて、濡れ性が悪いことが分かった。
図24から明らかなように、実施例5,比較例4,5及び6の半田層5の接合強度は、それぞれ、35MPa、28MPa、23MPa、26MPaであり、実施例5のサブマウント1の半田層5の接合強度が最も高いことが判明した。
何れの場合も、サブマウント1のパターンを同じとし、このサブマウント1に自社製の発光ダイオード7をダイボンダー(ハイソル社製、MOA−1250α)を用い、300℃で、2.3Nの荷重を印加して、半田接合を行なった。サブマウント1の裏面側は、同時にTO−18ステム上に半田接合した。熱サイクル試験は、ETAC社製熱サイクル試験機(モデルNT510)を用い、1サイクルの条件を、150℃で15分、−65℃で15分とし、このサイクルを繰り返すことで行なった。発光ダイオード7には150mAの電流を連続通電した。
図27は、実施例5,比較例4,5及び6に係る熱サイクル試験での発光ダイオード7の発光出力の熱サイクル依存性を示す図である。図27において、縦軸は発光出力(mW)を示し、横軸は熱サイクル数(サイクル)を示している。なお通電電流は150mAである。図27から明らかなように、発光出力は、実施例5,比較例4,5及び6において何れの発光ダイオード7の場合も熱サイクルの増加に伴い減少しているが、実施例5が最もその低下が緩やかであることが分かる。これにより、実施例5の半田層5の熱抵抗が小さく、発光ダイオード7にかかる熱サイクル負荷が小さくなり、発光ダイオード7の信頼性が向上したことが分かる。
図28は、実施例5,比較例4,5及び6における発光ダイオード7と半田層5との半田接合強度の熱サイクル依存性を示す図である。縦軸は半田接合強度(MPa)を、横軸は熱サイクル数(サイクル)を示している。
図28から明らかなように、実施例5では、熱サイクル試験前及び50回経過したときの半田接合強度は、それぞれ、34.7MPa、35.1MPaであり、初期半田接合強度が維持されていることが分かる。
一方、比較例4において、熱サイクル試験前及び50回経過したときの半田接合強度は、それぞれ、27.7MPa、34.7MPaであり、初期半田接合強度が実施例5よりも低く、熱サイクルを負荷しないと半田接合強度が向上しない。比較例5では、熱サイクル試験前及び50回経過したときの半田接合強度は、それぞれ、23.1MPa、7.2MPaであり、初期半田接合強度が比較例4に比べて低く、しかも、熱サイクル数の増加に従い、加速度的に半田接合強度が低下し、熱サイクルが50回で初期半田接合強度の約30%に低下する。比較例6の場合には、熱サイクル試験前及び50回経過したときの半田接合強度は、それぞれ、25.8MPa、13.6MPaであり、初期半田接合強度が比較例4に比べて低く、しかも、熱サイクル数の増加に従い、加速度的に半田接合強度が低下し、熱サイクルが50回で初期半田接合強度の約50%に低下することが分かった。
これにより、実施例5の発光ダイオード7は、半田層5との初期半田接合強度が高く、熱サイクルを負荷しても変化が生じないことが判明した。
Claims (7)
- 基板上に形成される鉛を含まない半田層であって、
上記半田層が、上記基板側のAuSn相からなる下層とAu 5 Sn相からなる上層とから成り、
上記上層と上記下層が粒状に偏析した箇所を含まないことを特徴とする、半田層。 - 前記半田層の厚みが10μm以下であることを特徴とする、請求項1に記載の半田層。
- 基板と該基板上に形成される鉛を含まない半田層とを有するデバイス接合用基板であって、
上記半田層が、上記基板側のAuSn相からなる下層とAu 5 Sn相からなる上層とから成り、
上記上層と上記下層が粒状に偏析した箇所を含まないことを特徴とする、デバイス接合用基板。 - 前記半田層の厚みが10μm以下であることを特徴とする、請求項3に記載のデバイス接合用基板。
- 前記デバイス接合用基板の熱抵抗が、0.35K/W以下であることを特徴とする、請求項3又は4に記載のデバイス接合用基板。
- 基板と該基板上に形成される鉛を含まない半田層とを含むデバイス接合用基板の製造方法であって、
金と錫とを主成分とする共晶組成以外の組成のAu−Sn系合金を上記基板上に形成する工程と、
上記Au−Sn系合金を、Au 5 Sn相からなる上層とAuSn相からなる下層に分離し、上記上層と上記下層を、粒状に偏析した箇所を含まない半田層とする熱処理工程を含むことを特徴とする、デバイス接合用基板の製造方法。 - 前記熱処理工程の温度を、150℃より高い温度で、かつ、共晶反応温度未満とすることを特徴とする、請求項6に記載のデバイス接合用基板の製造方法。
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JP5526336B2 (ja) * | 2007-02-27 | 2014-06-18 | Dowaエレクトロニクス株式会社 | 半田層及びそれを用いたデバイス接合用基板並びにその製造方法 |
CN101840988A (zh) * | 2010-04-22 | 2010-09-22 | 傲迪特半导体(南京)有限公司 | 汽车前大灯发热pcb基台及其制作方法 |
JP2014239084A (ja) * | 2011-09-30 | 2014-12-18 | 三洋電機株式会社 | 回路装置 |
CN102403419B (zh) * | 2011-11-09 | 2013-08-21 | 东莞勤上光电股份有限公司 | 一种大功率led散热结构的制作工艺 |
EP2790212B1 (en) * | 2012-07-19 | 2015-09-16 | Technische Universität Ilmenau | Method of self-assembly of components on a substrate |
KR101373710B1 (ko) | 2012-12-12 | 2014-03-13 | (주)포인트엔지니어링 | 엘이디 금속기판 패키지 및 그 제조방법 |
US9674727B2 (en) * | 2014-01-17 | 2017-06-06 | Qualcomm Incorporated | Indication of cell mode and CSI feedback rules for cell on-off procedure |
US10721720B2 (en) | 2014-01-30 | 2020-07-21 | Qualcomm Incorporated | Cell On-Off procedure for dual connectivity |
WO2019043950A1 (ja) * | 2017-09-04 | 2019-03-07 | 三菱電機株式会社 | 半導体モジュール及び電力変換装置 |
US11551995B2 (en) * | 2017-10-26 | 2023-01-10 | Qorvo Us, Inc. | Substrate with embedded active thermoelectric cooler |
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US20090095513A1 (en) | 2009-04-16 |
EP2009971A4 (en) | 2011-01-12 |
EP2009971B1 (en) | 2015-01-07 |
WO2007119571A1 (ja) | 2007-10-25 |
EP2009971A1 (en) | 2008-12-31 |
US8516692B2 (en) | 2013-08-27 |
JPWO2007119571A1 (ja) | 2009-08-27 |
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