JP5119678B2 - 実装構造、接続部材の製造方法、および半導体装置 - Google Patents
実装構造、接続部材の製造方法、および半導体装置 Download PDFInfo
- Publication number
- JP5119678B2 JP5119678B2 JP2007039528A JP2007039528A JP5119678B2 JP 5119678 B2 JP5119678 B2 JP 5119678B2 JP 2007039528 A JP2007039528 A JP 2007039528A JP 2007039528 A JP2007039528 A JP 2007039528A JP 5119678 B2 JP5119678 B2 JP 5119678B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- insulating sheet
- cross
- circuit board
- connection member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
(付記1)
半導体素子の接続端子に接続部材を介して回路基板と電気的に接続する実装構造であって、
前記接続部材は、
柱状部を有する導電性突起を有し、
前記半導体素子の表面に水平な面で切った前記柱状部の断面の断面積は、前記半導体素子の接続端子の表面積より小さいことを特徴とする実装構造。
(付記2)
前記導電性突起は、更に、テーパー部、電極部を有し、
前記テーパー部は、前記柱状部に接する端部から前記電極部に接続する端部に向けて小さくなる前記半導体素子の表面に水平な面で切った断面の断面積を有することを特徴とする付記1に記載の実装構造。
(付記3)
前記導電性突起と前記半導体素子は半田により接続されていることを特徴とする付記1又は付記2に記載の実装構造。
(付記4)
前記導電性突起は、絶縁性シートに担持されていることを特徴とする付記1乃至付記3のいずれかに記載の実装構造。
(付記5)
前記半導体素子の表面に水平な面で切った前記柱状部の断面の断面積は、前記導電性部材の弾性率を前記半田の弾性率で除した値に反比例することを特徴とする付記1乃至付記4のいずれかに記載の実装構造。
(付記6)
前記絶縁性シートの熱膨張率は、前記半導体素子の熱膨張率と前記回路基板の熱膨張率との値の間にあることを特徴とする付記1乃至付記5のいずれかに記載の実装構造。
(付記7)
半導体素子の接続端子に接続部材を介して回路基板と電気的に接続する実装構造の製造方法であって、
前記接続部材を形成する工程と、
前記接続部材と前記回路基板とを接続する工程と、
前記接続部材と前記半導体素子とを接続する工程と、からなり、
前記接続部材を形成する工程は、
絶縁層上に導電層を有する部材の前記絶縁層を貫通する導電性突起を形成する工程と、
前記導電層をパターニングして電極部を形成する工程と、
を有することを特徴とする実装構造の製造方法。
(付記8)
半導体素子の接続端子に接続部材を介して回路基板と電気的に接続する実装構造を有する半導体装置であって、
前記接続部材は、
柱状部を有する導電性突起を有し、
前記半導体素子の表面に水平な面で切った前記柱状部の断面の断面積は、前記半導体素子の接続端子と前記柱状部との接触面積より小さいことを特徴とする半導体装置。
(付記9)
前記導電性突起は、更に、テーパー部、電極部を有し、
前記テーパー部は、前記柱状部に接する端部から前記電極部に接続する端部に向けて小さくなる前記半導体素子の表面に水平な面で切った断面の断面積を有することを特徴とする付記8に記載の半導体装置。
(付記10)
前記導電性突起と前記半導体素子は半田により接続されていることを特徴とする付記8又は付記9に記載の半導体装置。
(付記11)
前記導電性突起は、絶縁性シートに担持されていることを特徴とする付記8乃至付記10のいずれかに記載の半導体装置。
(付記12)
前記半導体素子の表面に水平な面で切った前記柱状部の断面の断面積は、前記導電性部材の弾性率を前記半田の弾性率で除した値に反比例することを特徴とする付記8乃至付記11のいずれかに記載の半導体装置。
(付記13)
前記絶縁性シートの熱膨張率は、前記半導体素子の熱膨張率と前記回路基板の熱膨張率との値の間にあることを特徴とする付記8乃至付記12のいずれかに記載の半導体装置。
(付記14)
半導体素子の接続端子に接続部材を介して回路基板と電気的に接続する実装構造を有する半導体装置の製法方法であって、
前記接続部材を形成する工程と、
前記接続部材と前記回路基板とを接続する工程と、
前記接続部材と前記半導体素子とを接続する工程と、からなり、
前記接続部材を形成する工程は、
絶縁層上に導電層を有する部材の前記絶縁層を貫通する導電性突起を形成する工程と、
前記導電層をパターニングして電極部を形成する工程と、
を有することを特徴とする半導体装置の製造方法。
1A テーパー孔
2 導電性突起
2A 柱状部
2B テーパー部
2C 電極部
2C´ 電極層
3 回路基板
3A 接続端子
4 半導体素子
4A 接続端子
5A 半田
5B 半田
6 めっきレジスト
6A 孔
10 接続部材
20 半導体装置
Claims (6)
- 半導体素子の接続端子に接続部材を介して回路基板と電気的に接続する実装構造であって、
第1の面の開口径が第2の面の開口径より大きいテーパ状の孔を有する絶縁性シートを有し、
前記接続部材は、前記絶縁性シートの前記テーパ状の孔に担持され、
前記接続部材は、前記絶縁性シートの前記第1の面の表面から突出し前記半導体素子の接続端子に接続する柱状部と、前記テーパ状の孔内に設けられ前記テーパの形状に一致する形状を有するテーパ部と、前記絶縁性シートの前記第2の面に設けられ前記回路基板に接する電極部とを有し、
前記絶縁性シートの前記第1の面で切った前記テーパ部の断面の断面積は、前記絶縁性シートの前記第2の面で切った前記テーパ部の断面の段面積より大きい
ことを特徴とする実装構造。 - 前記半導体素子の表面に水平な面で切った前記柱状部の断面の断面積は、前記半導体素子の接続端子の表面積より小さいことを特徴とする請求項1に記載の実装構造。
- 前記接続部材の柱状部と前記半導体素子は半田により接続されていることを特徴とする請求項1又は請求項2に記載の実装構造。
- 前記絶縁性シートの熱膨張率は、前記半導体素子の熱膨張率と前記回路基板の熱膨張率との値の間にあることを特徴とする請求項1乃至請求項3のいずれかに記載の実装構造。
- 絶縁性シートの第1面に導電層を形成する工程と、
前記絶縁性シートの第2面から前記導電層に達するテーパ状の孔を形成する工程と、
前記絶縁性シートの第2面にレジスト層を形成する工程と、
前記絶縁性シート状の前記テーパ状の孔の位置に対応する位置の前記レジスト層に貫通孔を形成する工程と、
前記テーパ状の孔及び前記貫通孔内に前記導電部材を形成する工程と、
前記導電層をパターニングして電極部を形成する工程と、
前記レジスト層を除去する工程と
を有することを特徴とする半導体素子と回路基板を接続するための接続部材の製造方法。 - 半導体素子と、
前記半導体素子の接続端子に接続部材を介して回路基板と電気的に接続する実装構造とを有する半導体装置であって、
前記実装構造は、
第1の面の開口径が第2の面の開口径より大きいテーパ状の孔を有する絶縁性シートを有し、
前記接続部材は、前記絶縁性シートの前記テーパ状の孔に担持され、
前記接続部材は、前記絶縁性シートの前記第1の面の表面から突出し前記半導体素子の接続端子に接続する柱状部と、前記テーパ状の孔内に設けられ前記テーパの形状に一致する形状を有するテーパ部と、前記絶縁性シートの前記第2の面に設けられ前記回路基板に接する電極部とを有し、
前記絶縁性シートの前記第1の面で切った前記テーパ部の断面の断面積は、前記絶縁性シートの前記第2の面で切った前記テーパ部の断面の段面積より大きい
ことを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007039528A JP5119678B2 (ja) | 2007-02-20 | 2007-02-20 | 実装構造、接続部材の製造方法、および半導体装置 |
US12/068,593 US7791197B2 (en) | 2007-02-20 | 2008-02-08 | Semiconductor device, connecting member, method for manufacturing a semiconductor device and method for manufacturing a connecting member |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007039528A JP5119678B2 (ja) | 2007-02-20 | 2007-02-20 | 実装構造、接続部材の製造方法、および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008205184A JP2008205184A (ja) | 2008-09-04 |
JP5119678B2 true JP5119678B2 (ja) | 2013-01-16 |
Family
ID=39705943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007039528A Expired - Fee Related JP5119678B2 (ja) | 2007-02-20 | 2007-02-20 | 実装構造、接続部材の製造方法、および半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7791197B2 (ja) |
JP (1) | JP5119678B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5644264B2 (ja) * | 2009-10-14 | 2014-12-24 | 富士通株式会社 | 半導体装置 |
US9161438B2 (en) | 2010-03-31 | 2015-10-13 | Taiyo Yuden Co., Ltd. | Stress buffer layer and method for producing same |
US20120055706A1 (en) * | 2010-09-03 | 2012-03-08 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and method of manufacturing the same |
JP6376761B2 (ja) * | 2014-01-31 | 2018-08-22 | 日本航空電子工業株式会社 | 中継部材及び中継部材の製造方法 |
JP7266508B2 (ja) * | 2019-10-21 | 2023-04-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3362370B2 (ja) | 1998-05-14 | 2003-01-07 | 住友ベークライト株式会社 | 導電性ボール配列シートおよび導電性ボール配列シート製造装置 |
JP2002151549A (ja) * | 2000-11-09 | 2002-05-24 | Nitto Denko Corp | 異方導電性フィルム |
JP3851517B2 (ja) * | 2001-04-18 | 2006-11-29 | カシオマイクロニクス株式会社 | 半導体装置およびその製造方法並びにその接合構造 |
JP3782753B2 (ja) * | 2001-04-25 | 2006-06-07 | 松下電器産業株式会社 | 半導体装置の製造方法および半導体装置 |
US6717066B2 (en) * | 2001-11-30 | 2004-04-06 | Intel Corporation | Electronic packages having multiple-zone interconnects and methods of manufacture |
US7097462B2 (en) * | 2004-06-29 | 2006-08-29 | Intel Corporation | Patch substrate for external connection |
-
2007
- 2007-02-20 JP JP2007039528A patent/JP5119678B2/ja not_active Expired - Fee Related
-
2008
- 2008-02-08 US US12/068,593 patent/US7791197B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7791197B2 (en) | 2010-09-07 |
US20080197492A1 (en) | 2008-08-21 |
JP2008205184A (ja) | 2008-09-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5500870B2 (ja) | 接続端子付き基板及び電子部品のソケット等 | |
JP4917874B2 (ja) | 積層型パッケージ及びその製造方法 | |
JP2011501410A (ja) | 頑健な多層配線要素および埋設された超小型電子素子とのアセンブリ | |
US9326372B2 (en) | Semiconductor device manufacturing method and semiconductor mounting substrate | |
JP5119678B2 (ja) | 実装構造、接続部材の製造方法、および半導体装置 | |
JP4265607B2 (ja) | 積層型電子部品および積層型電子部品の実装構造 | |
JP2017092094A (ja) | 電子装置、電子装置の製造方法及び電子機器 | |
JP2004266074A (ja) | 配線基板 | |
JP2015015302A (ja) | プリント配線板及びプリント配線板の製造方法 | |
TWI646639B (zh) | 半導體封裝 | |
JP2013030748A (ja) | 電子部品 | |
JP2005243761A (ja) | 中継基板、中継基板付き樹脂製基板 | |
JP5550102B2 (ja) | 電子部品 | |
JP2007173862A (ja) | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 | |
JP2011061179A (ja) | 印刷回路基板及び印刷回路基板の製造方法 | |
JP2008047710A (ja) | 半導体基板、半導体装置およびこれらの製造方法 | |
JP2006310543A (ja) | 配線基板及びその製造方法、半導体回路素子付き配線基板 | |
KR101148494B1 (ko) | 접속금속층을 갖는 반도체 장치 및 그 제조방법 | |
JP4802679B2 (ja) | 電子回路基板の実装方法 | |
JP2006186094A (ja) | 高信頼性プラスチック基板とその製造方法 | |
JP6920611B2 (ja) | 半導体装置及びその製造方法 | |
JP2008135483A (ja) | 電子部品内蔵基板およびその製造方法 | |
JP6127403B2 (ja) | 電子部品の実装方法及び中間シート | |
JP2005011908A (ja) | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 | |
JP2005039232A (ja) | 半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091110 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110804 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110816 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111014 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120403 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120604 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120703 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120822 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120925 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121008 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151102 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |