JP5092662B2 - Method for manufacturing printed wiring board - Google Patents

Method for manufacturing printed wiring board Download PDF

Info

Publication number
JP5092662B2
JP5092662B2 JP2007259464A JP2007259464A JP5092662B2 JP 5092662 B2 JP5092662 B2 JP 5092662B2 JP 2007259464 A JP2007259464 A JP 2007259464A JP 2007259464 A JP2007259464 A JP 2007259464A JP 5092662 B2 JP5092662 B2 JP 5092662B2
Authority
JP
Japan
Prior art keywords
layer
insulating resin
metal support
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007259464A
Other languages
Japanese (ja)
Other versions
JP2009088429A (en
Inventor
利幸 島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP2007259464A priority Critical patent/JP5092662B2/en
Publication of JP2009088429A publication Critical patent/JP2009088429A/en
Application granted granted Critical
Publication of JP5092662B2 publication Critical patent/JP5092662B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、半導体素子実装用の薄板厚の印刷配線板とその製造方法と半導体装置に関する。   The present invention relates to a thin printed wiring board for mounting a semiconductor element, a manufacturing method thereof, and a semiconductor device.

従来の半導体素子実装用の薄板厚の印刷配線板の製造方法として、特許文献１では、第１に、金属の支持層上にニッケル等の外部電極パッドを形成し、次に、支持層と外部電極パッドを覆う第１の絶縁樹脂層を重ね、次に、第１の絶縁樹脂層に外部電極パッドに達する第１のビアホール下穴を形成し、次に、金属の支持層を電極とする電解銅めっきにより、第１のビアホール下穴を銅で充填しビアホールを形成し第１の絶縁樹脂層の表面に銅の第１の配線パターンを形成する。第２に、第１の絶縁樹脂層と第１の配線パターンを覆う第２の絶縁樹脂層を重ね、次に、第２の絶縁樹脂層に外部電極パッドに達する第２のビアホール下穴を形成し、次に、金属の支持層を電極とする電解銅めっきにより、第２のビアホール下穴を銅で充填しビアホールを形成し第２の絶縁樹脂層の表面に銅の第２の配線パターンを形成する。第３に、第２の絶縁樹脂層と第２の配線パターンを覆う第３の絶縁樹脂層を重ね、次に、第３の絶縁樹脂層に外部電極パッドに達する第３のビアホール下穴を形成し、次に、金属の支持層を電極とする電解銅めっきにより、第３のビアホール下穴を銅で充填しビアホールを形成し第３の絶縁樹脂層の表面に銅の第３の配線パターンを形成する。第４に、第３の絶縁樹脂層と第３の配線パターンを覆うソルダーレジストを形成する。第５に、金属の支持層をエッチングで除去することで、全層間厚がきわめて薄く薄板厚の印刷配線板を製造していた。   As a conventional method for manufacturing a thin printed wiring board for mounting a semiconductor element, in Patent Document 1, first, an external electrode pad such as nickel is formed on a metal support layer, and then the support layer and the external A first insulating resin layer covering the electrode pad is overlaid, then a first via hole pilot hole reaching the external electrode pad is formed in the first insulating resin layer, and then an electrolysis using the metal support layer as an electrode By copper plating, the first via hole pilot hole is filled with copper to form a via hole, and a first wiring pattern of copper is formed on the surface of the first insulating resin layer. Second, the first insulating resin layer and the second insulating resin layer covering the first wiring pattern are overlapped, and then a second via hole pilot hole reaching the external electrode pad is formed in the second insulating resin layer. Then, by electrolytic copper plating using the metal support layer as an electrode, the second via hole pilot hole is filled with copper to form a via hole, and a second wiring pattern of copper is formed on the surface of the second insulating resin layer. Form. Third, the second insulating resin layer and the third insulating resin layer covering the second wiring pattern are overlapped, and then a third via hole pilot hole reaching the external electrode pad is formed in the third insulating resin layer. Next, by electrolytic copper plating using the metal support layer as an electrode, the third via hole pilot hole is filled with copper to form a via hole, and a third wiring pattern of copper is formed on the surface of the third insulating resin layer. Form. Fourth, a solder resist that covers the third insulating resin layer and the third wiring pattern is formed. Fifth, by removing the metal support layer by etching, a printed wiring board having a very thin total interlayer thickness was manufactured.

以下に公知文献を記す。
特開２００１−１７７０１０号公報 The known literature is described below.
JP 2001-177010 A

しかし、特許文献１の印刷配線板の製造方法では、製造工程の一番最後に支持層を除去するまでは配線パターンとビアホールの全導体が支持層と電気接続しているため、配線パターンとビアホールの断線や短絡を電気検査で発見することができない問題があった。すなわち、支持層を除去した際に初めて配線パターンの回路が支持層から独立するので、次に、電気検査装置で配線パターンとビアホールの不具合を発見していた。こうして、製造工程の初期の段階で発生した配線パターンあるいはビアホールの断線や短絡の不具合を最後の工程で発見するため、印刷配線板の製造歩留まりが悪い問題があった。また、この製造方法で層数が多い印刷配線板を製造する場合は、印刷配線板の全層を支持層の片面に形成するため、製造工期が長くなる欠点があった。   However, in the printed wiring board manufacturing method of Patent Document 1, all the conductors in the wiring pattern and the via hole are electrically connected to the supporting layer until the supporting layer is removed at the very end of the manufacturing process. There was a problem that the disconnection or short circuit could not be found by electrical inspection. That is, since the circuit of the wiring pattern becomes independent from the supporting layer for the first time when the supporting layer is removed, the defect of the wiring pattern and the via hole has been discovered by an electrical inspection apparatus. Thus, the wiring pattern or via hole disconnection or short-circuit defect that occurred in the initial stage of the manufacturing process is discovered in the last process, and there has been a problem that the manufacturing yield of the printed wiring board is poor. Further, when a printed wiring board having a large number of layers is produced by this production method, since all the layers of the printed wiring board are formed on one side of the support layer, there is a drawback that the production period is long.

また、特許文献１の印刷配線板の製造方法では、両面にソルダーレジストを印刷する場合は、基板の片面にソルダーレジストを形成した後に支持層を除去し、露出した面にソルダーレジストを形成すると、片面にソルダーレジストを形成するアンバランスな応力により、印刷配線板が反る問題があった。一方、金属の支持層をエッチングで除去した後に、基板の両面にソルダーレジストを形成する場合も、ソルダーレジストを硬化させる際に加える加熱処理により印刷配線板が反る問題があった。鋭意研究の結果、この問題の原因は、片面形成した印刷配線板には、片面に偏った応力が残留するため、加熱処理により、上下面でアンバランスな応力があらわれ、その応力により印刷配線板が反る知見を得た。   Moreover, in the manufacturing method of the printed wiring board of patent document 1, when printing a solder resist on both surfaces, after forming the solder resist on one side of the substrate, removing the support layer, and forming the solder resist on the exposed surface, There was a problem that the printed wiring board warps due to unbalanced stress that forms the solder resist on one side. On the other hand, even when the solder resist is formed on both surfaces of the substrate after the metal support layer is removed by etching, there is a problem that the printed wiring board is warped by the heat treatment applied when the solder resist is cured. As a result of diligent research, the cause of this problem is that the printed wiring board that is formed on one side has stress that is biased on one side, so that unbalanced stress appears on the top and bottom surfaces due to heat treatment. Obtained warping knowledge.

更に、特許文献１の製造方法では、エッチングにより金属の支持層を除去する際に、支
持層に接していた外部電極パッドがエッチング液に曝されると、外部電極パッドの絶縁樹脂層の隙間から外部電極パッドに電気接続する配線パターンの位置までエッチング液が侵入し導体面が腐食されることがある問題があった。また、その外部電極パッドを金めっきで形成した場合、その金めっき上にソルダーレジストを形成すると、金めっきとソルダーレジストとの密着が悪くなり、ソルダーレジスト剥がれ不良を発生する問題があった。 Furthermore, in the manufacturing method of Patent Document 1, when the external electrode pad in contact with the support layer is exposed to the etching solution when the metal support layer is removed by etching, the gap is formed between the insulating resin layers of the external electrode pad. There has been a problem that the etching solution may invade to the position of the wiring pattern electrically connected to the external electrode pad and the conductor surface may be corroded. Further, when the external electrode pad is formed by gold plating, if a solder resist is formed on the gold plating, there is a problem that the adhesion between the gold plating and the solder resist is deteriorated and the solder resist is peeled off.

本発明の課題は、半導体素子実装用の薄板厚の印刷配線板においてこれらの問題を解決することにある、すなわち、印刷配線板の製造工期を短縮することを課題とし、また、薄板厚の印刷配線板の反りを低減し、印刷配線板のソルダーレジスト剥がれ不良を低減することを課題とする。   An object of the present invention is to solve these problems in a thin printed wiring board for mounting semiconductor elements, that is, to shorten the manufacturing period of the printed wiring board, and to print a thin board thickness. It is an object to reduce the warpage of the wiring board and to reduce the solder resist peeling failure of the printed wiring board.

本発明は、この課題を解決するために、厚さ０．０５ｍｍから０．２ｍｍのプリプレグから成る接着剤層の両面に前記接着剤層より小さい金属剥離層を該金属剥離層の粗面を前記接着剤層側に向けて設置し、前記金属剥離層の外側の両面に前記金属剥離層よりも大きい金属支持層を重ねて加熱・加圧することで両面の前記金属支持層の外周接着部分を前記接着剤層で接着した支持体を形成する第１の工程と、前記支持体の両面の前記金属支持層の外側に第１の絶縁樹脂層と第１の配線パターンを形成する第２の工程と、両面の前記第１の配線パターンの外側に絶縁樹脂層とビアホールと配線パターンとその外側の絶縁樹脂層を逐次形成する第３の工程と、前記外周接着部分を切断することで前記支持体から前記金属支持層付き基板を分離する第４の工程と、前記金属支持層付き基板から前記金属支持層を除去することで印刷配線板中間体を形成する第５の工程と、前記印刷配線板中間体の両面にビアホールと配線パターンを形成する第６の工程を有することを特徴とする印刷配線板の製造方法である。 In order to solve this problem, the present invention provides a metal release layer smaller than the adhesive layer on both sides of an adhesive layer made of a prepreg having a thickness of 0.05 mm to 0.2 mm, and a rough surface of the metal release layer. Installed toward the adhesive layer side, the metal support layer larger than the metal release layer is overlapped on both sides of the metal release layer, and heated and pressed to attach the outer peripheral adhesive portions of the metal support layer on both sides A first step of forming a support bonded with an adhesive layer; a second step of forming a first insulating resin layer and a first wiring pattern outside the metal support layer on both sides of the support; A third step of successively forming an insulating resin layer, a via hole, a wiring pattern, and an insulating resin layer outside the first wiring pattern on both sides of the first wiring pattern; and cutting the outer peripheral adhesive portion from the support. Separating the substrate with the metal support layer; Step 5, forming a printed wiring board intermediate by removing the metal supporting layer from the substrate with the metal supporting layer, and forming via holes and wiring patterns on both sides of the printed wiring board intermediate A printed wiring board manufacturing method characterized by comprising a sixth step.

また、本発明は、金属剥離体の両面に前記金属剥離体より小さい金属支持層を、粗面を外側に向けて重ねて設置し、前記金属支持層の外側の両面に前記金属支持層より大きいプリプレグから成る第１の絶縁樹脂層を重ねて加熱・加圧することで両面の前記第１の絶縁樹脂層の外周接着部分を前記金属剥離体に接着させる第１の工程と、前記第１の絶縁樹脂層の外側に第１の配線パターンを形成する第２の工程と、両面の前記第１の配線パターンの外側に絶縁樹脂層とビアホールと配線パターンとその外側の絶縁樹脂層を逐次形成する第３の工程と、前記外周接着部分を切断することで前記金属剥離体から前記金属支持層付き基板を分離する第４の工程と、前記金属支持層付き基板から前記金属支持層を除去した印刷配線板中間体を形成する第５の工程と、前記印刷配線板中間体の両面にビアホールと配線パターンを形成する第６の工程を有することを特徴とする印刷配線板の製造方法である。 In the present invention, a metal support layer smaller than the metal release body is disposed on both surfaces of the metal release body, with the rough surface facing outward, and larger than the metal support layer on both outer surfaces of the metal support layer. A first step of adhering the outer peripheral adhesive portions of the first insulating resin layers on both sides to the metal peeler by superposing and heating and pressurizing a first insulating resin layer made of a prepreg; and the first insulation A second step of forming a first wiring pattern outside the resin layer; and a step of sequentially forming an insulating resin layer, a via hole, a wiring pattern, and an insulating resin layer outside the first wiring pattern on both sides of the first wiring pattern. 3 and the 4th process which isolate | separates the said board | substrate with a metal support layer from the said metal peeling body by cut | disconnecting the said outer periphery adhesion | attachment part, The printed wiring which removed the said metal support layer from the said board | substrate with a metal support layer Forming the intermediate plate And step is a method of manufacturing a printed wiring board characterized by having a sixth step of forming a via hole and wiring pattern on both surfaces of the printed circuit board intermediate.

また、本発明は、粗面を外側に向けて重ねた第１の金属支持層と第２の金属支持層の外側の両面に、前記第１の金属支持層及び第２の金属支持層より大きいプリプレグから成る第１の絶縁樹脂層を重ねて加熱・加圧することで両面の前記金属支持層の外周より外側で両面の前記第１の絶縁樹脂層が接着した外周接着部分を形成した支持体を形成する第１の工程と、前記第１の絶縁樹脂層の外側に第１の配線パターンを形成する第２の工程と、両面の前記第１の配線パターンの外側に絶縁樹脂層とビアホールと配線パターンとその外側の絶縁樹脂層を逐次形成する第３の工程と、前記外周接着部分を切断することで前記第１の金属支持層を有する金属支持層付き基板と前記第２の金属支持層を有する金属支持層付き基板を分離する第４の工程と、前記金属支持層付き基板から前記金属支持層を除去した印刷配線板中間体を形成する第５の工程と、前記印刷配線板中間体の両面にビアホールと配線パターンを形成する第６の工程を有することを特徴とする印刷配線板の製造方法である。 Further, the present invention is larger than the first metal support layer and the second metal support layer on both the outer surfaces of the first metal support layer and the second metal support layer which are laminated with the rough surfaces facing outward. A support body in which a first insulating resin layer made of a prepreg is stacked and heated and pressed to form an outer peripheral adhesion portion where the first insulating resin layers on both sides are bonded to the outside of the outer periphery of the metal support layers on both sides. A first step of forming, a second step of forming a first wiring pattern outside the first insulating resin layer, an insulating resin layer, a via hole, and a wiring outside the first wiring pattern on both sides A third step of sequentially forming a pattern and an insulating resin layer outside the pattern; and a substrate with a metal support layer having the first metal support layer and the second metal support layer by cutting the outer peripheral adhesive portion. A fourth step of separating the substrate with the metal support layer, Having a sixth step of forming a fifth step of forming a printed wiring board intermediate from the metal supporting layer with the substrate to remove the metal supporting layer, a via hole and wiring pattern on both surfaces of the printed circuit board intermediate This is a method for manufacturing a printed wiring board.

また、本発明は、上記第１の絶縁樹脂層を、補強材入り樹脂プリプレグを用いて形成することを特徴とする上記の印刷配線板の製造方法である。   The present invention is also the above-described printed wiring board manufacturing method, wherein the first insulating resin layer is formed using a resin prepreg with a reinforcing material.

また、本発明は、上記第６の工程の次に、上記印刷配線板中間体の両面の外側に絶縁樹脂層とビアホールと配線パターンを逐次形成する第７の工程を有することを特徴とする上記の印刷配線板の製造方法である。   In addition, the present invention has a seventh step of sequentially forming an insulating resin layer, a via hole, and a wiring pattern on both outer sides of the printed wiring board intermediate after the sixth step. It is a manufacturing method of this printed wiring board.

また、本発明は、上記第７の工程において、最外層の絶縁樹脂層を補強材無しの絶縁樹脂層で形成することを特徴とする上記の印刷配線板の製造方法である。   The present invention is also the above-described printed wiring board manufacturing method, wherein, in the seventh step, the outermost insulating resin layer is formed of an insulating resin layer without a reinforcing material.

また、本発明は、上記印刷配線板の最外層の外層配線パターンの外側に外部電極パッド用開口部を有するソルダーレジストを形成する第８の工程を有することを特徴とする上記
の印刷配線板の製造方法である。 Further, the present invention includes an eighth step of forming a solder resist having an opening for an external electrode pad on the outer side of the outermost wiring pattern of the outermost layer of the printed wiring board. It is a manufacturing method.

また、本発明は、上記ソルダーレジストの上記外部電極パッド用開口部に露出した上記外層配線パターンに固相点が２４０℃以上で２５０℃以下のはんだで外部接続端子をはんだ付けする第９の工程を有することを特徴とする上記の印刷配線板の製造方法である。   Further, the present invention provides a ninth step of soldering an external connection terminal to the outer layer wiring pattern exposed at the external electrode pad opening of the solder resist with a solder having a solid phase point of 240 ° C. or higher and 250 ° C. or lower. It is a manufacturing method of said printed wiring board characterized by having.

本発明は、支持体の両面に同時に印刷配線板中間体を逐次形成するため製造効率が良い。また、支持層を除去した後の印刷配線板中間体も、その両面に絶縁樹脂層と配線パターンを逐次形成して２層ずつ形成していくので、支持層の片面に逐次形成していく従来工法に比べ逐次形成の工程数を半減させ、製造工期を短縮できる効果がある。また、本発明は、印刷配線板中間体の各絶縁樹脂層の厚さが薄い場合も、それらの絶縁樹脂層を複数層重ねた適度の厚さの印刷配線板中間体を、支持体の両面の支持層上に形成し、次に、支持体から両面の２組の支持層付き基板を分離し、次に、支持層を除去した印刷配線板中間体を取り扱うので、その印刷配線板中間体は厚さが適度であるため取り扱いが容易である。そのため、その印刷配線板中間体を電気検査装置で検査することができ、それにより配線パターンとビアホールの欠陥を検査でき、不良品を早期に除外できるので、印刷配線板の歩留まりを向上させる効果がある。   Since the present invention sequentially forms the printed wiring board intermediate on both sides of the support at the same time, the production efficiency is high. In addition, the printed wiring board intermediate after the support layer is removed is also formed in two layers by sequentially forming the insulating resin layer and the wiring pattern on both sides, so that it is sequentially formed on one side of the support layer. Compared to the construction method, the number of sequential forming steps can be halved and the production period can be shortened. In addition, the present invention provides a printed wiring board intermediate having an appropriate thickness obtained by stacking a plurality of insulating resin layers on both sides of the support even when each insulating resin layer of the printed wiring board intermediate is thin. Then, the printed wiring board intermediate is handled by handling the printed wiring board intermediate from which the two layers of the supporting layers on both sides are separated from the support, and then the supporting layer is removed. Is easy to handle due to its moderate thickness. Therefore, it is possible to inspect the printed wiring board intermediate with an electrical inspection device, thereby inspecting defects in the wiring pattern and via holes, and eliminating defective products at an early stage, thereby improving the yield of the printed wiring board. is there.

また、本発明の印刷配線板は、印刷配線板中間体の両面の絶縁樹脂層にビアホールと第４の配線パターンを形成し、また、その両面に第４の絶縁樹脂層を重ねてその基板の両面にビアホールと第４の配線パターンを形成することで印刷配線板中間体に上下対称な層構成にビアホールと配線パターンを逐次形成し、更に外側の絶縁樹脂層とビアホールと配線パターンを逐次形成することができる。それにより、板厚がきわめて薄い印刷配線板でありながら、その印刷配線板を加熱処理しても印刷配線板が反る問題が少ない良い品質の印刷配線板が得られる効果がある。特に、従来の基板の両面にソルダーレジストを印刷する際の加熱処理による印刷配線板の反りを改善できる効果がある。   In the printed wiring board of the present invention, via holes and fourth wiring patterns are formed on the insulating resin layers on both sides of the printed wiring board intermediate, and the fourth insulating resin layer is overlapped on both sides of the printed wiring board intermediate body. By forming via holes and fourth wiring patterns on both sides, via holes and wiring patterns are sequentially formed in a vertically symmetrical layer structure on the printed wiring board intermediate, and further, an outer insulating resin layer, via holes and wiring patterns are sequentially formed. be able to. Thereby, although the printed wiring board is extremely thin, there is an effect that a printed wiring board of good quality can be obtained with few problems of warping of the printed wiring board even if the printed wiring board is heat-treated. In particular, there is an effect that the warp of the printed wiring board due to the heat treatment when printing the solder resist on both surfaces of the conventional substrate can be improved.

また、本発明は、配線パターンを両面の絶縁樹脂層で被覆して配線パターンが露出しない印刷配線板中間体から支持層を除去するので、支持層の除去の際の薬液による処理によって配線パターンが損傷することが無く、また、その後の製造工程でも印刷配線板中間体の配線パターンが損傷することが無いので、印刷配線板の製造歩留まりを向上できる効果がある。更に、本発明は、外層配線パターン上にソルダーレジストを形成した後に、その外部電極パッド用開口部に露出した外層配線パターンに外部電極パッド用の金めっきを加えるので、ソルダーレジストの外層配線パターンへの密着性を損なわずソルダーレジスト剥がれ不良を低減できる効果がある。   Further, the present invention removes the support layer from the printed wiring board intermediate where the wiring pattern is covered with the insulating resin layers on both sides and the wiring pattern is not exposed, so that the wiring pattern is formed by treatment with a chemical when removing the supporting layer. There is no damage, and the wiring pattern of the printed wiring board intermediate is not damaged in the subsequent manufacturing process, so that it is possible to improve the manufacturing yield of the printed wiring board. Further, in the present invention, after forming the solder resist on the outer layer wiring pattern, gold plating for the external electrode pad is added to the outer layer wiring pattern exposed in the opening for the outer electrode pad. There is an effect that the solder resist peeling failure can be reduced without impairing the adhesion of the solder.

＜第１の実施形態＞
以下、本発明の第１の実施形態について図１から図９に基づき説明する。本実施形態は、接着剤層１ｂの外側の両面にそれより小さい金属剥離層１ａを設置し、その外側の両面に金属剥離層１ａより大きい金属支持層１を重ねて加熱・加圧することで両面の金属支持層１の外周接着部分１ｄを接着剤層１ｂで接着した支持体１ｃを形成する第１の工程を有する。次に、その支持体１ｃの両面の外側に第１の絶縁樹脂層２を重ね、その第１の絶縁樹脂層２の外側の面に第１の配線パターン６を形成する第２の工程を有する。その第１の配線パターン６の外側に絶縁樹脂層２−２を重ね、その絶縁樹脂層２−２内に第１の配線パターン６に接続するビアホール７−２を形成し、絶縁樹脂層２−２の面上に配線パターン６−２を金属めっきで形成する。このように支持体１ｃを中心にする基板の両面の配線パターンの外側に絶縁樹脂層とビアホールと配線パターンとその外側の絶縁樹脂層を逐次形成する処理を繰り返すことで第２の絶縁樹脂層群を形成する第３の工程を有する。 <First Embodiment>
A first embodiment of the present invention will be described below with reference to FIGS. In this embodiment, a metal release layer 1a smaller than the metal release layer 1a is disposed on both sides of the adhesive layer 1b, and a metal support layer 1 larger than the metal release layer 1a is placed on both sides of the adhesive layer 1b and heated and pressed. A first step of forming a support 1c in which the outer peripheral adhesion portion 1d of the metal support layer 1 is bonded with the adhesive layer 1b. Next, there is a second step in which the first insulating resin layer 2 is overlapped on both outer sides of the support 1c, and the first wiring pattern 6 is formed on the outer surface of the first insulating resin layer 2. . The insulating resin layer 2-2 is overlaid on the outside of the first wiring pattern 6, and a via hole 7-2 connected to the first wiring pattern 6 is formed in the insulating resin layer 2-2. A wiring pattern 6-2 is formed on the surface 2 by metal plating. In this way, the second insulating resin layer group is formed by repeating the process of sequentially forming the insulating resin layer, the via hole, the wiring pattern, and the insulating resin layer outside the wiring pattern on both sides of the substrate centering on the support 1c. A third step of forming

次に、外周接着部分１ｄを切断することで、支持体１ｃ中の上側の金属剥離層１ａを上側の金属支持層１以上の部分から剥離し、また、下側の金属剥離層１ａを下側の金属支持層１以下の部分から剥離することで、支持体１ｃから２組の金属支持層１付き基板を分離する第４の工程を有する。次に、それらの基板から金属支持層１を除去した印刷配線板中間体８を製造する第５の工程を有し、その印刷配線板中間体８の両面にビアホール下穴を形成して金属めっきでビアホール７−１と７−４と配線パターン６−１と６−４を形成する第６の工程を有する。次に、この印刷配線板中間体８の外側の両面に絶縁樹脂層２−５と２−６を重ね、ビアホール７−５と７−６と配線パターン６−５と６−６を逐次形成する処理を繰り返すことで第３の絶縁樹脂層群を形成する第７の工程を有する。次に、最外層の両面の配線パターン６−５と６−６の外側に、外部電極パッド用開口部１０を有するソルダーレジスト９を形成する第８の工程を有する印刷配線板の製造方法である。   Next, by cutting the outer peripheral adhesive portion 1d, the upper metal release layer 1a in the support 1c is released from the portion above the upper metal support layer 1, and the lower metal release layer 1a is It has the 4th process of isolate | separating two sets of board | substrates with the metal support layer 1 from the support body 1c by peeling from the part below the metal support layer 1 of this. Next, it has the 5th process which manufactures the printed wiring board intermediate body 8 which removed the metal support layer 1 from those board | substrates, forms a via-hole pilot hole in both surfaces of the printed wiring board intermediate body 8, and is metal-plated. And a sixth step of forming via holes 7-1 and 7-4 and wiring patterns 6-1 and 6-4. Next, insulating resin layers 2-5 and 2-6 are overlapped on both outer surfaces of the printed wiring board intermediate 8 to sequentially form via holes 7-5 and 7-6 and wiring patterns 6-5 and 6-6. There is a seventh step of forming the third insulating resin layer group by repeating the processing. Next, the printed wiring board manufacturing method includes an eighth step of forming the solder resist 9 having the external electrode pad openings 10 on the outer sides of the wiring patterns 6-5 and 6-6 on both surfaces of the outermost layer. .

（製造方法）
以下、本実施形態の製造方法を図１から図９に基づき詳細に説明する。
（工程１）
図１（ａ）のように、金属支持層１として金属板を、例えば１２５μｍの銅板を、粗化処理する。粗化処理は、過水硫酸系のソフトエッチング処理、または、研磨材によるバフ研磨やサンドブラスト処理、あるいは、酸化還元処理による黒化処理、ＣＺ処理でも良い。次に、金属支持層１、金属箔の金属剥離層１ａ、接着剤層１ｂ、金属箔の金属剥離層１ａ、金属支持層１の順で積み上げ、図１（ｂ）のように、積層プレスで熱圧着して一体化させた支持体１ｃを製造する。金属剥離層１ａは、例えば厚さが１２μｍの銅箔で、金属支持層１の寸法より３０ｍｍから６０ｍｍ程度小さいものを用いる。また、金属剥離層１ａの銅箔の粗面（マット面）を接着剤層１ｂ側に向ける。接着剤層１ｂは、厚さ５０μｍから２００μｍのガラス繊維入りエポキシ樹脂材やガラス繊維入りポリイミド樹脂材等のガラス繊維入り絶縁樹脂のプリプレグを用いる。積層プレスの加熱・加圧処理により、プリプレグの接着剤層１ｂの樹脂が溶融して上下の金属支持層１の外周接着部分１ｄを接着し、また、上下の金属剥離層１ａの内側の全面を接着剤層１ｂに接着する。金属剥離層１ａの外側の全面は接着せずに金属支持層１に接した状態で保持する。 (Production method)
Hereinafter, the manufacturing method of this embodiment is demonstrated in detail based on FIGS.
(Process 1)
As shown in FIG. 1A, a metal plate, for example, a 125 μm copper plate, is roughened as the metal support layer 1. The roughening treatment may be a perhydrosulfuric acid based soft etching treatment, a buffing or sandblasting treatment with an abrasive, or a blackening treatment or redox treatment by oxidation-reduction treatment. Next, the metal support layer 1, the metal release layer 1a of the metal foil, the adhesive layer 1b, the metal release layer 1a of the metal foil, and the metal support layer 1 are stacked in this order, as shown in FIG. The support 1c integrated by thermocompression bonding is manufactured. The metal peeling layer 1 a is, for example, a copper foil having a thickness of 12 μm, and is 30 mm to 60 mm smaller than the size of the metal support layer 1. Moreover, the rough surface (matte surface) of the copper foil of the metal peeling layer 1a is directed to the adhesive layer 1b side. For the adhesive layer 1b, a prepreg of an insulating resin containing glass fibers such as an epoxy resin material containing glass fibers or a polyimide resin material containing glass fibers having a thickness of 50 μm to 200 μm is used. By the heating / pressurizing treatment of the laminating press, the resin of the adhesive layer 1b of the prepreg is melted to adhere the outer peripheral adhesion portions 1d of the upper and lower metal support layers 1, and the entire inner surfaces of the upper and lower metal peeling layers 1a are adhered. Adhere to the adhesive layer 1b. The entire outer surface of the metal release layer 1a is held in contact with the metal support layer 1 without being bonded.

この工程１では、プリプレグを硬化させた接着剤層１ｂの１層で上下の金属支持層１の外周接着部分１ｄを接着するので、金属支持層１の接着作業を簡単にし、製造コストを低減する効果がある。また、この接着剤層１ｂは、ガラス繊維入り絶縁樹脂のプリプレグを用いたので、固化後の層面方向の熱膨張率を金属の金属支持層１の熱膨張率とほぼ同じにし差を少なくすることができる。これにより、接着剤層１ｂと金属支持層１の間で熱応力を少なくでき、製造する印刷配線の品質を良くできる効果がある。更に、接着剤層１ｂの厚さを５０μｍから２００μｍ程度の薄い層に形成することで、その熱膨張の影響を小さくし、印刷配線板の製造工程中の寸法挙動を安定させる効果がある。更に、この接着剤層１ｂはガラス繊維で強化されているため、硬化した後の剛性が大きく強度が強いので、薄い金属支持層１と薄い金属剥離層１ａと薄い接着剤層１ｂで構成する薄い支持体１ｃにおいても、接着剤層１ｂが金属支持層１の強度不足を補い剛性の大きい支持体１ｃを得ることができる効果がある。これにより、印刷配線板の製造工程中の寸法挙動を安定させることができる効果がある。   In this step 1, since the outer peripheral bonding portion 1d of the upper and lower metal support layers 1 is bonded by one layer of the adhesive layer 1b obtained by curing the prepreg, the bonding work of the metal support layer 1 is simplified and the manufacturing cost is reduced. effective. Further, since this adhesive layer 1b uses a prepreg of an insulating resin containing glass fiber, the thermal expansion coefficient in the layer surface direction after solidification is made substantially the same as the thermal expansion coefficient of the metal support layer 1, and the difference is reduced. Can do. Thereby, there is an effect that thermal stress can be reduced between the adhesive layer 1b and the metal support layer 1, and the quality of the printed wiring to be manufactured can be improved. Furthermore, by forming the adhesive layer 1b in a thin layer of about 50 μm to 200 μm, there is an effect of reducing the influence of thermal expansion and stabilizing the dimensional behavior during the manufacturing process of the printed wiring board. Furthermore, since the adhesive layer 1b is reinforced with glass fiber, the rigidity after curing is high and the strength is strong. Therefore, the adhesive layer 1b is a thin metal support layer 1, a thin metal release layer 1a, and a thin adhesive layer 1b. The support 1c also has an effect that the adhesive layer 1b can compensate for the insufficient strength of the metal support layer 1 and obtain a support 1c having high rigidity. Thereby, there exists an effect which can stabilize the dimensional behavior in the manufacturing process of a printed wiring board.

（変形例１）
工程１の変形例として、金属箔を金属支持層１とする。例えば１２μｍの銅箔を用いる。この金属支持層１は、その金属箔の粗面（マット面）を支持体１ｃの外側に向けて金属剥離層１ａの外側に重ねて、積層プレスで加熱・加圧することで支持体１ｃの中心の接着剤層１ｂの樹脂を溶融させて上下の金属箔の金属支持層１の外周接着部分１ｄを接着し、また、金属剥離層１ａを接着剤層１ｂに接着する。変形例１は、接着剤層１ｂがガラス繊維で強化されているため、硬化した後の剛性が大きく強度が強いので、金属支持層１が金属箔を用いて薄くされ、金属剥離層１ａも金属箔で薄い支持体１ｃにおいても、ガラス繊維で補強されたプリプレグが硬化された接着剤層１ｂが金属支持層１の強度不足を補い剛性を大きくする為、製造工程中の扱いが容易な支持体１ｃが得られ、これによる印刷配線板の製造を容易にすることができる。 (Modification 1)
As a modification of the step 1, the metal foil is a metal support layer 1. For example, a 12 μm copper foil is used. The metal support layer 1 has a rough surface (matte surface) of the metal foil facing the outside of the support 1c and is superimposed on the outside of the metal release layer 1a, and is heated and pressed with a laminating press to center the support 1c. The resin of the adhesive layer 1b is melted to adhere the outer peripheral adhesion portions 1d of the metal support layers 1 of the upper and lower metal foils, and the metal release layer 1a is adhered to the adhesive layer 1b. In the modified example 1, since the adhesive layer 1b is reinforced with glass fiber, the rigidity after curing is high and the strength is strong. Therefore, the metal support layer 1 is thinned using a metal foil, and the metal peeling layer 1a is also a metal. Even in the thin support 1c made of foil, the adhesive layer 1b obtained by curing the prepreg reinforced with glass fiber compensates for the insufficient strength of the metal support layer 1 and increases the rigidity, so that the support is easy to handle during the manufacturing process. 1c is obtained, which can facilitate the production of the printed wiring board.

（工程２）
次に、図１（ｃ）のように、支持体１ｃの両面の金属支持層１の両面に第１の絶縁樹脂層２をロールラミネートで熱圧着させる。例えば厚さ４５μｍのエポキシ樹脂あるいはガラス繊維で補強されたプリプレグをロールラミネートする。ここで、支持体１ｃの両面に上下対称に第１の絶縁樹脂層２を形成するため、製造中の反りが発生しない効果がある。以降の工程でも、同様に、支持体１ｃを中心にして上下対称に各層を逐次形成することで、製造中の反りが発生しない効果がある。
（変形例２）
工程２の変形例として、第１の絶縁樹脂層２として、金属支持層１上にガラス繊維やガラスフレークやフィラーなどの補強材入り樹脂プリプレグを重ね、その上に厚さ１２μｍの銅箔を重ね合わせ、積層プレスで熱圧着させることで、銅箔付きの第１の絶縁樹脂層２を金属支持層１に接着して形成する。次に、その外側の銅箔を塩化第二鉄水溶液などのエッチング液で全面エッチングして第１の絶縁樹脂層２の表面を露出させる。この第１の絶縁樹脂層２はガラス繊維で強化されているため、硬化した後の剛性が大きく強度が強いので、薄い金属支持層１と薄い金属剥離層１ａと薄い接着剤層１ｂで構成する薄い支持体１ｃにおいても、第１の絶縁樹脂層２が支持体１ｃの強度不足を更に補い、剛性の大きい基板を得ることができる効果がある。これにより、印刷配線板の製造工程中の寸法挙動を安定させることができる効果がある。 (Process 2)
Next, as shown in FIG. 1C, the first insulating resin layer 2 is thermocompression-bonded on both sides of the metal support layer 1 on both sides of the support 1c by roll lamination. For example, a prepreg reinforced with a 45 μm thick epoxy resin or glass fiber is roll laminated. Here, since the first insulating resin layer 2 is formed symmetrically on both surfaces of the support 1c, there is an effect that warpage during manufacturing does not occur. In the subsequent steps, similarly, each layer is sequentially formed symmetrically with the support 1c as the center, thereby providing an effect that warpage during manufacturing does not occur.
(Modification 2)
As a modified example of the step 2, as the first insulating resin layer 2, a resin prepreg containing a reinforcing material such as glass fiber, glass flake or filler is stacked on the metal support layer 1, and a copper foil having a thickness of 12 μm is stacked thereon. The first insulating resin layer 2 with a copper foil is bonded to the metal support layer 1 by thermocompression bonding with a lamination press. Next, the entire outer surface of the copper foil is etched with an etchant such as a ferric chloride aqueous solution to expose the surface of the first insulating resin layer 2. Since this first insulating resin layer 2 is reinforced with glass fiber, it has a large rigidity after curing and a high strength, so it is composed of a thin metal support layer 1, a thin metal release layer 1a, and a thin adhesive layer 1b. Even in the thin support 1c, the first insulating resin layer 2 has an effect of further compensating for the insufficient strength of the support 1c and obtaining a substrate having high rigidity. Thereby, there exists an effect which can stabilize the dimensional behavior in the manufacturing process of a printed wiring board.

特に、第１の絶縁樹脂層２には後工程による熱応力が何回も加わり熱応力により内部にクラックを生じ易く製造後にそのクラックが拡大し不具合を生じる恐れがあるので、第１の絶縁樹脂層２にガラス繊維入り樹脂プリプレグを用いることで、第１の絶縁樹脂層２を強化しクラック不具合を防止する効果がある。そして、不具合を発生し易い第１の絶縁樹脂層２をこのように補強することで製造する印刷配線板の信頼性を高くできる効果がある。また、補強材入り樹脂プリプレグの補強材としては、ガラス繊維以外に、アラミド不織布、アラミド繊維、ポリエステル繊維を使用することもできる。また、第１の絶縁樹脂層２の補強材は、繊維状の補強材以外にフレーク状の補強材、または、フィラーで、例えばセラミックスや硫酸バリウム等のフィラーで強化した補強材入り樹脂プリプレグを用いることができる。第１の絶縁樹脂層２の樹脂材料として、エポキシ樹脂、ビスマレイミド−トリアジン樹脂（以下、ＢＴ樹脂と称す）ポリイミド、ＰＰＥ樹脂、フェノール樹脂、ＰＴＦＥ樹脂、珪素樹脂、ポリブタジエン樹脂、ポリエステル樹脂、メラミン樹脂、ユリア樹脂、ＰＰＳ樹脂などの有機樹脂を使用することができる。また、これらの樹脂単独でも、複数樹脂を混合しあるいは化合物を作成するなどの樹脂の組み合わせも使用できる。 In particular, the first insulating resin layer 2 is subjected to thermal stress in the subsequent process many times, and the internal stress is likely to cause cracks in the interior. By using the glass fiber-containing resin prepreg for the layer 2, the first insulating resin layer 2 is strengthened and the crack defect is prevented. And there exists an effect which can improve the reliability of the printed wiring board manufactured by reinforcing the 1st insulating resin layer 2 which is easy to generate | occur | produce a defect in this way. In addition to the glass fiber, an aramid nonwoven fabric, an aramid fiber, or a polyester fiber can be used as the reinforcing material of the resin prepreg with a reinforcing material. The reinforcing material of the first insulating resin layer 2 uses a prepreg containing a reinforcing material reinforced with a flaky reinforcing material or a filler, for example, a filler such as ceramics or barium sulfate, in addition to the fibrous reinforcing material. be able to. As a resin material of the first insulating resin layer 2, epoxy resin, bismaleimide-triazine resin (hereinafter referred to as BT resin) polyimide, PPE resin, phenol resin, PTFE resin, silicon resin, polybutadiene resin, polyester resin, melamine resin Organic resins such as urea resin and PPS resin can be used. In addition, these resins can be used alone, or a combination of resins such as mixing a plurality of resins or preparing a compound can be used.

（工程３）
次に、必要に応じて第１の絶縁樹脂層２の表面を粗化する。一般的には、クロム酸、過マンガン酸塩の水溶液などの酸化剤による表面粗化処理などのウェットプロセスや、プラズマ処理やアッシング処理などのドライプロセスが有効である。次に、図１（ｄ）のように、無電解銅めっき処理により、第１の絶縁樹脂層２の表面の全面に、厚さ０．５μｍから３μｍのめっき下地導電層３を形成する。
（工程４）
次に、図２（ｅ）のように、めっきレジスト４として例えばドライフィルムの感光性レジストをロールラミネートで基板に貼り付け、次に、図２（ｆ）のように、露光・現像し配線パターン部分５を開口して、その部分でめっき下地導電層３を露出させためっきレジスト４のパターンを形成する。
（工程５）
次に、図２（ｇ）のように、めっき下地導電層３を電極にして電解銅めっき処理により、配線パターン部分５で露出しためっき下地導電層３の面上に銅めっきを１５μｍの厚さに厚付けした配線パターン６を形成した第１の導体層を形成する。
（工程６）
次に、めっきレジスト４を剥離する。次に、図３（ｈ）のように、過水硫酸系のフラッシュエッチング処理により、第１の絶縁樹脂層２上の第１の導体層に残っている厚さ０．５μｍから３μｍのめっき下地導電層３を除去し、第１の絶縁樹脂層２に配線パターン６を残した第１の導体層を形成する。 (Process 3)
Next, the surface of the first insulating resin layer 2 is roughened as necessary. In general, wet processes such as surface roughening with an oxidizing agent such as an aqueous solution of chromic acid or permanganate, and dry processes such as plasma treatment or ashing treatment are effective. Next, as shown in FIG. 1D, a plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm is formed on the entire surface of the first insulating resin layer 2 by electroless copper plating.
(Process 4)
Next, as shown in FIG. 2E, for example, a photosensitive resist of a dry film is attached to the substrate by roll lamination as the plating resist 4, and then exposed and developed to form a wiring pattern as shown in FIG. 2F. The part 5 is opened, and a pattern of the plating resist 4 in which the plating base conductive layer 3 is exposed at the part is formed.
(Process 5)
Next, as shown in FIG. 2G, copper plating is applied to the surface of the plating base conductive layer 3 exposed at the wiring pattern portion 5 by electrolytic copper plating using the plating base conductive layer 3 as an electrode to a thickness of 15 μm. A first conductor layer on which the thick wiring pattern 6 is formed is formed.
(Step 6)
Next, the plating resist 4 is peeled off. Next, as shown in FIG. 3 (h), a plating base having a thickness of 0.5 μm to 3 μm remaining on the first conductor layer on the first insulating resin layer 2 by a perhydrosulfuric acid-based flash etching process. The conductive layer 3 is removed, and a first conductor layer in which the wiring pattern 6 is left on the first insulating resin layer 2 is formed.

（変形例３）
以上の工程３から工程６による配線パターン６の形成方法はセミアディティブ工法であ
るが、これ以外に、以下の製造方法でも同様に第１の導体層の配線パターン６を形成することができる。すなわち、第１に、第１の絶縁樹脂層２の表面を粗化した後に、無電解銅めっき処理でめっき下地導電層３を形成し、第２に、めっき下地導電層３の全面に電解銅めっきを１２μｍの厚さで加えた第１の導体層を形成し、第３に、第１の導体層の表面にエッチングレジストパターンを形成することで第１の導体層をエッチングして配線パターン６を形成する。第４にエッチングレジストを剥離する。以上のサブトラクティブ工法によっても配線パターン６を形成し図３（ｈ）の構造を製造できる。
（工程７）
次に、第１の導体層の配線パターン６の表面を粗化処理することで第２の絶縁樹脂層２−２を形成する準備をする。この粗化処理としては、ＣＺ処理または酸化還元処理による黒化処理、過水硫酸系のソフトエッチング処理等を実施する。 (Modification 3)
The method of forming the wiring pattern 6 in the above steps 3 to 6 is a semi-additive method, but the wiring pattern 6 of the first conductor layer can be similarly formed by the following manufacturing method in addition to this. That is, first, after the surface of the first insulating resin layer 2 is roughened, the plating base conductive layer 3 is formed by electroless copper plating, and second, the electrolytic copper is deposited on the entire surface of the plating base conductive layer 3. A first conductor layer having a thickness of 12 μm is formed, and third, an etching resist pattern is formed on the surface of the first conductor layer to etch the first conductor layer to form a wiring pattern 6. Form. Fourth, the etching resist is removed. The wiring pattern 6 can also be formed by the above subtractive construction method to manufacture the structure of FIG.
(Step 7)
Next, the surface of the wiring pattern 6 of the first conductor layer is roughened to prepare for forming the second insulating resin layer 2-2. As the roughening treatment, blackening treatment by CZ treatment or oxidation-reduction treatment, perhydrosulfuric acid based soft etching treatment, or the like is performed.

次に、図３（ｉ）のように、第１の絶縁樹脂層２の厚さより配線パターン６の厚さだけ厚い第２の絶縁樹脂層２−２を、ロールラミネートまたは積層プレスで、配線パターン６および第１の絶縁樹脂層２の面上に熱圧着させる。例えば厚さ４５μｍエポキシ樹脂をロールラミネートする。これにより、配線パターン６、すなわち第１の導体層の上の第２の絶縁樹脂層２−２の厚さを第１の第１の絶縁樹脂層２と同じ厚さにする。ここで、第２の絶縁樹脂層２−２を形成するために、ガラス繊維やガラスフレークやフィラーなどの補強材入り樹脂プリプレグに厚さ１２μｍの銅箔を重ね合わせ、積層プレスで熱圧着させることで、銅箔付きの第２の絶縁樹脂層２−２を形成することが望ましい。第２の絶縁樹脂層２−２の材料としては、ガラス繊維入りエポキシ樹脂材、ガラス繊維入りＢＴ樹脂材、ガラス繊維入りポリイミド樹脂材、ガラス繊維入りＰＰＥ樹脂材を使用できる。ガラス繊維入り樹脂プリプレグを用いることで、絶縁樹脂層２−２にクラックが発生することを防ぎ、また、クラックが絶縁樹脂層２−２で成長することを防ぐことができる効果がある。こうして、プリプレグと銅箔を熱圧着させて第２の絶縁樹脂層２−２を形成した場合は、その銅箔を全面エッチングする。エッチング液として、塩化第二鉄水溶液などが使用できる。   Next, as shown in FIG. 3 (i), the second insulating resin layer 2-2, which is thicker than the first insulating resin layer 2 by the thickness of the wiring pattern 6, is formed by roll lamination or laminating press. 6 and thermocompression bonding on the surface of the first insulating resin layer 2. For example, a 45 μm thick epoxy resin is roll laminated. As a result, the thickness of the second insulating resin layer 2-2 on the wiring pattern 6, that is, the first conductor layer is made the same as that of the first first insulating resin layer 2. Here, in order to form the second insulating resin layer 2-2, a 12 μm-thick copper foil is superimposed on a resin prepreg containing a reinforcing material such as glass fiber, glass flake, or filler, and thermocompression-bonded with a lamination press. Thus, it is desirable to form the second insulating resin layer 2-2 with the copper foil. As a material for the second insulating resin layer 2-2, an epoxy resin material containing glass fiber, a BT resin material containing glass fiber, a polyimide resin material containing glass fiber, and a PPE resin material containing glass fiber can be used. By using the glass fiber-containing resin prepreg, it is possible to prevent cracks from occurring in the insulating resin layer 2-2 and to prevent the cracks from growing in the insulating resin layer 2-2. In this way, when the second insulating resin layer 2-2 is formed by thermocompression bonding of the prepreg and the copper foil, the entire surface of the copper foil is etched. An aqueous ferric chloride solution or the like can be used as an etching solution.

（工程８）
次に、図３（ｊ）のように、ビアホール下穴７を形成する。ビアホール下穴７は、レーザ法あるいはフォトエッチング法で形成する。フォトエッチング法で第２の絶縁樹脂層２−２にビアホール下穴７を形成する場合は、絶縁樹脂層２−２に光硬化型の感光性樹脂を用いる場合は、所定のビアホール下穴７の部分を遮光するパターンを形成したマスクを第２の絶縁樹脂層２−２に密着させ、紫外線により露光し、未露光部を現像除去する。あるいは、第２の絶縁樹脂層２−２に光分解型の感光性樹脂を用いる場合は、所定のビアホール下穴７部以外を遮光するパターンを形成したマスクを第２の絶縁樹脂層２−２に密着させ、紫外線により露光し、露光部を現像除去するフォトエッチング法によりビアホール下穴７を形成する。 (Process 8)
Next, as shown in FIG. 3J, a via hole prepared hole 7 is formed. The via hole prepared hole 7 is formed by a laser method or a photo etching method. When the via hole pilot hole 7 is formed in the second insulating resin layer 2-2 by the photoetching method, when a photo-curing type photosensitive resin is used for the insulating resin layer 2-2, the predetermined via hole pilot hole 7 is formed. A mask formed with a pattern for shielding the part is brought into close contact with the second insulating resin layer 2-2, exposed to ultraviolet rays, and unexposed portions are developed and removed. Alternatively, in the case of using a photodegradable photosensitive resin for the second insulating resin layer 2-2, a mask formed with a pattern that shields light other than the predetermined via hole pilot hole 7 portion is used as the second insulating resin layer 2-2. The via hole prepared hole 7 is formed by a photo-etching method in which the exposed portion is exposed to ultraviolet light and exposed to ultraviolet light, and the exposed portion is developed and removed.

レーザ光にて第２の絶縁樹脂層２−２にビアホール下穴７を形成する場合は、レーザ光としては、高調波ＹＡＧレーザやエキシマレーザなどの紫外線レーザ光を用いるか、炭酸ガスレーザなどの赤外線レーザ光を用いる。このようにレーザ光の波長域としては赤外光領域から紫外光領域までを用いる。第２の絶縁樹脂層２−２が熱硬化性樹脂からなる場合は、レーザ光にてビアホール下穴７を形成することが望ましい。ここで、レーザ光でビアホール下穴７を形成した場合は、ビアホール下穴７は、その穴の開口部分の径がその穴の底部の穴の径より大きい、円錐台形状の穴になる。   When the via hole pilot hole 7 is formed in the second insulating resin layer 2-2 with a laser beam, an ultraviolet laser beam such as a harmonic YAG laser or an excimer laser is used as the laser beam, or an infrared ray such as a carbon dioxide laser is used. Laser light is used. As described above, the wavelength range of the laser light is from the infrared light region to the ultraviolet light region. When the second insulating resin layer 2-2 is made of a thermosetting resin, it is desirable to form the via hole prepared hole 7 with a laser beam. Here, when the via-hole prepared hole 7 is formed by the laser beam, the via-hole prepared hole 7 is a frustoconical hole in which the diameter of the opening portion of the hole is larger than the diameter of the hole at the bottom of the hole.

ビアホール下穴７を形成した後にビアホール下穴７の底に薄い樹脂膜が残るため、デスミア処理により、その薄い樹脂膜を除去する。このデスミア処理は、強アルカリにより樹脂を膨潤させ、その後、クロム酸、過マンガン酸塩水溶液などの酸化剤を使用して樹脂を
分解除去する。また研磨材によるサンドブラスト処理やプラズマ処理にて除去してもよい。 Since a thin resin film remains at the bottom of the via hole pilot hole 7 after the via hole pilot hole 7 is formed, the thin resin film is removed by a desmear process. In the desmear treatment, the resin is swollen with a strong alkali, and then the resin is decomposed and removed using an oxidizing agent such as chromic acid or a permanganate aqueous solution. Alternatively, it may be removed by sandblasting or plasma treatment with an abrasive.

第２の絶縁樹脂層２−２にビアホール下穴７を形成した後、必要に応じて第２の絶縁樹脂層２−２の表面を粗化する。一般的には、熱硬化性樹脂や熱可塑性樹脂を使用した場合、クロム酸、過マンガン酸塩の水溶液などの酸化剤による表面粗化処理などのウェットプロセスや、プラズマ処理やアッシング処理などのドライプロセスが有効である。
（工程９）
次に、工程３と同様にして、ビアホール下穴７の壁面および第２の絶縁樹脂層２−２の表面の全面に無電解銅めっき処理により厚さ０．５μｍから３μｍのめっき下地導電層３（図示せず）を第２の導体層として形成する。次に、工程４と同様にして、めっきレジスト４（図示せず）例えばドライフィルムの感光性レジストをロールラミネートで基板に貼り付け、次に、露光・現像して配線パターン部分５（図示せず）を開口しためっきレジスト４を形成する。 After forming the via hole prepared hole 7 in the second insulating resin layer 2-2, the surface of the second insulating resin layer 2-2 is roughened as necessary. In general, when a thermosetting resin or thermoplastic resin is used, wet processes such as surface roughening with an oxidizing agent such as an aqueous solution of chromic acid or permanganate, or dry processes such as plasma treatment or ashing treatment are performed. The process is valid.
(Step 9)
Next, in the same manner as in step 3, the plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm is formed by electroless copper plating on the entire wall surface of the via hole pilot hole 7 and the surface of the second insulating resin layer 2-2. (Not shown) is formed as the second conductor layer. Next, in the same manner as in step 4, a plating resist 4 (not shown), for example, a dry film photosensitive resist is attached to the substrate by roll lamination, and then exposed and developed to form a wiring pattern portion 5 (not shown). A plating resist 4 having an opening is formed.

（工程１０）
次に、めっき下地導電層３を電極にして電解銅めっき処理を行い、配線パターン部分５に露出しためっき下地導電層３の面上に電解銅めっき層を１５μｍの厚さに厚付けすることで配線パターン６−２を形成した第２の導体層を形成し、同時に、ビアホール下穴７を電解銅めっき層で充填したビアホール７−２を第２の絶縁樹脂層２−２に埋め込んで形成する。この際にビアホール７−２を形成するために、電解銅めっき浴としては、以下の組成のように平滑剤を含む電解銅めっき浴を用いることが望ましい。
（電解銅めっき浴組成）
硫酸銅：200〜250ｇ/Ｌ
硫酸 ：30〜50ｇ/Ｌ
塩素 ：30〜60ｐｐｍ
ポリエチレングリコール（ＰＥＧ）：0.5〜1ｇ/Ｌ
ビス（３−スルホプロピル）ジスルフィド（ＳＰＳ）：1〜10ｍｇ/L
平滑剤：ヤーヌスグリーンＢ（ＪＧＢ）を1〜10ｍｇ/Ｌ。 (Process 10)
Next, electrolytic copper plating is performed using the plating base conductive layer 3 as an electrode, and the electrolytic copper plating layer is thickened to a thickness of 15 μm on the surface of the plating base conductive layer 3 exposed to the wiring pattern portion 5. A second conductor layer on which the wiring pattern 6-2 is formed is formed, and at the same time, a via hole 7-2 in which the via hole prepared hole 7 is filled with an electrolytic copper plating layer is embedded in the second insulating resin layer 2-2. . At this time, in order to form the via hole 7-2, it is desirable to use an electrolytic copper plating bath containing a smoothing agent as the following composition as the electrolytic copper plating bath.
(Electrolytic copper plating bath composition)
Copper sulfate: 200-250g / L
Sulfuric acid: 30-50g / L
Chlorine: 30-60ppm
Polyethylene glycol (PEG): 0.5-1g / L
Bis (3-sulfopropyl) disulfide (SPS): 1 to 10 mg / L
Smoothing agent: 1-10 mg / L of Janus Green B (JGB).

（工程１１）
次に、めっきレジスト４を剥離する。次に、第２の絶縁樹脂層２−２上の第２の導体層に残っている厚さ０．５μｍから３μｍのめっき下地導電層３は除去し、厚さ１５μｍの配線パターン６−２の大部分は残す過水硫酸系のフラッシュエッチング処理を行い、図４（ｋ）のように、第２の絶縁樹脂層２−２にビアホール７−２を有し、その上に第２の導体層の配線パターン６−２を有する構造を形成する。この工程でレーザ光を用いて形成したビアホール下穴７は、その穴の開口部分の径がその穴の底部の穴の径より大きい、円錐台形状の穴になるので、そのビアホール下穴７に形成されたビアホール７−２の径は、金属支持層１側の径が、金属支持層１から遠い側の径よりも小さい円錐台形状に形成される。 (Step 11)
Next, the plating resist 4 is peeled off. Next, the plating base conductive layer 3 having a thickness of 0.5 μm to 3 μm remaining on the second conductor layer on the second insulating resin layer 2-2 is removed, and the wiring pattern 6-2 having a thickness of 15 μm is removed. Most of the remaining persulfuric acid-based flash etching is performed, and as shown in FIG. 4 (k), the second insulating resin layer 2-2 has a via hole 7-2, and the second conductor layer is formed thereon. A structure having the wiring pattern 6-2 is formed. The via hole prepared hole 7 formed by using the laser beam in this process is a truncated cone-shaped hole in which the diameter of the opening portion of the hole is larger than the diameter of the hole at the bottom of the hole. The formed via hole 7-2 has a truncated cone shape in which the diameter on the metal support layer 1 side is smaller than the diameter on the side far from the metal support layer 1.

（工程１２）
次に、以下のように、工程７から工程１１までを繰り返すことで、配線パターンの導体層を多層に形成する。先ず、工程７の処理により、図４（ｍ）のように、絶縁樹脂層２−３を形成する。次に、工程８から工程１１の処理により、図５（ｎ）のように、配線パターン６−３の導体層と、絶縁樹脂層２−３に埋め込まれたビアホール７−３を形成する。こうして、工程３から工程１２の処理により、配線パターン６と６−２と６−３の３層の導体層が形成できる。この工程でレーザ光を用いて形成したビアホール下穴７に形成されたビアホール７−３の径は、金属支持層１側の径が、金属支持層１から遠い側の径よりも小さい円錐台形状に形成される。
（工程１３）
次に、図５（ｏ）のように、工程７の処理により絶縁樹脂層２−４を形成する。こうして、支持体１ｃの両面に第１の絶縁樹脂層２と、第２の絶縁樹脂層２−２と第２の導体層６−２が交互に重ねられ、外層が絶縁樹脂層２−４で覆われた基板を形成する。 (Step 12)
Next, by repeating steps 7 to 11 as described below, the conductor layer of the wiring pattern is formed in multiple layers. First, the insulating resin layer 2-3 is formed by the process of step 7 as shown in FIG. Next, by the processing from step 8 to step 11, as shown in FIG. 5N, the conductor layer of the wiring pattern 6-3 and the via hole 7-3 embedded in the insulating resin layer 2-3 are formed. In this way, the three conductor layers of the wiring patterns 6, 6-2, and 6-3 can be formed by the processing from step 3 to step 12. The diameter of the via hole 7-3 formed in the via hole pilot hole 7 formed using the laser beam in this step is a truncated cone shape in which the diameter on the metal support layer 1 side is smaller than the diameter on the side far from the metal support layer 1 Formed.
(Step 13)
Next, as shown in FIG. 5 (o), an insulating resin layer 2-4 is formed by the process of step 7. Thus, the first insulating resin layer 2, the second insulating resin layer 2-2, and the second conductor layer 6-2 are alternately stacked on both surfaces of the support 1c, and the outer layer is the insulating resin layer 2-4. A covered substrate is formed.

（工程１４）
次に、図６（ｐ）のように、基板の端部から金属剥離層１ａまでの１５ｍｍから３０ｍｍ程度の外周接着部分１ｄをルーターやプレス加工等で切断し金属剥離層１ａと金属支持層１の接触部分の外周を露出させた外周露出部１ｅを形成する。次に、図６（ｑ）のように、支持体１ｃの外側の２組の、金属支持層１を含む上側の部分の金属支持層１付き基板と、下側の金属支持層１付き基板を分離する。ここで、金属剥離層１ａと金属支持層１は接着していないので、外周接着部分１ｄが除去されて金属剥離層１ａと金属支持層１の接触部分の外周が露出されると、何ら応力を加えずに両者を分離できる。従来の製造方法で、両者を緩く接着しておき、緩く応力を加えて両者を引き剥がす製造方法では、引き剥がした基板が引き剥がしの応力により反る問題があったが、本実施形態では、何ら応力を加えずに両者を分離できるので、分離した基板が反らない効果がある。 (Step 14)
Next, as shown in FIG. 6 (p), the outer peripheral adhesive portion 1d of about 15 mm to 30 mm from the end of the substrate to the metal peeling layer 1a is cut by a router or press working, and the metal peeling layer 1a and the metal support layer 1 are cut. The outer periphery exposed portion 1e is formed by exposing the outer periphery of the contact portion. Next, as shown in FIG. 6 (q), two sets of the substrate with the metal support layer 1 on the upper side including the metal support layer 1 and the substrate with the metal support layer 1 on the lower side of the support 1c are provided. To separate. Here, since the metal peeling layer 1a and the metal supporting layer 1 are not bonded, if the outer peripheral bonding portion 1d is removed and the outer periphery of the contact portion between the metal peeling layer 1a and the metal supporting layer 1 is exposed, no stress is applied. Both can be separated without adding. In the conventional manufacturing method, the two are loosely bonded, and in the manufacturing method in which both are loosely applied and peeled off, there is a problem that the peeled substrate is warped by the peeling stress, but in this embodiment, Since both can be separated without applying any stress, there is an effect that the separated substrate does not warp.

（工程１５）
次に、図７（ｒ）のように、銅の金属支持層１をエッチングして除去することで、両面を第１の絶縁樹脂層２と絶縁樹脂層２−４で被覆した印刷配線板中間体８を製造する。この際に用いるエッチング溶液として、例えばアンモニアを主成分としたアルカリエッチング液などを使用できる。あるいは、第二塩化鉄水溶液または第二塩化銅水溶液を使用しても良い。ここで、先の変形例１で金属支持層１として厚さ１２μｍの銅箔を用いた場合は、この工程１５における金属支持層１のエッチング処理の時間をきわめて短時間で済ませることができる効果がある。 (Step 15)
Next, as shown in FIG. 7 (r), the copper metal support layer 1 is removed by etching, so that the printed wiring board intermediate layer whose both surfaces are covered with the first insulating resin layer 2 and the insulating resin layer 2-4 is removed. The body 8 is manufactured. As an etching solution used at this time, for example, an alkaline etching solution mainly containing ammonia can be used. Alternatively, a ferric chloride aqueous solution or a cupric chloride aqueous solution may be used. Here, when a copper foil having a thickness of 12 μm is used as the metal support layer 1 in the first modification example, the etching process of the metal support layer 1 in this step 15 can be performed in an extremely short time. is there.

この工程１５で得た印刷配線板中間体８は、その各絶縁樹脂層２、２−２、２−３、２−４の厚さが薄くても、それらの絶縁樹脂層を複数層重ねたことで適度の厚さを有するので、その印刷配線板中間体８の取り扱いが容易であり、この印刷配線板中間体８を内層基板にして両面に導体層と絶縁樹脂層を逐次形成して印刷配線板を製造することが容易である効果がある。また、印刷配線板中間体８の両面の導体層が第１の絶縁樹脂層２と絶縁樹脂層２−４で保護され外に露出しないので、印刷配線板中間体８から金属支持層１をエッチングして除去する際に印刷配線板中間体８の導体層が損傷しない効果がある。それ以降の製造工程における取り扱いでも、導体層が第１の絶縁樹脂層２と絶縁樹脂層２−４で保護されるのでその損傷が無く、印刷配線板の製造歩留まりが向上する効果がある。   The printed wiring board intermediate 8 obtained in this step 15 has a plurality of insulating resin layers stacked even if the insulating resin layers 2, 2-2, 2-3, 2-4 are thin. Therefore, the printed wiring board intermediate body 8 is easy to handle, and the printed wiring board intermediate body 8 is used as an inner substrate to sequentially form a conductor layer and an insulating resin layer on both sides for printing. There is an effect that it is easy to manufacture the wiring board. Further, since the conductor layers on both sides of the printed wiring board intermediate 8 are protected by the first insulating resin layer 2 and the insulating resin layer 2-4 and are not exposed to the outside, the metal support layer 1 is etched from the printed wiring board intermediate 8. Thus, there is an effect that the conductor layer of the printed wiring board intermediate 8 is not damaged when removed. Even in handling in the subsequent manufacturing process, the conductor layer is protected by the first insulating resin layer 2 and the insulating resin layer 2-4, so that there is no damage and the manufacturing yield of the printed wiring board is improved.

（変形例４）
以上の製造工程は、配線パターン６、６−２、６−３の３層の導体層を形成し、両面を第１の絶縁樹脂層２と絶縁樹脂層２−４で被覆した印刷配線板中間体８を製造するものであるが、これ以外の印刷配線板中間体８として、配線パターン６、６−２の２層の導体層を形成し、３層の絶縁樹脂層２、２−２、２−３を形成し、両面の表層を第１の絶縁樹脂層２と絶縁樹脂層２−３にした印刷配線板中間体８を製造することも可能である。更に、配線パターン６の１層の導体層を第１の絶縁樹脂層２と絶縁樹脂層２−２で被覆した印刷配線板中間体８を製造することも可能である。 (Modification 4)
In the above manufacturing process, three conductive layers of wiring patterns 6, 6-2, and 6-3 are formed, and the printed wiring board intermediate is coated with the first insulating resin layer 2 and the insulating resin layer 2-4 on both surfaces. Although the body 8 is manufactured, as the printed wiring board intermediate body 8 other than this, the two conductor layers of the wiring patterns 6 and 6-2 are formed, and the three insulating resin layers 2 and 2-2 are formed. It is also possible to manufacture the printed wiring board intermediate body 8 in which 2-3 is formed and the surface layers on both sides are the first insulating resin layer 2 and the insulating resin layer 2-3. Furthermore, it is also possible to manufacture the printed wiring board intermediate body 8 in which one conductor layer of the wiring pattern 6 is covered with the first insulating resin layer 2 and the insulating resin layer 2-2.

（工程１６）
次に、工程８と同様にして、印刷配線板中間体８の絶縁樹脂層２−４と第１の絶縁樹脂層２にレーザ光でビアホール下穴７を形成する。すなわち、ここでは、基板の片側のみではなく基板の両側にビアホール下穴７を形成する。この工程でレーザ光を用いて形成したビアホール下穴７の印刷配線板中間体８の中心側の底面の内径よりも印刷配線板中間体８
の外側の開口部の内径が大きい円錐台形状に形成される。 (Step 16)
Next, in the same manner as in step 8, via hole prepared holes 7 are formed in the insulating resin layer 2-4 and the first insulating resin layer 2 of the printed wiring board intermediate body 8 by laser light. That is, here, via hole prepared holes 7 are formed not only on one side of the substrate but also on both sides of the substrate. In this process, the printed wiring board intermediate body 8 is formed to be smaller than the inner diameter of the bottom surface of the printed wiring board intermediate body 8 in the via hole pilot hole 7 formed by using laser light.
Is formed in a truncated cone shape with a large inner diameter of the outer opening.

（工程１７）
次に、図７（ｓ）のように、工程９から工程１１と同様にして、ただし、基板の片側のみではなく基板の両側に金属めっきをする。すなわち、両面への金属めっきにより、絶縁樹脂層２−４の表面に形成した第３の導体層の配線パターン６−４と、絶縁樹脂層２−４に埋め込んだビアホール７−４を形成し、また、第１の絶縁樹脂層２に重ねた配線パターン６−１と、第１の絶縁樹脂層２に埋め込んだビアホール７−１を形成する。この工程で、先にレーザ光で形成したビアホール下穴７を金属めっきで充填したビアホール７−４と７−１は、その印刷配線板中間体８の中心側の底部の径よりも印刷配線板中間体８の外側の底部の径が大きい円錐台形状に形成される。 (Step 17)
Next, as shown in FIG. 7 (s), in the same manner as in steps 9 to 11, metal plating is performed not only on one side of the substrate but also on both sides of the substrate. That is, by metal plating on both surfaces, a wiring pattern 6-4 of the third conductor layer formed on the surface of the insulating resin layer 2-4 and a via hole 7-4 embedded in the insulating resin layer 2-4 are formed. In addition, a wiring pattern 6-1 superimposed on the first insulating resin layer 2 and a via hole 7-1 embedded in the first insulating resin layer 2 are formed. In this process, the via holes 7-4 and 7-1 in which the via hole prepared holes 7 previously formed by laser light are filled with the metal plating are printed wiring boards rather than the diameter of the bottom portion on the center side of the printed wiring board intermediate body 8. The intermediate body 8 is formed in a truncated cone shape with a large diameter at the bottom of the intermediate body 8.

（工程１８）
この図７（ｓ）の印刷配線板中間体８は厚さが約２００μｍあり電気検査装置で検査するための適度の厚さを有するので、電気検査の際の取り扱いが容易である効果がある。そのため、この印刷配線板中間体８を電気検査装置に設置し、印刷配線板中間体８の両面のビアホール下穴７に露出した配線パターン間の導通を検査する。これにより、印刷配線板中間体８の全配線パターンと導体層間を接続するビアホールの不良を検出し、不良品の印刷配線板中間体８を除外し以降の製造工程を進める。こうして配線パターンの電気接続の不具合を十分に検査し不具合を除外しつつ製造工程を進めることができ、印刷配線板の製造歩留まりを向上させられる効果がある。 (Step 18)
The printed wiring board intermediate body 8 shown in FIG. 7 (s) has a thickness of about 200 μm and an appropriate thickness for inspecting with an electrical inspection apparatus, so that there is an effect that handling at the time of electrical inspection is easy. Therefore, this printed wiring board intermediate body 8 is installed in an electrical inspection device, and the continuity between the wiring patterns exposed in the via hole prepared holes 7 on both surfaces of the printed wiring board intermediate body 8 is inspected. Thereby, the defect of the via hole connecting all the wiring patterns of the printed wiring board intermediate body 8 and the conductor layers is detected, and the defective printed wiring board intermediate body 8 is excluded, and the subsequent manufacturing process proceeds. Thus, it is possible to proceed with the manufacturing process while sufficiently inspecting the defects in the electrical connection of the wiring pattern and excluding the defects, and the production yield of the printed wiring board can be improved.

（工程１９）
次に、図７（ｔ）のように、工程７と同様にして、印刷配線板中間体８を内層基板として、その両面に第３の絶縁樹脂層２−５（上面）と２−６（下面）を形成する。この際に、導体層の上の第３の絶縁樹脂層の厚さを第１の絶縁樹脂層２の厚さと同じ厚さに形成する。 (Step 19)
Next, as shown in FIG. 7 (t), in the same manner as in step 7, the printed wiring board intermediate body 8 is used as an inner substrate, and third insulating resin layers 2-5 (upper surface) and 2-6 (upper surface) are formed on both surfaces thereof. Bottom surface). At this time, the thickness of the third insulating resin layer on the conductor layer is formed to be the same as the thickness of the first insulating resin layer 2.

（工程２０）
以下、必要な層数が得られるまで、工程１９に続いて工程１６から工程１７を繰り返し、図８（ｕ）のように、絶縁樹脂層２−５の内部に埋め込んだビアホール７−５と絶縁樹脂層２−５の表面に形成した導体層の配線パターン６−５を形成し、絶縁樹脂層２−６の内部に埋め込んだビアホール７−６と絶縁樹脂層２−６の表面に形成した導体層の配線パターン６−６を形成する。この工程でレーザ光を用いて形成したビアホール下穴７に形成したビアホール７−５と７−６は、その印刷配線板中間体８の中心側の底部の径よりも印刷配線板中間体８の外側の底部の径が大きい円錐台形状に形成される。この基板の最外層の絶縁樹脂層２−５および２−６は、補強材を含まない絶縁樹脂で形成することが望ましい。それにより、絶縁樹脂層２−５および２−６の凹凸が低減され平坦性が向上し、最外層に高密度な配線パターン６−５と６−６を形成することができる効果がある。 (Step 20)
Thereafter, until the required number of layers is obtained, the process 16 to the process 17 are repeated following the process 19 to insulate the via hole 7-5 embedded in the insulating resin layer 2-5 as shown in FIG. 8 (u). Conductor layer wiring pattern 6-5 formed on the surface of resin layer 2-5, and via hole 7-6 embedded in insulating resin layer 2-6 and conductor formed on the surface of insulating resin layer 2-6 A layer wiring pattern 6-6 is formed. The via holes 7-5 and 7-6 formed in the via hole pilot holes 7 formed by using laser light in this step are larger than the diameter of the bottom portion on the center side of the printed wiring board intermediate 8. The outer bottom is formed in a truncated cone shape with a large diameter. It is desirable that the outermost insulating resin layers 2-5 and 2-6 of this substrate be formed of an insulating resin that does not include a reinforcing material. Thereby, the unevenness of the insulating resin layers 2-5 and 2-6 is reduced, the flatness is improved, and there is an effect that the high-density wiring patterns 6-5 and 6-6 can be formed in the outermost layer.

（工程２１）
この工程２１は、先の工程１６から工程１７により基板の両面にビアホールと配線パターンから成る導体層を形成する逐次形成処理を行った後に、工程１９と工程２０を経ずに、直ぐにこの工程２１の処理に進んでも良い。工程２１では、図８（ｖ）のように、基板の両面にソルダーレジスト９を形成する。ソルダーレジスト９の形成手順は、前処理として、配線パターン６−４および配線パターン６−５の粗化処理に例えばＣＺ処理を施す。次に、感光性液状ソルダーレジスト９をスプレーコート、ロールコート、カーテンコート、スクリーン法で約２０μｍ厚に塗布し乾燥、または感光性ドライフィルム・ソルダーレジスト９をロールラミネートで貼り付ける。次に、図８（ｗ）のように、ソルダーレジスト９を露光・現像することで外部電極を形成するための外部電極パッド用開口部１０をソルダーレジスト９に形成する。次にソルダーレジスト９を加熱硬化させる。 (Step 21)
This step 21 is performed immediately after performing the sequential forming process of forming the conductor layer composed of the via hole and the wiring pattern on both surfaces of the substrate in the previous step 16 to step 17, without passing through the step 19 and step 20. You may proceed to the process. In step 21, solder resists 9 are formed on both sides of the substrate as shown in FIG. The solder resist 9 is formed by performing, for example, a CZ process on the roughening process of the wiring pattern 6-4 and the wiring pattern 6-5 as a pre-process. Next, the photosensitive liquid solder resist 9 is applied to a thickness of about 20 μm by spray coating, roll coating, curtain coating, or screen method and dried, or the photosensitive dry film / solder resist 9 is applied by roll lamination. Next, as shown in FIG. 8 (w), the solder resist 9 is exposed and developed to form external electrode pad openings 10 for forming external electrodes in the solder resist 9. Next, the solder resist 9 is cured by heating.

（工程２２）
次に、ソルダーレジスト９の外部電極パッド用開口部１０に露出した配線パターン６−５と６−６に、無電解ニッケルめっき層を３μｍ以上形成し、その上に無電解金めっき層を０．０３μｍ以上形成して外部電極パッド１０−１と１０−２を形成する。外部電極パッド１０−１と１０−２の無電解金めっき層は１μｍ以上のこともある。あるいは、この無電解ニッケルめっきと無電解金めっき層を省略することも可能である。更に外部電極パッド１０−１には、固相点が２１７〜２２７℃程度のＳｎ−Ａｇ−Ｃｕはんだや固相点が２１３℃程度のＳｎ−Ｂｉ−ＡｇはんだやＳｎＰｂはんだ等の、固相点が２３５℃以下のはんだをプリコートする。このプリコートはんだは、固相点が２３０℃以下のはんだを選んで用いることが望ましい。また、外部電極パッド１０−１と１０−２には、無電解ニッケルめっきのかわりに電解ニッケルめっき層を３μｍ以上形成し、その上に電解金めっき層を０．５μｍ以上形成した外部電極パッドを形成しても良い。あるいは、金属めっき層のかわりに、イミダゾール化合物やベンズイミダゾール化合物等から成る水溶性プリフラックスによる水溶液有機防錆皮膜を外部電極パッド１０−１と１０−２に形成することも可能である。
（工程２３）
次に、この基板をダイサーなどで加工することで、１つの基板から、個片に分離した複数の印刷配線板を得る。 (Step 22)
Next, an electroless nickel plating layer of 3 μm or more is formed on the wiring patterns 6-5 and 6-6 exposed in the external electrode pad opening 10 of the solder resist 9, and an electroless gold plating layer is formed on the wiring pattern 6-5 and 6-6. External electrode pads 10-1 and 10-2 are formed to have a thickness of 03 μm or more. The electroless gold plating layers of the external electrode pads 10-1 and 10-2 may be 1 μm or more. Alternatively, the electroless nickel plating and the electroless gold plating layer can be omitted. Further, the external electrode pad 10-1 has a solid phase point such as Sn—Ag—Cu solder having a solid phase point of about 217 to 227 ° C., Sn—Bi—Ag solder or SnPb solder having a solid phase point of about 213 ° C. Is pre-coated with solder at 235 ° C. or lower. As this precoat solder, it is desirable to select and use a solder having a solid phase point of 230 ° C. or lower. Further, the external electrode pads 10-1 and 10-2 are formed by forming an electrolytic nickel plating layer of 3 μm or more instead of electroless nickel plating, and forming an external electrode pad of 0.5 μm or more on the electrolytic gold plating layer thereon. It may be formed. Alternatively, instead of the metal plating layer, an aqueous organic rust preventive film made of a water-soluble preflux made of an imidazole compound or a benzimidazole compound can be formed on the external electrode pads 10-1 and 10-2.
(Step 23)
Next, by processing this substrate with a dicer or the like, a plurality of printed wiring boards separated into individual pieces are obtained from one substrate.

（変形例５）
変形例５として、工程１において、銅の金属支持層１と金属剥離層１ａの間に熱発泡性シートを挟んで基板を積層プレスで加熱・加圧することで金属支持層１と金属剥離層１ａを接着させ、工程２から工程１３で、その両面に絶縁樹脂層と導体層を逐次形成し、工程１４では、オーブン等で積層温度以上の熱、例えば２２０℃を加えて、５分間処理することで、熱発泡シートの残渣なく金属支持層１と金属剥離層１ａを分離することが可能である。以降の工程１５から工程２２を以上の説明のように処理して印刷配線板を製造することができる。 (Modification 5)
As a modified example 5, in step 1, the metal support layer 1 and the metal release layer 1a are formed by heating and pressing the substrate with a laminating press with a thermally foamable sheet sandwiched between the copper metal support layer 1 and the metal release layer 1a. In Step 2 to Step 13, an insulating resin layer and a conductor layer are sequentially formed on both surfaces. In Step 14, heat at a temperature higher than the lamination temperature, for example, 220 ° C. is applied in an oven or the like for 5 minutes. Thus, it is possible to separate the metal support layer 1 and the metal release layer 1a without any residue of the thermally foamed sheet. Subsequent steps 15 to 22 can be processed as described above to produce a printed wiring board.

以上の製造方法により、導体層間の絶縁樹脂層の厚さを同じ厚さに形成した印刷配線板が得られる。ここで、ソルダーレジスト形成後に外部電極パッド１０−１、１０−２の金めっき等を形成するので、外部電極パッド１０−１、１０−２の部分でのソルダーレジスト剥がれが無い良好な品質の印刷配線板が得られる効果がある。また、最良の実施形態として、各絶縁樹脂層２と２−２と２−３と２−４をガラス繊維入り絶縁樹脂層で形成し、絶縁樹脂層２−５と２−６をガラス繊維などの補強材無しの絶縁樹脂層で形成する。そして、この印刷配線板は、印刷配線板中間体８の両面の絶縁樹脂層にビアホールと配線パターンを形成することで、基板の上下に対称な層構成に絶縁樹脂層と配線パターンを逐次形成するので、応力を基板の片面側に偏らせないため、基板が反らない効果がある。そのため、板厚がきわめて薄い印刷配線板でありながら、この印刷配線板にソルダーレジストを印刷する際の加熱処理による熱応力や、後工程のはんだ付けの際の加熱処理などの熱応力を加えても印刷配線板が反る問題が少ない良い品質の印刷配線板が得られる効果がある。   By the above manufacturing method, a printed wiring board in which the insulating resin layers between the conductor layers are formed to the same thickness can be obtained. Here, since the gold plating or the like of the external electrode pads 10-1 and 10-2 is formed after the solder resist is formed, printing with good quality with no peeling of the solder resist at the portions of the external electrode pads 10-1 and 10-2. There is an effect that a wiring board is obtained. Further, as the best embodiment, the insulating resin layers 2, 2-2, 2-3, and 2-4 are formed of insulating resin layers containing glass fibers, and the insulating resin layers 2-5 and 2-6 are made of glass fibers or the like. It is formed of an insulating resin layer without any reinforcing material. In this printed wiring board, via holes and wiring patterns are formed in the insulating resin layers on both surfaces of the printed wiring board intermediate 8 so that the insulating resin layers and the wiring patterns are sequentially formed in a symmetrical layer configuration on the top and bottom of the substrate. Therefore, since the stress is not biased to one side of the substrate, the substrate does not warp. Therefore, while the printed wiring board is very thin, thermal stress due to heat treatment when solder resist is printed on this printed wiring board and thermal stress such as heat treatment during soldering in the subsequent process are applied. Also, there is an effect that a printed wiring board of good quality can be obtained with few problems of warping the printed wiring board.

更に、その金属支持層１を除去する工程１４と工程１５以前に印刷配線板中間体８の絶縁樹脂層２−２と２−３に埋め込んで形成したビアホールは、上底の径が下底の径より大きい逆向きの円錐台形状に形成される。金属支持層１を除去した後に第１の絶縁樹脂層２に形成したビアホールは、印刷配線板の中心に対して上下対称な向きに形成され、ビアホールの円錐台形状の印刷配線板の中心側に面する下底の径よりも印刷配線板の外側に面する上底の径の方が大きく形成される。そのため、印刷配線板で絶縁樹脂層２−２と２−３と２−４と２−５との４層の絶縁樹脂層に埋め込まれたビアホールは上側の径が下側の径より大きい逆向きの円錐台形状に形成され、第１の絶縁樹脂層２と絶縁樹脂層２−６との２層の絶縁樹脂層に埋め込まれたビアホールは上側の径が下側の径より小さい円錐台形状に形成される。   Further, the via holes formed by embedding the insulating resin layers 2-2 and 2-3 of the printed wiring board intermediate 8 before Step 14 and Step 15 for removing the metal support layer 1 have an upper base diameter of the lower base. It is formed in a reverse truncated cone shape larger than the diameter. The via hole formed in the first insulating resin layer 2 after the metal support layer 1 is removed is formed in a vertically symmetrical direction with respect to the center of the printed wiring board, and is located on the center side of the frustoconical printed wiring board of the via hole. The diameter of the upper base facing the outside of the printed wiring board is formed larger than the diameter of the lower base facing. Therefore, the via hole embedded in the insulating resin layers 2-2, 2-3, 2-4, and 2-5 on the printed wiring board has the upper diameter opposite to the lower diameter. The via hole embedded in the two insulating resin layers of the first insulating resin layer 2 and the insulating resin layer 2-6 has a truncated cone shape with an upper diameter smaller than the lower diameter. It is formed.

このように、本実施形態で製造した印刷配線板は、その上層側の絶縁樹脂層が、上側の径が下側の径より大きい逆向きの円錐台形状を有するビアホールを有し、下層側の絶縁樹脂層が含むビアホールが、その上下が逆の円錐台形状を有するビアホールであり、上層側の絶縁樹脂層の層数が下層側の絶縁樹脂層の層数より多い独特な形状の印刷配線板が製造される。この印刷配線板は、この印刷配線板の不具合の解析の際に、断面を観察し各層のビアホールの上下の向きを確認することで、金属支持層１上に逐次形成して形成した印刷配線板中間体の部分とその外側の両面に逐次形成して形成した外側の層を容易に区別することができ、異なる製造プロセスに起因する不具合を容易に区別して解析できる効果がある。   As described above, the printed wiring board manufactured in the present embodiment has a via hole having an inverted frustoconical shape in which the upper insulating resin layer has a larger upper diameter than the lower diameter. The via hole included in the insulating resin layer is a via hole having a truncated cone shape that is upside down, and the number of layers of the upper insulating resin layer is larger than the number of lower insulating resin layers. Is manufactured. This printed wiring board is formed by sequentially forming on the metal support layer 1 by observing the cross section and confirming the vertical direction of the via hole in each layer when analyzing the defects of the printed wiring board. It is possible to easily distinguish between the intermediate layer and the outer layer formed by sequentially forming both sides of the intermediate portion, and it is possible to easily distinguish and analyze defects caused by different manufacturing processes.

（工程２４）
次に、図９（ｘ）のように、外部電極パッド１０−１のプリコートはんだを加熱して再溶融させて半導体素子１１のバンプ１２をはんだ付けして半導体素子１１をフリップチップ接続する。次に、封止樹脂１３を半導体素子１１と絶縁樹脂層２−５との間の空間に流し込み硬化させることで半導体素子１１を絶縁樹脂層２−５とその上面のソルダーレジスト９上にフリップチップ実装する。
（工程２５）
次に、図９（ｙ）のように、外部電極パッド１０−２にはんだボールの外部接続端子１４を装着しボールグリッドアレイ構造の半導体装置を製造する。 (Step 24)
Next, as shown in FIG. 9 (x), the precoat solder of the external electrode pad 10-1 is heated and remelted to solder the bumps 12 of the semiconductor element 11, and the semiconductor element 11 is flip-chip connected. Next, the sealing resin 13 is poured into the space between the semiconductor element 11 and the insulating resin layer 2-5 and cured to flip the semiconductor element 11 onto the insulating resin layer 2-5 and the solder resist 9 on the upper surface thereof. Implement.
(Step 25)
Next, as shown in FIG. 9 (y), a solder ball external connection terminal 14 is attached to the external electrode pad 10-2 to manufacture a semiconductor device having a ball grid array structure.

（変形例６）
半導体装置の変形例として、外部電極パッド１０−２に装着する外部接続端子１４として金属のピン端子を用い、そのピン端子を外部電極パッド１０−２に装着してピングリッドアレイ構造を形成することもできる。外部接続端子１４に用いるピン端子は、例えばピン端子の銅合金の基材の表面にニッケルめっきし、その上に金めっきをした構造のピン端子を用いる。また、ピン端子の、外部電極パッド１０−２に装着する部分を面状端子にし、面状端子にピンを立てた構造のピン端子を用いる。そして、ピン端子のはんだ付けは、工程２４において、半導体素子１１を絶縁樹脂層２−５上に設置する以前に、ピン端子の面状端子を、固相点が２４０℃以上で２５０℃以下のはんだで、外部電極パッド１０−２にはんだ付けする。この条件を満足するはんだにはＳｎ−５Ｓｂはんだ（固相点が２４０℃）やＳｎ−Ｓｂ−Ｐｂはんだ等がある。 (Modification 6)
As a modification of the semiconductor device, a metal pin terminal is used as the external connection terminal 14 to be attached to the external electrode pad 10-2, and the pin terminal is attached to the external electrode pad 10-2 to form a pin grid array structure. You can also. As the pin terminal used for the external connection terminal 14, for example, a pin terminal having a structure in which the surface of a copper alloy base material of the pin terminal is nickel-plated and gold-plated thereon is used. In addition, a pin terminal having a structure in which a portion of the pin terminal attached to the external electrode pad 10-2 is a planar terminal and a pin is raised on the planar terminal is used. The soldering of the pin terminal is performed in step 24, before the semiconductor element 11 is placed on the insulating resin layer 2-5, the planar terminal of the pin terminal has a solid phase point of 240 ° C. or higher and 250 ° C. or lower. The external electrode pad 10-2 is soldered with solder. Examples of solder that satisfies this condition include Sn-5Sb solder (solid phase point is 240 ° C.), Sn—Sb—Pb solder, and the like.

ピン端子をはんだ付けするはんだの固相点が２５０℃を超えるとそのはんだ付け温度が絶縁樹脂層を劣化させる問題があり、固相点が２４０℃未満の場合は、次の工程で、半導体素子１１のバンプ１２を印刷配線板の外部電極パッド１０−１へはんだ付けする際にピン端子の接合部分が外れたり劣化する問題が発生する。このように、外部電極パッド１０−２に固相点が２４０℃以上で２５０℃以下のはんだで外部接続端子１４をはんだ付けすることで、外部電極パッド１０−１に半導体素子１１やその他の電子部品をはんだ付けする際の印刷配線板の加熱処理で外部接続端子の接合部分が耐えることができる効果がある。   When the solid phase point of the solder for soldering the pin terminal exceeds 250 ° C., there is a problem that the soldering temperature deteriorates the insulating resin layer. When the eleven bumps 12 are soldered to the external electrode pads 10-1 of the printed wiring board, there arises a problem that the joint portion of the pin terminal is detached or deteriorated. As described above, the external connection terminal 14 is soldered to the external electrode pad 10-2 with a solder having a solid phase point of 240 ° C. or higher and 250 ° C. or lower, so that the semiconductor element 11 and other electrons are connected to the external electrode pad 10-1. There is an effect that the joint portion of the external connection terminal can withstand the heat treatment of the printed wiring board when soldering the component.

また、外部電極パッド１０−１へ半導体素子１１のバンプ１２をはんだ付けする際に、工程２２でプリコートしたはんだで、固相点が２３５℃以下のはんだを再溶融させる。すなわち、先の工程２２において、外部電極パッド１０−１および外部電極パッド１０−２に、それぞれにはんだ付けする部品に応じたはんだを予めプリコートしておく。すなわち、工程２２では、印刷配線板の外部電極パッド１０−１には固相点が２３５℃以下のはんだをプリコートし、外部電極パッド１０−２には固相点が２４０℃以上で２５０℃以下のはんだをプリコートする。そして、工程２４で、外部電極パッド１０−２にピン端子の外部接続端子１４をはんだ付けしてピングリッドアレイ構造を形成し、次に、外部電極パッド１０−１に２３５℃以下の温度で半導体素子１１のバンプ１２をはんだ付けして半導体装置を製造する。   Further, when the bumps 12 of the semiconductor element 11 are soldered to the external electrode pads 10-1, the solder having a solid phase point of 235 ° C. or lower is remelted with the solder pre-coated in step 22. That is, in the previous step 22, the external electrode pad 10-1 and the external electrode pad 10-2 are pre-coated with solder corresponding to the components to be soldered to each other in advance. That is, in step 22, the external electrode pad 10-1 of the printed wiring board is pre-coated with a solder having a solid phase point of 235 ° C. or less, and the external electrode pad 10-2 has a solid phase point of 240 ° C. or more and 250 ° C. or less. Precoat with solder. In step 24, the external connection terminals 14 of the pin terminals are soldered to the external electrode pads 10-2 to form a pin grid array structure, and then the semiconductor is applied to the external electrode pads 10-1 at a temperature of 235 ° C. or lower. A bump 12 of the element 11 is soldered to manufacture a semiconductor device.

なお、半導体素子１１などをはんだ付けする以前に印刷配線板に接合する外部接続端子１４は、ピン端子に限られない。例えば、電子部品を印刷配線板にはんだ付け以前に、金属バンプの外部接続端子１４を外部電極パッド１０−２にはんだ付け接合した印刷配線板、あるいは表層の導体層の一部に金属スティフナーをはんだ付けした印刷配線板、を形成する場合も同様に固相点が２４０℃以上で２５０℃以下のはんだでそれらの外部接続端子１４等を導体層の一部に接合することが望ましい。   Note that the external connection terminals 14 to be joined to the printed wiring board before the semiconductor element 11 or the like is soldered are not limited to pin terminals. For example, before soldering the electronic component to the printed wiring board, the printed wiring board in which the external connection terminals 14 of the metal bumps are soldered to the external electrode pads 10-2, or the metal stiffener is soldered to a part of the surface conductor layer. Similarly, when the attached printed wiring board is formed, it is desirable that the external connection terminals 14 and the like are joined to a part of the conductor layer with a solder having a solid phase point of 240 ° C. or higher and 250 ° C. or lower.

また、この半導体装置は、半導体素子１１及び外部接続端子１４は、印刷配線板に対して図９とは上下逆に設置することも可能である。更に、半導体素子１１および外部接続端子１４を印刷配線板の下面に設置し、外部接続端子１４も半導体素子１１も印刷配線板の同じ下面に設置することも可能である。   In this semiconductor device, the semiconductor element 11 and the external connection terminal 14 can be installed upside down with respect to the printed wiring board as shown in FIG. Furthermore, the semiconductor element 11 and the external connection terminal 14 can be installed on the lower surface of the printed wiring board, and the external connection terminal 14 and the semiconductor element 11 can be installed on the same lower surface of the printed wiring board.

以上の工程で製造した半導体装置は、半導体素子１１を実装する印刷配線板が、第１の絶縁樹脂層の上層に第２絶縁樹脂層を有し、前記第１の絶縁樹脂層の下層と前記第２の絶縁樹脂層の上層の両面に同じ層数の第３の絶縁樹脂層を有し、前記両面の第３の絶縁樹脂層の外層の両面にソルダーレジストを有し、前記第２の絶縁樹脂層以上の絶縁樹脂層内のビアホールが上側の径が下側の径より大きい逆向きの円錐台形状のビアホールであり、前記第１の絶縁樹脂層以下の絶縁樹脂層のビアホールが上側の径が下側の径より小さい円錐台形状のビアホールである構造を有する。そのように、この半導体素子１１を実装する印刷配線板のビアホールの円錐台形状の向きが印刷配線板の層構造の中心層に対して非対称な向きに配置されている。そのため、この半導体装置をマザー基板に実装する熱応力が加わった際に、その半導体装置の印刷配線板は、層構造の中心層に対する非対称な構造を反映して、印刷配線板の同じ側の片側に反る傾向を持つ。それにより、反りの対策や補正および反りの管理が容易になる効果がある。   In the semiconductor device manufactured through the above steps, the printed wiring board on which the semiconductor element 11 is mounted has a second insulating resin layer above the first insulating resin layer, and the lower layer of the first insulating resin layer and the above A second insulating resin layer having the same number of third insulating resin layers on both surfaces; and a solder resist on both surfaces of the outer surfaces of the third insulating resin layers on both surfaces; The via hole in the insulating resin layer above the resin layer is a frustoconical via hole whose upper diameter is larger than the lower diameter, and the via hole of the insulating resin layer below the first insulating resin layer has an upper diameter. Is a frustoconical via hole smaller than the lower diameter. As such, the direction of the frustoconical shape of the via hole of the printed wiring board on which the semiconductor element 11 is mounted is arranged in an asymmetric direction with respect to the central layer of the layer structure of the printed wiring board. Therefore, when thermal stress is applied to mount this semiconductor device on the mother board, the printed wiring board of the semiconductor device reflects an asymmetric structure with respect to the central layer of the layer structure, and is on one side of the printed wiring board. Tend to warp. Thereby, there is an effect that the countermeasure and correction of the warp and the management of the warp become easy.

＜第２の実施形態＞
図１０と図１１により第２の実施形態を説明する。第２の実施形態が第１の実施形態と相違する点は、第２の実施形態では、第１の実施形態の工程１と工程２を１つの工程で行い、金属剥離体１ｆの外周接着部分１ｄに印刷配線板中間体８の表層の第１の絶縁樹脂層２を接着した点である。そして、外周接着部分１ｄ以外の部分である金属支持層１の外側の全面を第１の絶縁樹脂層２に接着し、その金属支持層１の内側の全面を金属剥離体１ｆに接して接着せずに保持し、この第１の絶縁樹脂層２を表層にした基板を中心にして印刷配線板中間体８を製造する。 <Second Embodiment>
A second embodiment will be described with reference to FIGS. 10 and 11. The second embodiment is different from the first embodiment in that, in the second embodiment, Step 1 and Step 2 of the first embodiment are performed in one step, and the outer peripheral adhesion portion of the metal peeling body 1f. The first insulating resin layer 2 on the surface layer of the printed wiring board intermediate 8 is adhered to 1d. Then, the entire outer surface of the metal support layer 1, which is a portion other than the outer peripheral bonding portion 1d, is bonded to the first insulating resin layer 2, and the entire inner surface of the metal support layer 1 is in contact with and adhered to the metal peeling body 1f. The printed wiring board intermediate body 8 is manufactured around the substrate having the first insulating resin layer 2 as a surface layer.

（工程１）
図１０のように、金属支持層１として金属箔を用い、金属剥離体１ｆとして金属板、例えば１２５μｍの銅板を用いる。金属剥離体１ｆは、過水硫酸系のソフトエッチング処理、または、研磨材によるバフ研磨やサンドブラスト処理、あるいは、酸化還元処理による黒化処理、ＣＺ処理で粗化処理する。次に、図１０（ａ）のように、第１の絶縁樹脂層２、それより小さい金属支持層１、金属支持層１より大きい金属剥離体１ｆ、金属支持層１、第１の絶縁樹脂層２の順で積み上げ、積層プレスで熱圧着して、図１０（ｂ）のように、第１の絶縁樹脂層２と金属剥離体１ｆを外周接着部分１ｄで接着して一体化させる。あるいは、例えば厚さ４５μｍのエポキシ樹脂の第１の絶縁樹脂層２を、金属支持層１、金属剥離体１ｆ、金属支持層１の両面にロールラミネートで熱圧着させても良い。金属支持層１は、例えば厚さが１２μｍの銅箔で、金属剥離体１ｆの寸法より３０ｍｍから６０ｍｍ程度小さいものを用い、金属剥離体１ｆの外周を金属剥離体１ｆの外周から１５ｍｍから３０ｍｍ内側に置く。積層プレスの加熱・加圧処理により、第１の絶縁樹脂層２が金属剥離体１ｆの外周接着部分１ｄに接着し、また、外周接着部分１ｄの内側の部分である金属支持層１ａの外側の全面を第１の絶縁樹脂層２で覆って接着する。その金属支持層１の内側の全面は金属剥離体１ｆに接して接着せずに保持する。 (Process 1)
As shown in FIG. 10, a metal foil is used as the metal support layer 1, and a metal plate, for example, a 125 μm copper plate is used as the metal strip 1f. The metal strip 1f is roughened by a perhydrosulfuric acid-based soft etching process, a buffing process using an abrasive or a sand blast process, a blackening process using an oxidation-reduction process, or a CZ process. Next, as shown in FIG. 10A, the first insulating resin layer 2, the metal support layer 1 smaller than that, the metal peeler 1f larger than the metal support layer 1, the metal support layer 1, and the first insulating resin layer. Then, the first insulating resin layer 2 and the metal strip 1f are bonded and integrated at the outer peripheral bonding portion 1d as shown in FIG. 10B. Alternatively, for example, the first insulating resin layer 2 of an epoxy resin having a thickness of 45 μm may be thermocompression bonded to both surfaces of the metal support layer 1, the metal release body 1 f, and the metal support layer 1 by roll lamination. The metal support layer 1 is, for example, a copper foil having a thickness of 12 μm and is 30 mm to 60 mm smaller than the dimension of the metal peeler 1f. The outer periphery of the metal peeler 1f is 15 mm to 30mm inside from the outer periphery of the metal peeler 1f. Put on. The first insulating resin layer 2 adheres to the outer peripheral adhesive portion 1d of the metal peeling body 1f by the heating / pressurizing process of the laminating press, and the outer side of the metal support layer 1a that is the inner portion of the outer peripheral adhesive portion 1d. The entire surface is covered with the first insulating resin layer 2 and bonded. The entire inner surface of the metal support layer 1 is held in contact with the metal strip 1f without being bonded.

また、第１の絶縁樹脂層２は、第１の実施形態の変形例２と同様にして、金属支持層１上にガラス繊維やガラスフレークやフィラーなどの補強材入り樹脂プリプレグを重ね、その上に厚さ１２μｍの銅箔を重ね合わせ、積層プレスで熱圧着させることで、銅箔付きの第１の絶縁樹脂層２を金属支持層１に接着して形成することができる。そして、その外側の銅箔を塩化第二鉄水溶液などのエッチング液で全面エッチングして第１の絶縁樹脂層２の表面を露出させる。   In addition, the first insulating resin layer 2 is formed by stacking a resin prepreg containing a reinforcing material such as glass fiber, glass flake, or filler on the metal support layer 1 in the same manner as in the second modification of the first embodiment. The first insulating resin layer 2 with the copper foil can be adhered to the metal support layer 1 by superimposing a 12 μm thick copper foil on each other and thermocompression bonding with a laminating press. Then, the entire outer surface of the copper foil is etched with an etchant such as a ferric chloride aqueous solution to expose the surface of the first insulating resin layer 2.

また、金属支持層１の銅箔の粗面（マット面）は外側に向けて積層する。しかし、マット面の凹凸が大きいため第１の絶縁樹脂層２の表面のプロファイルに与える影響を懸念する場合は、金属支持層１の銅箔のマット面を内側に向けて金属剥離体１ｆの両面に金属支持層１を密着させ、金属支持層１の外側の面を過水硫酸系のソフトエッチング処理等で最適な凹凸が得られる処理を行う。   The rough surface (matte surface) of the copper foil of the metal support layer 1 is laminated outward. However, since the mat surface has large irregularities, if there is a concern about the influence on the profile of the surface of the first insulating resin layer 2, the mat surface of the copper foil of the metal support layer 1 faces inward and both surfaces of the metal release body 1 f are placed. The metal support layer 1 is brought into close contact with the surface, and the outer surface of the metal support layer 1 is subjected to a treatment for obtaining optimum unevenness by a perhydrosulfuric acid based soft etching treatment or the like.

（工程２）
次に、第１の実施形態の工程３から工程１３までの処理と同様に処理して、図１０（ｃ）のように、金属剥離体１ｆの両面に第１の絶縁樹脂層２と、第２の絶縁樹脂層２−２と第２の導体層６−２が交互に重ねられ、外層が絶縁樹脂層２−４で覆われた基板を形成する。 (Process 2)
Next, processing is performed in the same manner as the processing from step 3 to step 13 of the first embodiment, and as shown in FIG. 10C, the first insulating resin layer 2 and the first Two insulating resin layers 2-2 and second conductor layers 6-2 are alternately stacked, and a substrate is formed in which the outer layer is covered with the insulating resin layer 2-4.

（工程３）
次に、図１１（ｄ）のように、金属剥離体１ｆの端部から金属支持層１の端部までの１５ｍｍから３０ｍｍ程度の外周接着部分１ｄをルーターやプレス加工等の機械加工で切断し、金属支持層１と金属剥離体１ｆの接触部分の外周を露出させた外周露出部１ｅを形成する。次に、図１１（ｅ）のように、金属剥離体１ｆの外側の２組の、金属支持層１を含む上側の部分の金属支持層１付き基板と、下側の金属支持層１付き基板を分離する。
（工程４）
次に、図１１（ｆ）のように、銅の金属支持層１をエッチングし除去し両面を第１の絶縁樹脂層２と絶縁樹脂層２−４で被覆した印刷配線板中間体８を製造する。この際に用いるエッチング溶液として、例えばアンモニアを主成分としたアルカリエッチング液などを使用できる。あるいは、第二塩化鉄水溶液または第二塩化銅水溶液を使用しても良い。ここで、金属支持層１として厚さ１２μｍの銅箔を用いることで、金属支持層１のエッチング処理の時間をきわめて短時間で済ませることができる効果がある。 (Process 3)
Next, as shown in FIG. 11 (d), an outer peripheral adhesive portion 1d of about 15 mm to 30 mm from the end of the metal strip 1f to the end of the metal support layer 1 is cut by machining such as router or pressing. Then, the outer periphery exposed portion 1e is formed by exposing the outer periphery of the contact portion between the metal support layer 1 and the metal strip 1f. Next, as shown in FIG. 11 (e), two sets of the substrate with metal support layer 1 on the upper side including the metal support layer 1 and the substrate with metal support layer 1 on the lower side of the metal peeling body 1f. Isolate.
(Process 4)
Next, as shown in FIG. 11 (f), the printed metal board intermediate body 8 is manufactured by etching and removing the copper metal support layer 1 and covering both surfaces with the first insulating resin layer 2 and the insulating resin layer 2-4. To do. As an etching solution used at this time, for example, an alkaline etching solution mainly containing ammonia can be used. Alternatively, a ferric chloride aqueous solution or a cupric chloride aqueous solution may be used. Here, by using a copper foil having a thickness of 12 μm as the metal support layer 1, there is an effect that the etching time of the metal support layer 1 can be made extremely short.

（工程５）
次に、第１の実施形態の工程１６から工程２３により印刷配線板を製造し、工程２４から工程２５により半導体装置を製造する。 (Process 5)
Next, a printed wiring board is manufactured by steps 16 to 23 of the first embodiment, and a semiconductor device is manufactured by steps 24 to 25.

＜第３の実施形態＞
図１２と図１３により第３の実施形態を説明する。第３の実施形態が第１および第２の実施形態と相違する点は、第１の実施形態の工程１と工程２を１つの工程で行うとともに、上下の印刷配線板中間体８の第１の絶縁樹脂層２の外周接着部分１ｄを接着した点である。外周接着部分１ｄ以外の部分である金属箔の金属支持層１の外側の全面を第１の絶縁樹脂層２に接着し、その金属支持層１の内側の全面は接着せずに、他方の金属支持層１に接して保持する点が第２の実施形態と相違する。そして、この第１の絶縁樹脂層２を表層にした基板を中心にして印刷配線板中間体８を製造する。 <Third Embodiment>
A third embodiment will be described with reference to FIGS. The third embodiment is different from the first and second embodiments in that the steps 1 and 2 of the first embodiment are performed in one step, and the upper and lower printed wiring board intermediates 8 are the first. This is a point where the outer peripheral adhesive portion 1d of the insulating resin layer 2 is adhered. The entire outer surface of the metal support layer 1 of the metal foil other than the outer peripheral bonding portion 1d is bonded to the first insulating resin layer 2, and the entire inner surface of the metal support layer 1 is not bonded, but the other metal The point of holding in contact with the support layer 1 is different from the second embodiment. And the printed wiring board intermediate body 8 is manufactured centering on the board | substrate which made this 1st insulating resin layer 2 the surface layer.

（工程１）
第３の実施形態では、金属支持層１として金属箔を用い、図１２（ａ）のように、第１の絶縁樹脂層２、それより小さい金属支持層１、金属支持層１、第１の絶縁樹脂層２の順で積み上げ、積層プレスで熱圧着して、図１２（ｂ）のように、上下の第１の絶縁樹脂層２を外周接着部分１ｄで接着させて一体化させる。あるいは、例えば厚さ４５μｍのエポキシ樹脂の第１の絶縁樹脂層２を、金属支持層１、金属支持層１の両面にロールラミネートで熱圧着させても良い。金属支持層１の金属箔は、例えば厚さが１２μｍの銅箔で、金属剥離体１ｆの寸法より３０ｍｍから６０ｍｍ程度小さいものを用い、金属支持層１の外周を金属剥離体１ｆの内側に１５ｍｍから３０ｍｍ程度の位置に置く。積層プレスの加熱・加圧処理により、上下の第１の絶縁樹脂層２がその外周から金属支持層１ａの外周までの外周接着部分１ｄで接着し、金属支持層１ａの全面に第１の絶縁樹脂層２を接着する。金属支持層１ａの内側の全面は他方の金属支持層１に接するのみで接着しないで保持する。 (Process 1)
In the third embodiment, a metal foil is used as the metal support layer 1, and as shown in FIG. 12A, the first insulating resin layer 2, the smaller metal support layer 1, the metal support layer 1, the first The insulating resin layers 2 are stacked in this order and are thermocompression bonded with a lamination press, and the upper and lower first insulating resin layers 2 are bonded and integrated at the outer peripheral bonding portion 1d as shown in FIG. Alternatively, for example, the first insulating resin layer 2 made of an epoxy resin having a thickness of 45 μm may be thermocompression bonded to both the metal support layer 1 and the metal support layer 1 by roll lamination. The metal foil of the metal support layer 1 is, for example, a copper foil having a thickness of 12 μm and is 30 mm to 60 mm smaller than the dimension of the metal release body 1f. The outer periphery of the metal support layer 1 is 15 mm inside the metal release body 1f. To about 30 mm. The upper and lower first insulating resin layers 2 are bonded by the outer peripheral adhesive portion 1d from the outer periphery to the outer periphery of the metal support layer 1a by the heating and pressurizing treatment of the laminating press, and the first insulating resin layer 1a is entirely covered with the first insulating layer. The resin layer 2 is bonded. The entire inner surface of the metal support layer 1a is held in contact with the other metal support layer 1 without being bonded.

また、第１の絶縁樹脂層２は、第２の実施形態と同様にして、金属支持層１上にガラス繊維やガラスフレークやフィラーなどの補強材入り樹脂プリプレグを重ね、その上に厚さ１２μｍの銅箔を重ね合わせ、積層プレスで熱圧着させることで、銅箔付きの第１の絶縁樹脂層２を金属支持層１に接着して形成することができる。そして、その外側の銅箔を塩化第二鉄水溶液などのエッチング液で全面エッチングして第１の絶縁樹脂層２の表面を露出させる。   Further, in the same manner as in the second embodiment, the first insulating resin layer 2 is formed by stacking a resin prepreg containing a reinforcing material such as glass fiber, glass flake, or filler on the metal support layer 1, and having a thickness of 12 μm thereon. The first insulating resin layer 2 with the copper foil can be adhered and formed on the metal support layer 1 by stacking the copper foils and thermocompression bonding with a lamination press. Then, the entire outer surface of the copper foil is etched with an etchant such as a ferric chloride aqueous solution to expose the surface of the first insulating resin layer 2.

また、金属支持層１の銅箔の粗面（マット面）は外側に向けて積層する。しかし、マット面の凹凸が大きいため第１の絶縁樹脂層２の表面のプロファイルに与える影響を懸念する場合は、金属支持層１の銅箔のマット面を内側に向けて対向する金属支持層１と密着させ、金属支持層１の外側の面を過水硫酸系のソフトエッチング処理等で最適な凹凸が得られる処理を行う。   The rough surface (matte surface) of the copper foil of the metal support layer 1 is laminated outward. However, if the mat surface has large irregularities, if there is concern about the effect on the profile of the surface of the first insulating resin layer 2, the metal support layer 1 that faces the mat surface of the copper foil of the metal support layer 1 facing inward. Then, the outer surface of the metal support layer 1 is subjected to a process for obtaining optimum unevenness by a perhydrosulfuric acid based soft etching process or the like.

（工程２）
次に、第１の実施形態の工程３から工程１３までの処理と同様に処理して、図１２（ｃ）のように、一対の金属支持層１の外側の両面に第１の絶縁樹脂層２と、第２の絶縁樹脂層２−２と第２の導体層６−２が交互に重ねられ、外層が絶縁樹脂層２−４で覆われた基板を形成する。 (Process 2)
Next, the first insulating resin layer is formed on both the outer surfaces of the pair of metal support layers 1 as shown in FIG. 2, the second insulating resin layer 2-2 and the second conductor layer 6-2 are alternately stacked, and the outer layer is covered with the insulating resin layer 2-4.

（工程３）
次に、図１３（ｄ）のように、基板の外周から金属支持層１の端部までの１５ｍｍから３０ｍｍの外周接着部分１ｄをルーターやプレス加工等の機械加工で切断し、金属支持層１の接触部分の外周を露出させた外周露出部１ｅを形成する。次に、図１３（ｅ）のように２組の、金属支持層１を含む上側の部分の金属支持層１付き基板と、下側の金属支持層１付き基板に分割する。
（工程４）
次に、図１３（ｆ）のように、銅の金属支持層１をエッチングし除去し両面を第１の絶縁樹脂層２と絶縁樹脂層２−４で被覆した印刷配線板中間体８を製造する。この際に用いるエッチング溶液として、例えばアンモニアを主成分としたアルカリエッチング液などを使用できる。あるいは、第二塩化鉄水溶液または第二塩化銅水溶液を使用しても良い。ここで、金属支持層１として厚さ１２μｍの銅箔を用いることで、金属支持層１のエッチング処理の時間をきわめて短時間で済ませることができる効果がある。 (Process 3)
Next, as shown in FIG. 13 (d), the outer peripheral adhesion portion 1d from 15 mm to 30 mm from the outer periphery of the substrate to the end of the metal support layer 1 is cut by a mechanical process such as a router or a press process, and the metal support layer 1 The outer periphery exposed portion 1e is formed by exposing the outer periphery of the contact portion. Next, as shown in FIG. 13 (e), the substrate is divided into two sets, a substrate with the metal support layer 1 in the upper part including the metal support layer 1 and a substrate with the lower metal support layer 1.
(Process 4)
Next, as shown in FIG. 13 (f), the printed metal board intermediate 8 in which the copper metal support layer 1 is removed by etching and the both surfaces are covered with the first insulating resin layer 2 and the insulating resin layer 2-4 is manufactured. To do. As an etching solution used at this time, for example, an alkaline etching solution mainly containing ammonia can be used. Alternatively, a ferric chloride aqueous solution or a cupric chloride aqueous solution may be used. Here, by using a copper foil having a thickness of 12 μm as the metal support layer 1, there is an effect that the etching time of the metal support layer 1 can be made extremely short.

（工程５）
次に、第１の実施形態の工程１６から工程２３により印刷配線板を製造し、工程２４から工程２５により半導体装置を製造する。 (Process 5)
Next, a printed wiring board is manufactured by steps 16 to 23 of the first embodiment, and a semiconductor device is manufactured by steps 24 to 25.

本発明の第１の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 1st Embodiment of this invention. 本発明の第１の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 1st Embodiment of this invention. 本発明の第１の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 1st Embodiment of this invention. 本発明の第１の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 1st Embodiment of this invention. 本発明の第１の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 1st Embodiment of this invention. 本発明の第１の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 1st Embodiment of this invention. 本発明の第１の実施形態の印刷配線板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board of the 1st Embodiment of this invention. 本発明の第１の実施形態の印刷配線板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board of the 1st Embodiment of this invention. 本発明の第１の実施形態の半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device of the 1st Embodiment of this invention. 本発明の第２の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 2nd Embodiment of this invention. 本発明の第２の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 2nd Embodiment of this invention. 本発明の第３の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 3rd Embodiment of this invention. 本発明の第３の実施形態の印刷配線板中間体の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the printed wiring board intermediate body of the 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１・・・金属支持層
１ａ・・・金属剥離層
１ｂ・・・接着剤層
１ｃ・・・支持体
１ｄ・・・外周接着部分
１ｅ・・・外周露出部
１ｆ・・・金属剥離体
２、２−２、２−３、２−４、２−５、２−６・・・絶縁樹脂層
３・・・めっき下地導電層
４・・・めっきレジスト
５・・・配線パターン部分
６、６−１、６−２、６−３、６−４、６−５、６−６・・・配線パターン
７・・・ビアホール下穴
７−１、７−２、７−３、７−４、７−５、７−６・・・ビアホール
８・・・印刷配線板中間体
９・・・ソルダーレジスト
１０・・・外部電極パッド用開口部
１０−１、１０−２・・・外部電極パッド
１１・・・半導体素子
１２・・・バンプ
１３・・・封止樹脂
１４・・・外部接続端子 DESCRIPTION OF SYMBOLS 1 ... Metal support layer 1a ... Metal peeling layer 1b ... Adhesive layer 1c ... Support body 1d ... Outer periphery adhesion part 1e ... Outer periphery exposure part 1f ... Metal peeling body 2, 2-2, 2-3, 2-4, 2-5, 2-6 ... insulating resin layer 3 ... plating base conductive layer 4 ... plating resist 5 ... wiring pattern portion 6, 6- 1, 6-2, 6-3, 6-4, 6-5, 6-6 ... wiring pattern 7 ... via hole pilot holes 7-1, 7-2, 7-3, 7-4, 7 -5, 7-6 ... via hole 8 ... printed wiring board intermediate 9 ... solder resist 10 ... external electrode pad openings 10-1, 10-2 ... external electrode pad 11 ..Semiconductor element 12 ... Bump 13 ... Sealing resin 14 ... External connection terminal

Claims (8)

厚さ０．０５ｍｍから０．２ｍｍのプリプレグから成る接着剤層の両面に前記接着剤層より小さい金属剥離層を該金属剥離層の粗面を前記接着剤層側に向けて設置し、前記金属剥離層の外側の両面に前記金属剥離層よりも大きい金属支持層を重ねて加熱・加圧することで両面の前記金属支持層の外周接着部分を前記接着剤層で接着した支持体を形成する第１の工程と、前記支持体の両面の前記金属支持層の外側に第１の絶縁樹脂層と第１の配線パターンを形成する第２の工程と、両面の前記第１の配線パターンの外側に絶縁樹脂層とビアホールと配線パターンとその外側の絶縁樹脂層を逐次形成する第３の工程と、前記外周接着部分を切断することで前記支持体から前記金属支持層付き基板を分離する第４の工程と、前記金属支持層付き基板から前記金属支持層を除去することで印刷配線板中間体を形成する第５の工程と、前記印刷配線板中間体の両面にビアホールと配線パターンを形成する第６の工程を有することを特徴とする印刷配線板の製造方法。 A metal release layer smaller than the adhesive layer is placed on both sides of an adhesive layer made of a prepreg having a thickness of 0.05 mm to 0.2 mm, with the rough surface of the metal release layer facing the adhesive layer side, and the metal A metal support layer larger than the metal release layer is stacked on both sides of the release layer and heated and pressed to form a support in which the outer peripheral adhesion portions of the metal support layers on both sides are bonded with the adhesive layer. A first step, a second step of forming a first insulating resin layer and a first wiring pattern outside the metal support layer on both sides of the support, and an outer side of the first wiring pattern on both sides. A third step of sequentially forming an insulating resin layer, a via hole, a wiring pattern, and an insulating resin layer outside the insulating resin layer; and a fourth step of separating the substrate with the metal support layer from the support by cutting the outer peripheral adhesive portion. Process and substrate with metal support layer A fifth step of forming a printed wiring board intermediate by removing the metal support layer, and a sixth step of forming a via hole and a wiring pattern on both surfaces of the printed wiring board intermediate. A printed wiring board manufacturing method. 金属剥離体の両面に前記金属剥離体より小さい金属支持層を、粗面を外側に向けて重ねて設置し、前記金属支持層の外側の両面に前記金属支持層より大きいプリプレグから成る第１の絶縁樹脂層を重ねて加熱・加圧することで両面の前記第１の絶縁樹脂層の外周接着部分を前記金属剥離体に接着させる第１の工程と、前記第１の絶縁樹脂層の外側に第１の配線パターンを形成する第２の工程と、両面の前記第１の配線パターンの外側に絶縁樹脂層とビアホールと配線パターンとその外側の絶縁樹脂層を逐次形成する第３の工程と、前記外周接着部分を切断することで前記金属剥離体から前記金属支持層付き基板を分離する第４の工程と、前記金属支持層付き基板から前記金属支持層を除去した印刷配線板中間体を形成する第５の工程と、前記印刷配線板中間体の両面にビアホールと配線パターンを形成する第６の工程を有することを特徴とする印刷配線板の製造方法。 A metal support layer smaller than the metal release body is disposed on both surfaces of the metal release body, with a rough surface facing outward, and a first prepreg made of a prepreg larger than the metal support layer on both outer surfaces of the metal support layer. A first step of bonding the outer peripheral adhesion portions of the first insulating resin layers on both sides to the metal peeler by overlapping and heating and pressurizing the insulating resin layers; and a first step outside the first insulating resin layers. A second step of forming one wiring pattern, a third step of sequentially forming an insulating resin layer, a via hole, a wiring pattern, and an insulating resin layer on the outside of the first wiring pattern on both sides, A fourth step of separating the substrate with the metal support layer from the metal release body by cutting an outer peripheral adhesive portion, and a printed wiring board intermediate in which the metal support layer is removed from the substrate with the metal support layer are formed. A fifth step, Method of manufacturing a printed wiring board characterized by having a sixth step of forming a via hole and wiring pattern on both surfaces of the printing wiring board intermediate. 粗面を外側に向けて重ねた第１の金属支持層と第２の金属支持層の外側の両面に、前記第１の金属支持層及び第２の金属支持層より大きいプリプレグから成る第１の絶縁樹脂層を重ねて加熱・加圧することで両面の前記金属支持層の外周より外側で両面の前記第１の絶縁樹脂層が接着した外周接着部分を形成した支持体を形成する第１の工程と、前記第１の絶縁樹脂層の外側に第１の配線パターンを形成する第２の工程と、両面の前記第１の配線パターンの外側に絶縁樹脂層とビアホールと配線パターンとその外側の絶縁樹脂層を逐次形成する第３の工程と、前記外周接着部分を切断することで前記第１の金属支持層を有する金属支持層付き基板と前記第２の金属支持層を有する金属支持層付き基板を分離する第４の工程と、前記金属支持層付き基板から前記金属支持層を除去した印刷配線板中間体A first metal support layer made of a prepreg larger than the first metal support layer and the second metal support layer is formed on both outer surfaces of the first metal support layer and the second metal support layer with the rough surfaces facing outward. A first step of forming a support body in which an outer peripheral adhesion portion in which the first insulating resin layers on both sides are bonded is formed outside the outer periphery of the metal support layers on both sides by overlapping and heating and pressurizing the insulating resin layers. A second step of forming a first wiring pattern on the outside of the first insulating resin layer; an insulating resin layer, a via hole, a wiring pattern, and insulation on the outside of the first wiring pattern on both sides; A third step of sequentially forming a resin layer, a substrate with a metal support layer having the first metal support layer by cutting the outer peripheral adhesive portion, and a substrate with a metal support layer having the second metal support layer A fourth step of separating the metal support layer and the metal support layer Printed circuit board intermediate the come substrate to remove the metal supporting layer
を形成する第５の工程と、前記印刷配線板中間体の両面にビアホールと配線パターンを形成する第６の工程を有することを特徴とする印刷配線板の製造方法。And a sixth step of forming via holes and a wiring pattern on both surfaces of the printed wiring board intermediate body. 前記第１の絶縁樹脂層を、補強材入り樹脂プリプレグを用いて形成することを特徴とする請求項１記載の印刷配線板の製造方法。 The method for producing a printed wiring board according to claim 1, wherein the first insulating resin layer is formed using a resin prepreg with a reinforcing material. 前記第６の工程の次に、前記印刷配線板中間体の両面の外側に絶縁樹脂層とビアホールと配線パターンを逐次形成する第７の工程を有することを特徴とする請求項１乃至４の何れか一項記載の印刷配線板の製造方法。   5. The method according to claim 1, further comprising a seventh step of sequentially forming an insulating resin layer, a via hole, and a wiring pattern on both sides of the printed wiring board intermediate body after the sixth step. A method for producing a printed wiring board according to claim 1. 前記第７の工程において、最外層の絶縁樹脂層を補強材無しの絶縁樹脂層で形成することを特徴とする請求項５記載の印刷配線板の製造方法。   6. The method of manufacturing a printed wiring board according to claim 5, wherein in the seventh step, the outermost insulating resin layer is formed of an insulating resin layer without a reinforcing material. 前記印刷配線板の最外層の外層配線パターンの外側に外部電極パッド用開口部を有するソルダーレジストを形成する第８の工程を有することを特徴とする請求項１乃至６の何れか一項記載の印刷配線板の製造方法。   7. The method according to claim 1, further comprising an eighth step of forming a solder resist having an opening for an external electrode pad on the outside of the outermost wiring pattern of the outermost layer of the printed wiring board. Manufacturing method of printed wiring board. 前記ソルダーレジストの前記外部電極パッド用開口部に露出した前記外層配線パターンに固相点が２４０℃以上で２５０℃以下のはんだで外部接続端子をはんだ付けする第９の工程を有することを特徴とする請求項７記載の印刷配線板の製造方法。   It has a ninth step of soldering external connection terminals to the outer layer wiring pattern exposed in the external electrode pad opening of the solder resist with a solder having a solid phase point of 240 ° C. or higher and 250 ° C. or lower. The manufacturing method of the printed wiring board of Claim 7.
JP2007259464A 2007-10-03 2007-10-03 Method for manufacturing printed wiring board Expired - Fee Related JP5092662B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007259464A JP5092662B2 (en) 2007-10-03 2007-10-03 Method for manufacturing printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007259464A JP5092662B2 (en) 2007-10-03 2007-10-03 Method for manufacturing printed wiring board

Publications (2)

Publication Number Publication Date
JP2009088429A JP2009088429A (en) 2009-04-23
JP5092662B2 true JP5092662B2 (en) 2012-12-05

Family

ID=40661419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007259464A Expired - Fee Related JP5092662B2 (en) 2007-10-03 2007-10-03 Method for manufacturing printed wiring board

Country Status (1)

Country Link
JP (1) JP5092662B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899239B2 (en) 2015-11-06 2018-02-20 Apple Inc. Carrier ultra thin substrate

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI390692B (en) * 2009-06-23 2013-03-21 Unimicron Technology Corp Package substrate and base therefor and fabrication method thereof
KR101044177B1 (en) 2009-10-09 2011-06-24 삼성전기주식회사 A carrier member for manufacturing a substrate and a method of manufacturing a substrate using the same
KR101044197B1 (en) 2009-11-12 2011-06-28 삼성전기주식회사 A method of manufacturing a printed circuit board
KR101055571B1 (en) 2009-11-30 2011-08-08 삼성전기주식회사 Carrier member for substrate manufacturing and method for manufacturing substrate using same
KR101101496B1 (en) 2009-11-30 2012-01-03 삼성전기주식회사 carrier for manufacturing wiring substrate and method of manufacturing wiring substrate using the same
KR101055455B1 (en) 2009-11-30 2011-08-08 삼성전기주식회사 Carrier member for substrate manufacturing and method for manufacturing substrate using same
KR101055473B1 (en) * 2009-12-15 2011-08-08 삼성전기주식회사 Carrier member for substrate manufacturing and method for manufacturing substrate using same
KR101055462B1 (en) * 2010-01-07 2011-08-08 삼성전기주식회사 Carrier for manufacturing printed circuit board, manufacturing method thereof and manufacturing method of printed circuit board using same
KR101109234B1 (en) * 2010-01-07 2012-01-30 삼성전기주식회사 A carrier for manufacturing a printed circuit board and a method of manufacturing the same and a method of manufacturing a printed circuit board using the same
KR101167422B1 (en) * 2010-09-15 2012-07-19 삼성전기주식회사 Carrier member and method of manufacturing PCB using the same
JP5606268B2 (en) * 2010-10-27 2014-10-15 日本特殊陶業株式会社 Manufacturing method of multilayer wiring board
KR101282965B1 (en) * 2010-11-05 2013-07-08 주식회사 두산 Novel printed circuit board and method of producing the same
JP6081693B2 (en) * 2011-09-12 2017-02-15 新光電気工業株式会社 Wiring board and method of manufacturing wiring board
JP5902931B2 (en) * 2011-12-06 2016-04-13 新光電気工業株式会社 WIRING BOARD MANUFACTURING METHOD AND WIRING BOARD MANUFACTURING SUPPORT
JP6057641B2 (en) 2012-09-20 2017-01-11 新光電気工業株式会社 Wiring board and manufacturing method thereof
JP6092555B2 (en) 2012-09-24 2017-03-08 新光電気工業株式会社 Wiring board manufacturing method
KR101884430B1 (en) * 2012-10-15 2018-08-01 삼성전기주식회사 Multi-layer type printed circuit board and Method of manufacturing the same
DE102017121015A1 (en) * 2017-09-12 2019-03-14 Rogers Germany Gmbh Adapter element for connecting a component such as a laser diode to a heat sink, a system of a laser diode, a heat sink and an adapter element and method for producing an adapter element

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3811680B2 (en) * 2003-01-29 2006-08-23 富士通株式会社 Wiring board manufacturing method
JP2004048072A (en) * 2003-10-24 2004-02-12 Ngk Spark Plug Co Ltd Resin wiring board and its manufacture
JP4445778B2 (en) * 2004-02-27 2010-04-07 日本特殊陶業株式会社 Wiring board manufacturing method
JP4072176B2 (en) * 2005-08-29 2008-04-09 新光電気工業株式会社 Manufacturing method of multilayer wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899239B2 (en) 2015-11-06 2018-02-20 Apple Inc. Carrier ultra thin substrate

Also Published As

Publication number Publication date
JP2009088429A (en) 2009-04-23

Similar Documents

Publication Publication Date Title
JP5092662B2 (en) Method for manufacturing printed wiring board
JP5092547B2 (en) Method for manufacturing printed wiring board
US8959760B2 (en) Printed wiring board and method for manufacturing same
KR101475109B1 (en) Multilayer Wiring Substrate and Method of Manufacturing the Same
JP4866268B2 (en) Wiring board manufacturing method and electronic component device manufacturing method
US7595228B2 (en) Method for manufacturing electronic component-mounted board
JP5526746B2 (en) Multilayer substrate manufacturing method and supporting substrate
US9253897B2 (en) Wiring substrate and method for manufacturing the same
JP2010251688A (en) Component built-in printed wiring board and manufacturing method of the same
JP2009032918A (en) Wiring substrate, manufacturing method thereof, electronic component device, and manufacturing method thereof
WO2007069789A1 (en) Multilayer printed wiring plate, and method for fabricating the same
JP2010267948A (en) Coreless packaging substrate and method for manufacturing the same
US20120186863A1 (en) Multilayer wiring board
TW201334647A (en) Multi-layer wiring substrate and method for manufacturing the same
JP5221887B2 (en) Wiring board manufacturing method
JP2010226075A (en) Wiring board and method for manufacturing the same
JP3999784B2 (en) Manufacturing method of electronic component mounting board
JP6417142B2 (en) Semiconductor device and manufacturing method thereof
US11516910B1 (en) Circuit board structure and manufacturing method thereof
TW201927090A (en) Wiring board and manufacturing method thereof
JP2004055777A (en) Method for manufacturing compound multilayer wiring board
JP2005005545A (en) Semiconductor device manufacturing method
JP4779619B2 (en) Support plate, multilayer circuit wiring board, and semiconductor package using the same
JP7052464B2 (en) Manufacturing method of coreless substrate with fine wiring layer and manufacturing method of semiconductor package
CN102686024A (en) Multilayer wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100908

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20110224

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120113

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120117

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120305

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120821

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120903

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150928

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees