JP5087302B2 - 回路装置およびその製造方法 - Google Patents
回路装置およびその製造方法 Download PDFInfo
- Publication number
- JP5087302B2 JP5087302B2 JP2007089830A JP2007089830A JP5087302B2 JP 5087302 B2 JP5087302 B2 JP 5087302B2 JP 2007089830 A JP2007089830 A JP 2007089830A JP 2007089830 A JP2007089830 A JP 2007089830A JP 5087302 B2 JP5087302 B2 JP 5087302B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- electrode
- circuit device
- wiring board
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図2を参照して本実施の形態の回路装置の製造方法について説明する。
Claims (5)
- 配線基板と、
前記配線基板に形成された凹部に設けられた回路素子と、
前記配線基板の凹部の周囲に設けられた基板電極と、
前記凹部の底面側と反対側の前記回路素子の上に設けられた素子電極と、
前記基板電極および前記素子電極と電気的に接続する導電性の突起部がそれぞれ一体的に形成された配線層を有する配線部と、
を備え、
前記素子電極の高さと、前記基板電極の高さがほぼ等しいことを特徴とする回路装置。 - 前記配線部の材料が圧延銅板であることを特徴とする請求項1に記載の回路装置。
- 前記配線基板と前記配線部との間に、加圧により塑性流動を起こす絶縁樹脂が設けられていることを特徴とする請求項1または2に記載の回路装置。
- 配線基板に設けられた凹部に回路素子を嵌め込む工程と、
前記凹部の周囲に位置し、前記配線基板の表面に設けられた基板電極と、前記回路素子の表面に設けられた素子電極とを、前記基板電極および前記素子電極にそれぞれ対応する導電性の突起部が一体的に形成された配線層からなる配線部を用いて電気的に接続する工程と、
を備え、
前記回路素子を嵌め込む工程において前記素子電極の高さと、前記基板電極の高さがほぼ等しくなるようにすることを特徴とする回路装置の製造方法。 - 前記配線部を用いて前記素子電極と前記基板電極とを電気的に接続する工程において、
加圧により塑性流動を起こす絶縁層を介して前記配線部を圧着することにより、前記素子電極と前記基板電極に前記配線部が有する前記突起部がそれぞれ接続されることを特徴とする請求項4に記載の回路装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007089830A JP5087302B2 (ja) | 2007-03-29 | 2007-03-29 | 回路装置およびその製造方法 |
US12/078,311 US20090057903A1 (en) | 2007-03-29 | 2008-03-28 | Semiconductor module, method for manufacturing semiconductor modules, semiconductor apparatus, method for manufacturing semiconductor apparatuses, and portable device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007089830A JP5087302B2 (ja) | 2007-03-29 | 2007-03-29 | 回路装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008251745A JP2008251745A (ja) | 2008-10-16 |
JP5087302B2 true JP5087302B2 (ja) | 2012-12-05 |
Family
ID=39976363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007089830A Expired - Fee Related JP5087302B2 (ja) | 2007-03-29 | 2007-03-29 | 回路装置およびその製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP5087302B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5130177B2 (ja) | 2008-09-29 | 2013-01-30 | 住友重機械工業株式会社 | 減速装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4208631B2 (ja) * | 2003-04-17 | 2009-01-14 | 日本ミクロン株式会社 | 半導体装置の製造方法 |
JP2004335641A (ja) * | 2003-05-06 | 2004-11-25 | Canon Inc | 半導体素子内蔵基板の製造方法 |
JP4792749B2 (ja) * | 2005-01-14 | 2011-10-12 | 大日本印刷株式会社 | 電子部品内蔵プリント配線板の製造方法 |
JP2006245453A (ja) * | 2005-03-07 | 2006-09-14 | Three M Innovative Properties Co | フレキシブルプリント回路基板の他の回路基板への接続方法 |
JP2006310530A (ja) * | 2005-04-28 | 2006-11-09 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
-
2007
- 2007-03-29 JP JP2007089830A patent/JP5087302B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2008251745A (ja) | 2008-10-16 |
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