JP5087118B2 - 通信機器 - Google Patents
通信機器 Download PDFInfo
- Publication number
- JP5087118B2 JP5087118B2 JP2010216711A JP2010216711A JP5087118B2 JP 5087118 B2 JP5087118 B2 JP 5087118B2 JP 2010216711 A JP2010216711 A JP 2010216711A JP 2010216711 A JP2010216711 A JP 2010216711A JP 5087118 B2 JP5087118 B2 JP 5087118B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring
- antenna
- electrode
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6688—Mixed frequency adaptations, i.e. for operation at different frequencies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
- Details Of Aerials (AREA)
- Transceivers (AREA)
Description
(第1の実施形態)
図1は、第1の実施形態に係る通信機器1の断面透視図である。図2は、第1の実施形態に係る半導体チップ20の回路構成図である。図3〜図5は、第1の実施形態に係る通信機器の上面透過図である。以下、図1〜図5を参照して、この第1の実施形態に係る通信機器1について説明する。
図6及び図7は、第2の実施形態に係る通信機器2の上面透過図である。以下、図6及び図7を参照して、第2の実施形態に係る通信機器2の構成について説明するが、図1で説明した構成と同じ構成には同一の符号を付して説明を省略する。
図8は、第3の実施形態に係る通信機器3の上面透過図である。以下、図8を参照して、第3の実施形態に係る通信機器3の構成について説明するが、図1で説明した構成と同じ構成には同一の符号を付して説明を省略する。
図9,10は、第4の実施形態に係る通信機器4の裏面図である。以下、図9,10を参照して、第4の実施形態に係る通信機器4の構成について説明するが、図1で説明した構成と同じ構成には同一の符号を付して説明を省略する。なお、図9,10には、実装基板30の表面に実装されている半導体チップ20を破線で図示した。
図11は、第5の実施形態に係る通信機器5の断面透視図である。図12は、第5の実施形態に係る通信機器5の上面透過図である。以下、図11及び図12を参照して、第5の実施形態に係る通信機器5の構成について説明するが、図1で説明した構成と同じ構成には同一の符号を付して説明を省略する。
図13は、第6の実施形態に係る通信機器6の断面透視図である。図14は、第6の実施形態に係る通信機器6の上面透過図である。以下、図13及び図14を参照して、第6の実施形態に係る通信機器6の構成について説明するが、図1で説明した構成と同じ構成には同一の符号を付して説明を省略する。
なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。
Claims (8)
- 高周波信号を送受信するアンテナと、
前記高周波信号を処理する矩形状の半導体チップと、
グラウンドに接続される第1の配線、前記半導体チップへ電源を供給する第2の配線、半導体チップの保護素子に接続される第3の配線、および前記半導体チップからの信号を伝送する第4の配線がめっきにより形成され、前記半導体チップを実装する基板と、
を備え、
前記基板は、半導体実装面である基板主面に前記第1ないし第4の配線の先端に形成され、前記第1ないし第4の配線を半導体チップへ接続するための第1ないし第4の基板主面電極及び半導体実装面と逆の基板裏面に前記第1ないし第4の配線の先端に形成され、前記第1ないし第4の配線を外部装置へ接続するための第1ないし第4の基板裏面電極をさらに有し、
前記第1ないし第3の配線のうちの少なくとも一つが、前記基板端縁部まで延長して形成された前記めっき処理を行うためのめっき用延長配線を有し、前記第4の配線のうちの少なくとも一つが、前記基板端縁部まで延長して形成された前記めっき処理を行うためのめっき用延長配線を有さないことを特徴とし、
前記アンテナは、前記半導体チップの中央部から、前記半導体チップの四隅うちの一の隅または前記半導体チップの四辺のうちの一の辺に偏在して配設され、
前記めっき用延長配線は、前記一の隅、または前記一の辺以外の隅または辺で、前記第1ないし第3の配線を前記基板端縁部まで延長して形成されていることを特徴とする通信機器。 - 前記アンテナは、前記半導体チップの中央部から、前記半導体チップの四隅うちの一の隅または前記半導体チップの四辺のうちの一の辺に偏在して配設され、
前記めっき用延長配線は、前記一の隅、または前記一の辺から最も遠い対向した隅または辺で、前記第1ないし第3の配線を前記基板端縁部まで延長して形成されていることを特徴とする請求項1記載の通信機器。 - 前記アンテナは、前記半導体チップの四辺のうちの一の辺の外側に配設され、
前記めっき用延長配線は、前記一の辺以外の辺で、前記第1ないし第3の配線を前記基板端縁部まで延長して形成されていることを特徴とする請求項1ないし2記載の通信機器。 - 前記第1ないし第2の電極の少なくとも一つは、前記第4の電極よりも前記半導体チップに近い位置に形成されていることを特徴とする請求項1ないし請求項3のいずれか1項記載の通信機器。
- 前記第4の配線のうち少なくとも1ペアはペアで差動信号を扱う配線であり、ペアとなる2つの配線長さが概ね等しいことを特徴とする請求項1ないし請求項3のいずれか1項記載の通信機器。
- 前記めっき延長線の長さ、又は、前記めっき用延長配線を含む前記第1ないし第4の配線の長さが、前記アンテナの動作波長の半波長の整数倍以外であることを特徴とする請求項1ないし請求項5のいずれか1項記載の通信機器。
- 前記半導体チップには半導体チップのI/O電極が形成され、前記半導体チップのI/O電極と前記基板主面電極とはボンディングワイヤにより接続される構造であり、前記アンテナはボンディングワイヤを構造の一部とするアンテナであり、かつ前記半導体チップにおいてアンテナの動作波長を持つ信号の前記基板主面電極は、アンテナ向け電極のみであることを特徴とする、あるいは、半導体チップ上に形成されたオンチップ構造のアンテナであり、アンテナの動作波長を持つ信号の前記基板主面電極は無いことを特徴とする請求項1ないし請求項6のいずれか1項記載の通信機器。
- 前記電極は、BGA電極又はLGA電極であることを特徴とする請求項1ないし請求項7のいずれか1項記載の通信機器。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010216711A JP5087118B2 (ja) | 2010-09-28 | 2010-09-28 | 通信機器 |
US13/052,192 US8253245B2 (en) | 2010-09-28 | 2011-03-21 | Communication device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010216711A JP5087118B2 (ja) | 2010-09-28 | 2010-09-28 | 通信機器 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012074814A JP2012074814A (ja) | 2012-04-12 |
JP5087118B2 true JP5087118B2 (ja) | 2012-11-28 |
Family
ID=45869792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010216711A Active JP5087118B2 (ja) | 2010-09-28 | 2010-09-28 | 通信機器 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8253245B2 (ja) |
JP (1) | JP5087118B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101412946B1 (ko) | 2012-12-20 | 2014-06-26 | 삼성전기주식회사 | 안테나 및 프론트 엔드 모듈 |
CN103066370A (zh) * | 2012-12-28 | 2013-04-24 | 中兴通讯股份有限公司 | 一种栅格阵列封装模块及设备 |
JP6136804B2 (ja) * | 2013-09-19 | 2017-05-31 | 株式会社デンソーウェーブ | Rfid読取装置 |
US9344140B2 (en) * | 2014-02-25 | 2016-05-17 | Skyworks Solutions, Inc. | Systems, devices and methods related to improved radio-frequency modules |
US10230683B1 (en) | 2018-02-09 | 2019-03-12 | Capital One Services, Llc | Routing for large server deployments |
US10847479B2 (en) * | 2018-12-04 | 2020-11-24 | Micron Technology, Inc. | Antenna formation by integrated metal layer or redistribution layer |
JP2022092959A (ja) * | 2020-12-11 | 2022-06-23 | 株式会社村田製作所 | 高周波モジュール |
EP4080677A1 (en) * | 2021-04-22 | 2022-10-26 | Nxp B.V. | Integrated millimeter-wave dual-mode matching network |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6525410B1 (en) * | 1998-07-24 | 2003-02-25 | Texas Instruments Incorporated | Integrated circuit wireless tagging |
JP2001267463A (ja) * | 2000-03-17 | 2001-09-28 | Nec Yamaguchi Ltd | 半導体装置基板及び半導体装置の製造方法 |
CN1275328C (zh) * | 2000-06-21 | 2006-09-13 | 日立马库塞鲁株式会社 | 半导体芯片和使用了该半导体芯片的半导体器件 |
JP2003163459A (ja) * | 2001-11-26 | 2003-06-06 | Sony Corp | 高周波回路ブロック体及びその製造方法、高周波モジュール装置及びその製造方法。 |
JP4141857B2 (ja) * | 2003-02-18 | 2008-08-27 | 日立マクセル株式会社 | 半導体装置 |
DE60337036D1 (de) * | 2003-08-28 | 2011-06-16 | Hitachi Ltd | Halbleiterbauelement und verfahren zu seiner herstellung |
JP2005340741A (ja) * | 2004-05-31 | 2005-12-08 | Renesas Technology Corp | 半導体装置 |
JP4413174B2 (ja) * | 2004-09-01 | 2010-02-10 | 三洋電機株式会社 | アンテナ一体型回路装置 |
JP2007300266A (ja) * | 2006-04-28 | 2007-11-15 | Seiko Epson Corp | Ic部品 |
JP4786579B2 (ja) | 2007-03-29 | 2011-10-05 | 三菱電機株式会社 | 高周波モジュール |
JP5086817B2 (ja) * | 2008-01-15 | 2012-11-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5446718B2 (ja) * | 2009-10-22 | 2014-03-19 | ソニー株式会社 | 半導体装置、半導体装置の製造方法、無線伝送システム |
-
2010
- 2010-09-28 JP JP2010216711A patent/JP5087118B2/ja active Active
-
2011
- 2011-03-21 US US13/052,192 patent/US8253245B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20120074512A1 (en) | 2012-03-29 |
JP2012074814A (ja) | 2012-04-12 |
US8253245B2 (en) | 2012-08-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5087118B2 (ja) | 通信機器 | |
KR100891763B1 (ko) | 반도체 장치 | |
US7321166B2 (en) | Wiring board having connecting wiring between electrode plane and connecting pad | |
US7649499B2 (en) | High-frequency module | |
US8373997B2 (en) | Semiconductor device | |
US7436056B2 (en) | Electronic component package | |
US9362209B1 (en) | Shielding technique for semiconductor package including metal lid | |
JP2008010859A (ja) | 半導体装置 | |
US20130279134A1 (en) | Printed wiring board, semiconductor package, and printed circuit board | |
KR101218989B1 (ko) | 반도체 패키지 및 그 제조방법 | |
KR20080057190A (ko) | 향상된 접지 성능과 매립된 안테나를 갖는 3d 전자 패키징구조체 | |
US20130234304A1 (en) | Semiconductor device | |
US9589908B1 (en) | Methods to improve BGA package isolation in radio frequency and millimeter wave products | |
US20130154066A1 (en) | Semiconductor package and manufacturing method thereof | |
JP6643714B2 (ja) | 電子装置及び電子機器 | |
CN105762138A (zh) | 整合式毫米波芯片封装结构 | |
US10553954B2 (en) | Wireless device | |
US8791369B2 (en) | Electronic component | |
JP2016201537A (ja) | 実装基板モジュール | |
US10490522B2 (en) | Semi-conductor package structure | |
US20110316139A1 (en) | Package for a wireless enabled integrated circuit | |
JP5286694B2 (ja) | 電子装置 | |
CN114980510A (zh) | 用于蓝牙模组电路板的*** | |
JP6320681B2 (ja) | 半導体装置 | |
JP2010141366A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120802 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120814 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120907 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5087118 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150914 Year of fee payment: 3 |