JP5064157B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法Info
- Publication number
- JP5064157B2 JP5064157B2 JP2007241374A JP2007241374A JP5064157B2 JP 5064157 B2 JP5064157 B2 JP 5064157B2 JP 2007241374 A JP2007241374 A JP 2007241374A JP 2007241374 A JP2007241374 A JP 2007241374A JP 5064157 B2 JP5064157 B2 JP 5064157B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- connection terminal
- internal connection
- semiconductor substrate
- scribe region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Dicing (AREA)
Description
本発明の他の観点によれば、複数の半導体チップ形成領域、及び前記複数の半導体チップ形成領域の間に配置されたスクライブ領域を有する半導体基板を前記スクライブ領域で切断する工程を含む、電極パッドを有した半導体チップと、前記電極パッドに配設された内部接続端子と、前記半導体チップ上に形成された絶縁層と、前記絶縁層上に形成され前記内部接続端子と電気的に接続された配線パターンと、を備えた半導体装置の製造方法であって、前記スクライブ領域にアライメント用パターンを形成するアライメント用パターン形成工程と、前記電極パッド上に前記内部接続端子を形成する内部接続端子形成工程と、支持体上に絶縁層を積層し、積層された前記絶縁層に前記スクライブ領域に対応する貫通溝を形成する貫通溝形成工程と、前記支持体の前記絶縁層側を、前記半導体基板の前記内部接続端子が形成された側に貼り付けて、前記半導体基板上に、前記スクライブ領域と対向する部分に貫通溝を有した前記絶縁層を形成する絶縁層形成工程と、前記支持体を前記内部接続端子側に押圧し、前記内部接続端子の上面を前記絶縁層から露出させる露出工程と、前記支持体を除去する支持体除去工程と、前記絶縁層上に、前記アライメント用パターンを露出する貫通溝を有する金属層を形成する金属層形成工程と、前記アライメント用パターンに基づき、前記配線パターンの形成位置のアライメントを行い、前記金属層をパターニングして前記配線パターンを形成する配線パターン形成工程と、前記配線パターン形成工程後に、前記半導体基板を含む前記スクライブ領域の前記貫通溝内に露出する部分を切断する切断工程と、を含むことを特徴とする半導体装置の製造方法が提供される。
図12は、本発明の第1の実施の形態に係る半導体装置の断面図である。図12を参照するに、第1の実施の形態の半導体装置10は、半導体チップ11と、内部接続端子12と、絶縁層13と、配線パターン14と、ソルダーレジスト16と、外部接続端子17とを有する。
図34は、本発明の第2の実施の形態に係る半導体装置の断面図である。図34において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。図34を参照するに、第2の実施の形態の半導体装置40は、第1の実施の形態の半導体装置10に設けられた配線パターン14の代わりに、メタルシード層42と金属膜43とからなる配線パターン41を設けた以外は半導体装置10と同様に構成される。メタルシード層42としては、例えば、Cu層等を用いることができる。また、メタルシード層42の厚さT7は、例えば、0.5μm〜1.0μmとすることができる。金属膜43としては、例えば、Cu等を用いることができる。また、金属膜43の厚さT8は、例えば、10μm〜20μmとすることができる。
11,101 半導体チップ
12,102 内部接続端子
12A,13A,25A,33A,42A,102A,103A 上面
13,103 絶縁層
14,41,104 配線パターン
14A,41A,104A 外部接続端子配設領域
16,106 ソルダーレジスト
17,107 外部接続端子
21,31,109,110 半導体基板
22,111 半導体集積回路
23,112 電極パッド
24,113 保護膜
25 支持体
26 貫通溝
27 アライメント用パターン
33 金属層
33B 下面
35 ダイシングブレード
36、44,45 レジスト膜
42 メタルシード層
43 金属膜
44A,45A 開口部
A 半導体装置形成領域
B スクライブ領域
C 切断位置
T1〜T8 厚さ
H1 高さ
W1,W2 幅
Claims (4)
- 複数の半導体チップ形成領域、及び前記複数の半導体チップ形成領域の間に配置されたスクライブ領域を有する半導体基板を前記スクライブ領域で切断する工程を含む、電極パッドを有した半導体チップと、前記電極パッドに配設された内部接続端子と、前記半導体チップ上に形成された絶縁層と、前記絶縁層上に形成され前記内部接続端子と電気的に接続された配線パターンと、を備えた半導体装置の製造方法であって、
前記スクライブ領域にアライメント用パターンを形成するアライメント用パターン形成工程と、
前記電極パッド上に前記内部接続端子を形成する内部接続端子形成工程と、
支持体上に金属層と絶縁層とを順次積層し、積層された前記金属層及び前記絶縁層に前記スクライブ領域に対応する貫通溝を形成する貫通溝形成工程と、
前記支持体の前記絶縁層側を、前記半導体基板の前記内部接続端子が形成された側に貼り付けて、前記半導体基板上に、前記スクライブ領域と対向する部分に貫通溝を有した前記絶縁層を形成する絶縁層形成工程と、
前記支持体を前記内部接続端子側に押圧し、前記金属層と前記内部接続端子とを圧着させる圧着工程と、
前記支持体を除去する支持体除去工程と、
前記アライメント用パターンに基づき、前記配線パターンの形成位置のアライメントを行い、前記金属層をパターニングして前記配線パターンを形成する配線パターン形成工程と、
前記配線パターン形成工程後に、前記半導体基板を含む前記スクライブ領域の前記貫通溝内に露出する部分を切断する切断工程と、を含むことを特徴とする半導体装置の製造方法。 - 複数の半導体チップ形成領域、及び前記複数の半導体チップ形成領域の間に配置されたスクライブ領域を有する半導体基板を前記スクライブ領域で切断する工程を含む、電極パッドを有した半導体チップと、前記電極パッドに配設された内部接続端子と、前記半導体チップ上に形成された絶縁層と、前記絶縁層上に形成され前記内部接続端子と電気的に接続された配線パターンと、を備えた半導体装置の製造方法であって、
前記スクライブ領域にアライメント用パターンを形成するアライメント用パターン形成工程と、
前記電極パッド上に前記内部接続端子を形成する内部接続端子形成工程と、
支持体上に絶縁層を積層し、積層された前記絶縁層に前記スクライブ領域に対応する貫通溝を形成する貫通溝形成工程と、
前記支持体の前記絶縁層側を、前記半導体基板の前記内部接続端子が形成された側に貼り付けて、前記半導体基板上に、前記スクライブ領域と対向する部分に貫通溝を有した前記絶縁層を形成する絶縁層形成工程と、
前記支持体を前記内部接続端子側に押圧し、前記内部接続端子の上面を前記絶縁層から露出させる露出工程と、
前記支持体を除去する支持体除去工程と、
前記絶縁層上に、前記アライメント用パターンを露出する貫通溝を有する金属層を形成する金属層形成工程と、
前記アライメント用パターンに基づき、前記配線パターンの形成位置のアライメントを行い、前記金属層をパターニングして前記配線パターンを形成する配線パターン形成工程と、
前記配線パターン形成工程後に、前記半導体基板を含む前記スクライブ領域の前記貫通溝内に露出する部分を切断する切断工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記電極パッドと前記アライメント用パターンとを同一の工程で形成することを特徴とする請求項1又は2記載の半導体装置の製造方法。
- 前記アライメント用パターンに基づき、前記半導体基板の前記スクライブ領域の位置と前記貫通溝の位置とのアライメントを行うことを特徴とする請求項1又は2記載の半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007241374A JP5064157B2 (ja) | 2007-09-18 | 2007-09-18 | 半導体装置の製造方法 |
KR1020080091161A KR20090029660A (ko) | 2007-09-18 | 2008-09-17 | 반도체 장치의 제조 방법 |
TW097135580A TW200915440A (en) | 2007-09-18 | 2008-09-17 | Manufacturing method of semiconductor apparatus |
US12/212,169 US7772091B2 (en) | 2007-09-18 | 2008-09-17 | Manufacturing method of semiconductor apparatus comprising alignment patterns in scribe regions |
CNA2008101612067A CN101393848A (zh) | 2007-09-18 | 2008-09-18 | 半导体器件的制造方法 |
EP08164617A EP2040288A2 (en) | 2007-09-18 | 2008-09-18 | Method of forming semiconductor chip wiring pattern using alignment marks |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007241374A JP5064157B2 (ja) | 2007-09-18 | 2007-09-18 | 半導体装置の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009076496A JP2009076496A (ja) | 2009-04-09 |
JP2009076496A5 JP2009076496A5 (ja) | 2010-09-02 |
JP5064157B2 true JP5064157B2 (ja) | 2012-10-31 |
Family
ID=40030274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007241374A Expired - Fee Related JP5064157B2 (ja) | 2007-09-18 | 2007-09-18 | 半導体装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7772091B2 (ja) |
EP (1) | EP2040288A2 (ja) |
JP (1) | JP5064157B2 (ja) |
KR (1) | KR20090029660A (ja) |
CN (1) | CN101393848A (ja) |
TW (1) | TW200915440A (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8053279B2 (en) | 2007-06-19 | 2011-11-08 | Micron Technology, Inc. | Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces |
JP5432481B2 (ja) * | 2008-07-07 | 2014-03-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
JP2010109182A (ja) * | 2008-10-30 | 2010-05-13 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2012134270A (ja) * | 2010-12-21 | 2012-07-12 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP5728947B2 (ja) * | 2011-01-06 | 2015-06-03 | セイコーエプソン株式会社 | アライメントマーク形成方法、ノズル基板形成方法、ノズル基板および液滴吐出ヘッド |
TWI464857B (zh) * | 2011-05-20 | 2014-12-11 | Xintec Inc | 晶片封裝體、其形成方法、及封裝晶圓 |
US10008413B2 (en) | 2013-08-27 | 2018-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level dicing method |
KR102288381B1 (ko) * | 2014-08-20 | 2021-08-09 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US10163805B2 (en) * | 2016-07-01 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method for forming the same |
KR20190052957A (ko) * | 2017-11-09 | 2019-05-17 | 에스케이하이닉스 주식회사 | 다이 오버시프트 지시 패턴을 포함하는 반도체 패키지 |
US10607941B2 (en) * | 2018-04-30 | 2020-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor device |
CN111200907B (zh) * | 2018-11-20 | 2021-10-19 | 宏启胜精密电子(秦皇岛)有限公司 | 无撕膜内埋式电路板及其制作方法 |
CN112770495B (zh) * | 2019-10-21 | 2022-05-27 | 宏启胜精密电子(秦皇岛)有限公司 | 全向内埋模组及制作方法、封装结构及制作方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1106036C (zh) * | 1997-05-15 | 2003-04-16 | 日本电气株式会社 | 芯片型半导体装置的制造方法 |
JP2000077312A (ja) * | 1998-09-02 | 2000-03-14 | Mitsubishi Electric Corp | 半導体装置 |
JP4037561B2 (ja) * | 1999-06-28 | 2008-01-23 | 株式会社東芝 | 半導体装置の製造方法 |
JP2002057251A (ja) * | 2000-08-07 | 2002-02-22 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6900532B1 (en) * | 2000-09-01 | 2005-05-31 | National Semiconductor Corporation | Wafer level chip scale package |
JP3609761B2 (ja) * | 2001-07-19 | 2005-01-12 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP4260405B2 (ja) * | 2002-02-08 | 2009-04-30 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
JP3614828B2 (ja) * | 2002-04-05 | 2005-01-26 | 沖電気工業株式会社 | チップサイズパッケージの製造方法 |
JP4134866B2 (ja) * | 2003-09-22 | 2008-08-20 | カシオ計算機株式会社 | 封止膜形成方法 |
JP3953027B2 (ja) * | 2003-12-12 | 2007-08-01 | ソニー株式会社 | 半導体装置およびその製造方法 |
US7442624B2 (en) * | 2004-08-02 | 2008-10-28 | Infineon Technologies Ag | Deep alignment marks on edge chips for subsequent alignment of opaque layers |
JP4636839B2 (ja) * | 2004-09-24 | 2011-02-23 | パナソニック株式会社 | 電子デバイス |
JP4105202B2 (ja) * | 2006-09-26 | 2008-06-25 | 新光電気工業株式会社 | 半導体装置の製造方法 |
-
2007
- 2007-09-18 JP JP2007241374A patent/JP5064157B2/ja not_active Expired - Fee Related
-
2008
- 2008-09-17 US US12/212,169 patent/US7772091B2/en not_active Expired - Fee Related
- 2008-09-17 KR KR1020080091161A patent/KR20090029660A/ko not_active Application Discontinuation
- 2008-09-17 TW TW097135580A patent/TW200915440A/zh unknown
- 2008-09-18 CN CNA2008101612067A patent/CN101393848A/zh active Pending
- 2008-09-18 EP EP08164617A patent/EP2040288A2/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JP2009076496A (ja) | 2009-04-09 |
EP2040288A2 (en) | 2009-03-25 |
US7772091B2 (en) | 2010-08-10 |
US20090075457A1 (en) | 2009-03-19 |
CN101393848A (zh) | 2009-03-25 |
TW200915440A (en) | 2009-04-01 |
KR20090029660A (ko) | 2009-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5064157B2 (ja) | 半導体装置の製造方法 | |
US8410614B2 (en) | Semiconductor device having a semiconductor element buried in an insulating layer and method of manufacturing the same | |
JP4105202B2 (ja) | 半導体装置の製造方法 | |
US7494845B2 (en) | Method of forming a thin wafer stack for a wafer level package | |
US7790515B2 (en) | Semiconductor device with no base member and method of manufacturing the same | |
JP2009081355A (ja) | 電子装置及びその製造方法 | |
JP4379102B2 (ja) | 半導体装置の製造方法 | |
JP5064158B2 (ja) | 半導体装置とその製造方法 | |
US20100213605A1 (en) | Semiconductor device and method of manufacturing semiconductor device | |
JP4828515B2 (ja) | 半導体装置の製造方法 | |
JP2008210912A (ja) | 半導体装置及びその製造方法 | |
JP2009272512A (ja) | 半導体装置の製造方法 | |
JP5139039B2 (ja) | 半導体装置及びその製造方法 | |
JP2009246174A (ja) | 半導体モジュール、半導体モジュールの製造方法、ならびに携帯機器 | |
JP2005353837A (ja) | 半導体装置及びその製造方法 | |
JP2004343088A (ja) | 半導体装置及びその製造方法 | |
JP5048420B2 (ja) | 半導体装置及びその製造方法 | |
US20100112786A1 (en) | Method of manufacturing semiconductor device | |
JP2007294575A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100714 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100714 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101130 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120731 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120808 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5064157 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150817 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |