JP5025113B2 - 回路装置 - Google Patents
回路装置 Download PDFInfo
- Publication number
- JP5025113B2 JP5025113B2 JP2005283605A JP2005283605A JP5025113B2 JP 5025113 B2 JP5025113 B2 JP 5025113B2 JP 2005283605 A JP2005283605 A JP 2005283605A JP 2005283605 A JP2005283605 A JP 2005283605A JP 5025113 B2 JP5025113 B2 JP 5025113B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- layer
- insulating layer
- via hole
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図1は、本発明の第1実施形態による回路装置を示した断面図である。
図6は、本発明の第2実施形態による回路装置を示した断面図である。第1実施形態と異なる箇所は、LSIチップ9と導電層5のワイヤボンディング部において、導電層3と接続することができない箇所に、絶縁層4の表面側に凹状の非貫通のビアホール4c1を設けていることである。それ以外については、第1実施形態と同様である。
2 絶縁層
2a 絶縁層2を貫通するビアホール(接続孔)
2b 絶縁層2の表面側の非貫通のビアホール(凹部)
3 導電層
3a,3b,3c,3d 配線部
3a1 貫通サーマルビア
3b1 非貫通サーマルビア
4 樹脂層
4a 絶縁層4を貫通するビアホール(接続孔)
4b 絶縁層4の表面側の非貫通のビアホール(凹部)
4c 絶縁層4を貫通するビアホール(接続孔)
5 導電層
5a,5b,5c,5d 配線部
5a1 貫通サーマルビア
5a2 非貫通サーマルビア
5b1,5c1 非充填ビア
6 フォトソルダーレジスト層
7 ワイヤ
9 LSIチップ(回路素子)
10 封止樹脂層
100 回路装置
Claims (4)
- 第1の導電層と、
前記第1の導電層の上に設けられた絶縁層と、
前記絶縁層内に設けられた1つ又は複数のビアホールと、
前記絶縁層上および前記ビアホール内に形成された第2の導電層と、
前記第2の導電層に電気的に接続された回路素子と、
を備え、
前記ビアホールは、その底部が前記第1の導電層に向かって延び、且つ、前記第1の導電層に達しない凹部を含むとともに、
前記凹部において、前記第1の導電層と前記第2の導電層との間隔が、前記凹部のない箇所に比べて短いことを特徴とした回路装置。 - 前記絶縁層は、該絶縁層の熱伝導率を高くするための充填材を含み、
前記凹部の底部と前記第1の導電層との間隔は、前記充填材の最大粒径よりも大きいことを特徴とした請求項1に記載の回路装置。 - 前記凹部は、前記回路素子の下方に位置する領域に設けられていることを特徴とした請求項1または2に記載の回路装置。
- 前記ビアホールは、その底部が前記第1の導電層に達する接続孔をさらに含むことを特徴とした請求項1〜3のいずれか一項に記載の回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005283605A JP5025113B2 (ja) | 2005-09-29 | 2005-09-29 | 回路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005283605A JP5025113B2 (ja) | 2005-09-29 | 2005-09-29 | 回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007096003A JP2007096003A (ja) | 2007-04-12 |
JP5025113B2 true JP5025113B2 (ja) | 2012-09-12 |
Family
ID=37981335
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005283605A Expired - Fee Related JP5025113B2 (ja) | 2005-09-29 | 2005-09-29 | 回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5025113B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6754117B2 (en) * | 2002-08-16 | 2004-06-22 | Micron Technology, Inc. | System and method for self-testing and repair of memory modules |
KR100803212B1 (ko) * | 2006-01-11 | 2008-02-14 | 삼성전자주식회사 | 스케일러블 채널 복호화 방법 및 장치 |
JP4816128B2 (ja) * | 2006-02-21 | 2011-11-16 | 株式会社デンソー | 車両用発電制御装置 |
KR100817513B1 (ko) * | 2006-11-08 | 2008-03-27 | 피앤에이파워시스템 주식회사 | 단로기 |
KR100856114B1 (ko) * | 2008-04-18 | 2008-09-02 | 강지민 | 리모컨을 이용한 텔레비전 음향과 데이터 송수신방법 |
US8492911B2 (en) * | 2010-07-20 | 2013-07-23 | Lsi Corporation | Stacked interconnect heat sink |
JP6279921B2 (ja) * | 2014-02-12 | 2018-02-14 | 新光電気工業株式会社 | 配線基板及び半導体パッケージ |
US20230260883A1 (en) * | 2020-07-02 | 2023-08-17 | Sony Semiconductor Solutions Corporation | Interposer, circuit device, method of manufacturing interposer, and method of manufacturing circuit device |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01295455A (ja) * | 1988-05-24 | 1989-11-29 | Matsushita Electric Ind Co Ltd | 半導体積層集積回路素子 |
JPH07193347A (ja) * | 1993-12-27 | 1995-07-28 | Toshiba Corp | 配線基板 |
JP3311899B2 (ja) * | 1995-01-20 | 2002-08-05 | 松下電器産業株式会社 | 回路基板及びその製造方法 |
JPH09283933A (ja) * | 1996-04-10 | 1997-10-31 | Cmk Corp | プリント配線板 |
JP3395621B2 (ja) * | 1997-02-03 | 2003-04-14 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP3982876B2 (ja) * | 1997-06-30 | 2007-09-26 | 沖電気工業株式会社 | 弾性表面波装置 |
JP3241019B2 (ja) * | 1999-03-15 | 2001-12-25 | 日本電気株式会社 | コプレーナ線路 |
JP2004039908A (ja) * | 2002-07-04 | 2004-02-05 | Nippon Mektron Ltd | 回路基板及びその製造法 |
JP2004260051A (ja) * | 2003-02-27 | 2004-09-16 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
-
2005
- 2005-09-29 JP JP2005283605A patent/JP5025113B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2007096003A (ja) | 2007-04-12 |
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