JP5018771B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5018771B2
JP5018771B2 JP2008509588A JP2008509588A JP5018771B2 JP 5018771 B2 JP5018771 B2 JP 5018771B2 JP 2008509588 A JP2008509588 A JP 2008509588A JP 2008509588 A JP2008509588 A JP 2008509588A JP 5018771 B2 JP5018771 B2 JP 5018771B2
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宇俊 和泉
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Description

本発明は、下部電極と上部電極との間に強誘電体を材料とする誘電体膜が挟持されてなる強誘電体キャパシタ構造を有する半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device having a ferroelectric capacitor structure in which a dielectric film made of a ferroelectric material is sandwiched between a lower electrode and an upper electrode, and a method for manufacturing the same.

従来より、電源を断っても記憶情報が消失しない不揮発性メモリとして、フラッシュメモリや強誘電体メモリ（ＦｅＲＡＭ：Ferro-electric Random Access Memory）が知られている。
フラッシュメモリは、絶縁ゲート型電界効果トランジスタ（ＩＧＦＥＴ）のゲート絶縁膜中に埋め込まれたフローティングゲートを有し、フローティングゲートに記憶情報を表わす電荷を蓄積することによって情報を記憶する。情報の書き込み、消去には絶縁膜を通過するトンネル電流を流す必要があり、比較的高い電圧を必要とする。Conventionally, flash memories and ferroelectric memories (FeRAM: Ferro-electric Random Access Memory) are known as nonvolatile memories in which stored information is not lost even when the power is turned off.
A flash memory has a floating gate embedded in a gate insulating film of an insulated gate field effect transistor (IGFET), and stores information by accumulating charges representing stored information in the floating gate. For writing and erasing information, a tunnel current passing through the insulating film needs to flow, and a relatively high voltage is required.

ＦｅＲＡＭは、強誘電体のヒステリシス特性を利用して情報を記憶する。強誘電体膜を上部及び下部電極間のキャパシタ膜として有する強誘電体キャパシタ構造は、電極間の印加電圧に応じて分極を生じ、印加電圧を取り去っても自発分極を有する。印加電圧の極性を反転すれば、自発分極の極性も反転する。この自発分極を検出すれば情報を読み出すことができる。ＦｅＲＡＭは、フラッシュメモリに比べて低電圧で動作し、省電力で高速の書き込みができるという利点を有する。従来のロジック技術に、このＦｅＲＡＭを取り入れたロジック混載チップ（ＳＯＣ：System On Chip）が、ＩＣカードなどの用途として検討されている。   FeRAM stores information using the hysteresis characteristics of ferroelectrics. A ferroelectric capacitor structure having a ferroelectric film as a capacitor film between upper and lower electrodes generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Information can be read by detecting this spontaneous polarization. FeRAM has an advantage that it operates at a lower voltage than a flash memory, and can perform high-speed writing with power saving. A logic embedded chip (SOC: System On Chip) that incorporates this FeRAM in the conventional logic technology has been studied as an application such as an IC card.

特開平１０−１２７３０号公報Japanese Patent Laid-Open No. 10-12730 特開平９−２３７８３４号公報Japanese Patent Laid-Open No. 9-237834 特開平２−１５１０３２号公報Japanese Patent Laid-Open No. 2-151032

近時では、半導体装置の微細化・高集積化が進行している。ＦｅＲＡＭにおける強誘電体キャパシタ構造や配線のデザインルールが０．１８μｍレベルともなれば、既存のシリコン酸化膜等の層間絶縁膜では、隣接する強誘電体キャパシタ構造間又は隣接する配線間を十分に埋め込むことができず、当該間隙の領域に空隙（ボイド）が発生してしまうという問題がある。ボイドの発生により、当該ボイドを通して水分・水素が内部へ浸透し易くなり、キャパシタ膜である強誘電体への悪影響等が懸念され、装置の信頼性上、大きな問題となる。   Recently, semiconductor devices have been miniaturized and highly integrated. If the design rule of the ferroelectric capacitor structure and wiring in FeRAM is 0.18 μm level, an existing interlayer insulating film such as a silicon oxide film is sufficiently embedded between adjacent ferroelectric capacitor structures or between adjacent wirings. There is a problem that voids are generated in the gap region. The generation of voids makes it easy for moisture and hydrogen to permeate into the inside through the voids, and there is a concern about adverse effects on the ferroelectric substance that is the capacitor film, which is a serious problem in terms of device reliability.

この問題に対処すべく、層間絶縁膜を高密度プラズマＣＶＤ法（ＨＤＰ−ＣＶＤ法）により緻密に形成し、優れた埋め込み性により当該層間絶縁膜（以下、ＨＤＰ−ＣＶＤ絶縁膜と称する。）におけるボイドの発生を可及的に抑制する技術が案出されている。ところがＨＤＰ−ＣＶＤ法により層間絶縁膜を形成する場合、発生させた高密度プラズマに起因して、強誘電体キャパシタ構造のキャパシタ膜にダメージが及ぼされ、キャパシタ特性の劣化を招くという問題がある。また、ＨＤＰ−ＣＶＤ絶縁膜は、膜中の含有水分量が多く、強誘電体キャパシタ構造の形成後に必須であるキャパシタ膜の回復アニール等に起因して、形成されたＨＤＰ−ＣＶＤ絶縁膜から水分や水素が発生して、キャパシタ特性の劣化を招くことになる。 In order to cope with this problem, an interlayer insulating film is densely formed by a high-density plasma CVD method (HDP-CVD method), and the interlayer insulating film (hereinafter referred to as an HDP-CVD insulating film) has excellent embeddability. A technique has been devised to suppress the generation of voids as much as possible. However, when the interlayer insulating film is formed by the HDP-CVD method, there is a problem that the capacitor film of the ferroelectric capacitor structure is damaged due to the generated high-density plasma, and the capacitor characteristics are deteriorated. Further, the HDP-CVD insulating film has a high moisture content in the film, and moisture is removed from the formed HDP-CVD insulating film due to the recovery annealing of the capacitor film that is essential after the formation of the ferroelectric capacitor structure. And hydrogen is generated, which causes deterioration of capacitor characteristics.

本発明は、上記の課題に鑑みてなされたものであり、（第１及び第２の）層間絶縁膜から水分や水素を発生させることなく、ボイドが発生してもキャパシタ構造には悪影響を及ぼすことなく高いキャパシタ特性を確実に保持し、高い信頼性を得ることのできる半導体装置及びその製造方法を提供することを目的とする。   The present invention has been made in view of the above-described problems. Even if voids are generated without generating moisture or hydrogen from the (first and second) interlayer insulating films, the capacitor structure is adversely affected. An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can reliably retain high capacitor characteristics and obtain high reliability.

本発明の半導体装置は、半導体基板と、前記半導体基板の上方に形成されており、下部電極と上部電極とにより強誘電体を材料とするキャパシタ膜を挟持してなるキャパシタ構造と、前記キャパシタ構造を覆う第１の層間絶縁膜と、前記第１の層間絶縁膜上に形成された、前記キャパシタ構造の特性劣化を防止する第１の水素拡散防止膜とを含み、前記第１の層間絶縁膜の表層部分には第１の空隙があり、前記第１の空隙の上部が前記第１の層間絶縁膜の表面から開口した状態とされており、前記第１の水素拡散防止膜は、前記第１の空隙の少なくとも内壁面上に形成され、かつ、前記第１の空隙上に閉塞部分を有する。 The semiconductor device of the present invention includes a semiconductor substrate, a capacitor structure formed above the semiconductor substrate, and a capacitor film made of a ferroelectric material sandwiched between a lower electrode and an upper electrode, and the capacitor structure. A first interlayer insulating film that covers the first interlayer insulating film, and a first hydrogen diffusion preventing film that is formed on the first interlayer insulating film to prevent deterioration of the characteristics of the capacitor structure. There is a first void in the surface layer portion, and an upper portion of the first void is opened from the surface of the first interlayer insulating film, and the first hydrogen diffusion prevention film includes the first void . It is formed on at least the inner wall surface of the first gap, and has a closed portion on the first gap.

本発明の半導体装置の製造方法は、半導体基板の上方に、下部電極と上部電極とにより強誘電体を材料とするキャパシタ膜を挟持してなるキャパシタ構造を形成する工程と、前記キャパシタ構造を覆うように第１の層間絶縁膜を形成する工程と、前記第１の層間絶縁膜の表層部分に発生した第１の空隙の上部を、前記第１の層間絶縁膜の表面から開口させる工程と、前記第１の層間絶縁膜上に、前記第１の空隙の少なくとも内壁面を覆いつつ、前記第１の空隙を閉塞するように、前記キャパシタ構造の特性劣化を防止する第１の水素拡散防止膜を形成する工程とを含む。 The method of manufacturing a semiconductor device of the present invention includes a step of forming a capacitor structure in which a capacitor film made of a ferroelectric material is sandwiched between a lower electrode and an upper electrode above a semiconductor substrate, and covers the capacitor structure. Forming the first interlayer insulating film as described above, opening the upper part of the first gap generated in the surface layer portion of the first interlayer insulating film from the surface of the first interlayer insulating film, on the first interlayer insulating film, wherein while covering at least an inner wall surface of the first gap, so as to close said first gap, the first hydrogen diffusion preventing film for preventing the characteristic degradation of the capacitor structure Forming the step.

本発明によれば、（第１及び第２の）層間絶縁膜から水分や水素を発生させることなく、ボイドが発生してもキャパシタ構造には悪影響を及ぼすことなく高いキャパシタ特性を確実に保持し、信頼性の高い半導体装置が実現する。   According to the present invention, without generating moisture or hydrogen from the (first and second) interlayer insulating films, even if voids are generated, high capacitor characteristics are reliably maintained without adversely affecting the capacitor structure. A highly reliable semiconductor device is realized.

図１Ａは、本発明の基本構成を説明するための概略断面図である。FIG. 1A is a schematic cross-sectional view for explaining the basic configuration of the present invention. 図１Ｂは、本発明の基本構成を説明するための概略断面図である。FIG. 1B is a schematic cross-sectional view for explaining the basic configuration of the present invention. 図１Ｃは、本発明の基本構成を説明するための概略断面図である。FIG. 1C is a schematic cross-sectional view for explaining the basic configuration of the present invention. 図２Ａは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 2A is a schematic cross-sectional view showing a method of manufacturing the stacked FeRAM according to the first embodiment of the present invention in the order of steps. 図２Ｂは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 2B is a schematic cross-sectional view illustrating the stacked FeRAM manufacturing method according to the first embodiment of the present invention in the order of steps. 図２Ｃは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 2C is a schematic cross-sectional view showing the manufacturing method of the stack type FeRAM according to the first embodiment of the present invention in the order of steps. 図３Ａは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 3A is a schematic cross-sectional view illustrating the stack type FeRAM manufacturing method according to the first embodiment of the present invention in the order of steps. 図３Ｂは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 3B is a schematic cross-sectional view showing the manufacturing method of the stack type FeRAM according to the first embodiment of the present invention in the order of steps. 図３Ｃは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 3C is a schematic cross-sectional view illustrating the stack type FeRAM manufacturing method according to the first embodiment of the present invention in the order of steps. 図４Ａは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 4A is a schematic cross-sectional view illustrating the stack type FeRAM manufacturing method according to the first embodiment of the present invention in the order of steps. 図４Ｂは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 4B is a schematic cross-sectional view illustrating the stacked FeRAM manufacturing method according to the first embodiment of the present invention in the order of steps. 図４Ｃは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 4C is a schematic cross-sectional view showing the manufacturing method of the stack type FeRAM according to the first embodiment of the present invention in the order of steps. 図５Ａは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 5A is a schematic cross-sectional view illustrating the stack type FeRAM manufacturing method according to the first embodiment of the present invention in the order of steps. 図５Ｂは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 5B is a schematic cross-sectional view showing the method of manufacturing the stack type FeRAM according to the first embodiment of the present invention in the order of steps. 図５Ｃは、本発明の第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 5C is a schematic cross-sectional view illustrating the stack type FeRAM manufacturing method according to the first embodiment of the present invention in the order of steps. 図６Ａは、本発明の第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 6A is a schematic cross-sectional view illustrating a stacked FeRAM manufacturing method according to the second embodiment of the present invention in the order of steps. 図６Ｂは、本発明の第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 6B is a schematic cross-sectional view showing the method of manufacturing the stacked FeRAM according to the second embodiment of the present invention in the order of steps. 図６Ｃは、本発明の第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 6C is a schematic cross-sectional view showing the method of manufacturing the stacked FeRAM according to the second embodiment of the present invention in the order of steps. 図７Ａは、本発明の第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 7A is a schematic cross-sectional view showing a method of manufacturing a stacked FeRAM according to the second embodiment of the present invention in the order of steps. 図７Ｂは、本発明の第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 7B is a schematic cross-sectional view showing the method of manufacturing the stacked FeRAM according to the second embodiment of the present invention in the order of steps. 図７Ｃは、本発明の第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 7C is a schematic cross-sectional view showing the method of manufacturing the stacked FeRAM according to the second embodiment of the present invention in the order of steps. 図８Ａは、本発明の第２の実施形態の変形例によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 8A is a schematic cross-sectional view showing a method for manufacturing a stack type FeRAM according to a modification of the second embodiment of the present invention in the order of steps. 図８Ｂは、本発明の第２の実施形態の変形例によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 8B is a schematic cross-sectional view showing a method of manufacturing a stack type FeRAM according to a modification of the second embodiment of the present invention in the order of steps. 図８Ｃは、本発明の第２の実施形態の変形例によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。FIG. 8C is a schematic cross-sectional view illustrating a stack type FeRAM manufacturing method according to a modification of the second embodiment of the present invention in the order of steps.

−本発明の基本骨子−
従来では、微細化の進む強誘電体キャパシタ構造や配線を覆うように層間絶縁膜を形成する場合、当該層間絶縁膜におけるボイドの発生を抑止すべく、層間絶縁膜の形成に高密度プラズマＣＶＤ法を用いる等の様々な技術的工夫がなされてきた。-Basic outline of the present invention-
Conventionally, when an interlayer insulating film is formed so as to cover a ferroelectric capacitor structure and wiring that are becoming finer, a high-density plasma CVD method is used to form the interlayer insulating film in order to suppress the generation of voids in the interlayer insulating film. Various technical devices have been made such as using.

しかしながら、ボイド発生抑止の手法を採用した場合、上述のようにキャパシタ膜である強誘電体膜に大きなダメージを及ぼすという回避し難い問題が生じてしまう。そこで本発明者は、言わば発想を転換し、そもそもボイドは発生するが強誘電体膜へ対して低ダメージの絶縁材料・成膜条件で強誘電体キャパシタ構造又は配線を覆う層間絶縁膜を形成し、発生したボイドを積極的に利用すべく鋭意検討した結果、本発明に想到した。   However, when the method for suppressing the generation of voids is employed, there arises an inevitable problem that the ferroelectric film as the capacitor film is seriously damaged as described above. Therefore, the present inventor changed the way of thinking, and formed an interlayer insulating film covering the ferroelectric capacitor structure or the wiring with a low damage insulating material and film forming conditions to the ferroelectric film although voids were originally generated. As a result of intensive studies to actively use the generated voids, the present invention has been conceived.

ＦｅＲＡＭでは、水分及び水素に対する耐性の低い強誘電体膜をキャパシタ膜に用いることから、発生した水分及び水素が強誘電体膜へ拡散しないように、可及的に当該拡散を抑えるべく、アルミ酸化物（アルミナ）に代表される材料からなる水素拡散防止膜を強誘電体キャパシタ構造の周囲（主に上部）に形成することが必須であると考えられている。   In FeRAM, a ferroelectric film having low resistance to moisture and hydrogen is used for the capacitor film. Therefore, in order to prevent the generated moisture and hydrogen from diffusing into the ferroelectric film, aluminum oxide is used to suppress the diffusion as much as possible. It is considered essential to form a hydrogen diffusion prevention film made of a material typified by an object (alumina) around the ferroelectric capacitor structure (mainly at the top).

本発明では、この水素拡散防止膜を利用して、工程数の増加を招くことなく、むしろ発生したボイドを水分・水素の拡散防止機能の向上に寄与させる。以下、本発明の主要構成について、図１Ａ〜図１Ｃを用いて説明する。   In the present invention, this hydrogen diffusion prevention film is used to increase the number of steps, and rather, the generated voids contribute to the improvement of the moisture / hydrogen diffusion prevention function. Hereinafter, the main structure of this invention is demonstrated using FIG. 1A-FIG. 1C.

先ず、図１Ａでは、半導体基板上にトランジスタ構造等を形成した後、その上方に、強誘電体キャパシタ構造１を形成した様子の概略を示している。ここでは、隣接する２つの強誘電体キャパシタ構造１を例示し、両者は近接して形成されている。   First, FIG. 1A schematically shows a state in which a ferroelectric capacitor structure 1 is formed above a transistor structure and the like formed on a semiconductor substrate. Here, two adjacent ferroelectric capacitor structures 1 are illustrated, and both are formed close to each other.

なお、層間絶縁膜による埋め込み対象物として強誘電体キャパシタ構造１を例示するが、これが配線である場合でもほぼ同様であり、強誘電体キャパシタ構造１を配線１と読み替えても良い。以下、強誘電体キャパシタ構造１を例に採るため、図示の便宜上、トランジスタ構造を含む強誘電体キャパシタ構造１の下層の構造を、下層２として一括して示す。   Although the ferroelectric capacitor structure 1 is illustrated as an object to be embedded by the interlayer insulating film, the same is true even when this is a wiring, and the ferroelectric capacitor structure 1 may be read as the wiring 1. Hereinafter, in order to take the ferroelectric capacitor structure 1 as an example, the lower layer structure of the ferroelectric capacitor structure 1 including the transistor structure is collectively shown as the lower layer 2 for convenience of illustration.

続いて、図１Ｂに示すように、下層２上で強誘電体キャパシタ構造１を覆うように層間絶縁膜３を形成する。ここで、層間絶縁膜３としては、強誘電体キャパシタ構造１のキャパシタ膜（強誘電体膜）に対して低ダメージとなる材料・条件、例えば含有水分量の抑制されたＰＥ−ＴＥＯＳ−ＳｉＯによりＣＶＤ法で形成する。具体的に、当該含有水分量は、例えば５×１０−３（ｇ／ｃｍ３）以下程度である。Subsequently, as shown in FIG. 1B, an interlayer insulating film 3 is formed on the lower layer 2 so as to cover the ferroelectric capacitor structure 1. Here, the interlayer insulating film 3 is made of a material and conditions that cause low damage to the capacitor film (ferroelectric film) of the ferroelectric capacitor structure 1, for example, PE-TEOS-SiO in which the moisture content is suppressed. It is formed by the CVD method. Specifically, the moisture content is about 5 × 10 −3 (g / cm 3 ) or less, for example.

このとき、強誘電体キャパシタ構造１間の領域を層間絶縁膜３で完全に埋め込むことはできず、層間絶縁膜３内の当該領域にボイド４が発生する。本発明では、層間絶縁膜３に内包されるようにボイド４が発生した場合には、層間絶縁膜３の表層を例えばＣＭＰ法により平坦化する際に、後述の水素拡散防止膜５がボイド４内に入り込めるように、当該平坦化によりボイド４の上部を層間絶縁膜３の表面から開口させる。ボイド４の開口部を４ａと記す。   At this time, the region between the ferroelectric capacitor structures 1 cannot be completely filled with the interlayer insulating film 3, and a void 4 is generated in the region in the interlayer insulating film 3. In the present invention, when the void 4 is generated so as to be included in the interlayer insulating film 3, when the surface layer of the interlayer insulating film 3 is planarized by, for example, the CMP method, the hydrogen diffusion preventing film 5 described later becomes the void 4 The upper part of the void 4 is opened from the surface of the interlayer insulating film 3 by the planarization so as to be able to enter inside. The opening of the void 4 is denoted as 4a.

続いて、図１Ｃに示すように、例えばアルミナを材料として、強誘電体キャパシタ構造１のキャパシタ膜の特性劣化を防止する水素拡散防止膜５を、ボイド４の少なくとも内壁面を完全に覆うように、層間絶縁膜３上に形成する。水素拡散防止膜５を上記のように形成することから、その形成法として被覆性に優れたＭＯ−ＣＶＤ法を用いることが好ましい。そして、水素拡散防止膜５上を覆うように、例えばＣＶＤ法により、シリコン酸化膜又はシリコン窒化膜等のキャップ絶縁膜６を形成する。   Subsequently, as shown in FIG. 1C, for example, using alumina as a material, a hydrogen diffusion preventing film 5 that prevents deterioration of the characteristics of the capacitor film of the ferroelectric capacitor structure 1 is completely covered with at least the inner wall surface of the void 4. And formed on the interlayer insulating film 3. Since the hydrogen diffusion prevention film 5 is formed as described above, it is preferable to use the MO-CVD method having excellent coverage as the formation method. Then, a cap insulating film 6 such as a silicon oxide film or a silicon nitride film is formed by CVD, for example, so as to cover the hydrogen diffusion preventing film 5.

上記のように水素拡散防止膜５を形成することにより、ボイドの内壁は水素拡散防止膜５により完全に覆われ、若干の空洞部分が残るとしても殆ど閉塞する。この閉塞部分は、実質的にみれば、水素拡散防止膜５の層間絶縁膜３上の部分に比して厚く膜材料が堆積した状態とされており、キャパシタ膜に対する水分・水素の堅固なブロック機能を果たすことになる。そして、キャップ絶縁膜６により、仮に前記空洞部分の上部が開口されていたとしても、ボイド４の部分は水素拡散防止膜５によりほぼ充填された状態で完全に密閉された状態となり、キャパシタ膜に対する側面方向からの確実な前記ブロック機能が実現する。   By forming the hydrogen diffusion preventing film 5 as described above, the inner wall of the void is completely covered with the hydrogen diffusion preventing film 5, and even if some hollow portions remain, they are almost blocked. The blocking portion is substantially in a state where the film material is deposited thicker than the portion of the hydrogen diffusion preventing film 5 on the interlayer insulating film 3, and a firm block of moisture and hydrogen on the capacitor film. Will serve the function. Even if the upper portion of the hollow portion is opened by the cap insulating film 6, the void 4 portion is completely sealed with the hydrogen diffusion preventing film 5 and is completely sealed. A reliable block function from the side is realized.

なお、特許文献１〜３には、層間絶縁膜を形成する際に、配線間にボイドを形成する技術が開示されているが、層間絶縁膜の誘電率等を調節することに主眼を置いている。これに対して本発明は、飽くまで強誘電体キャパシタ構造を有するＦｅＲＡＭに固有の問題に対処するため、強誘電体キャパシタ構造の高いキャパシタ特性を保持すべく、水素拡散防止膜を利用してボイド内を埋め込む構成を採る。このように、本発明は明らかに特許文献１〜３とは別発明である。   Patent Documents 1 to 3 disclose a technique for forming a void between wirings when forming an interlayer insulating film. However, the main focus is on adjusting the dielectric constant and the like of the interlayer insulating film. Yes. On the other hand, in order to address the problems inherent in the FeRAM having a ferroelectric capacitor structure, the present invention uses a hydrogen diffusion prevention film to maintain the high capacitor characteristics of the ferroelectric capacitor structure. The structure which embeds is taken. Thus, the present invention is clearly another invention from Patent Documents 1 to 3.

−本発明を適用した具体的な実施形態−
以下、本発明を適用した具体的な緒実施形態として、いわゆるスタック型のＦｅＲＡＭを開示する。ここでは便宜上、ＦｅＲＡＭの構成をその製造方法と共に説明する。-Specific embodiment to which the present invention is applied-
Hereinafter, a so-called stack type FeRAM is disclosed as a specific embodiment to which the present invention is applied. Here, for convenience, the structure of the FeRAM will be described together with its manufacturing method.

（第１の実施形態）
図２Ａ〜図５Ｃは、第１の実施形態によるスタック型のＦｅＲＡＭの製造方法を工程順に示す概略断面図である。(First embodiment)
2A to 5C are schematic cross-sectional views illustrating a method of manufacturing the stack type FeRAM according to the first embodiment in the order of steps.

初めに、図２Ａに示すように、シリコン半導体基板１０上に選択トランジスタとして機能するトランジスタ構造２０ａ，２０ｂを形成する。   First, as shown in FIG. 2A, transistor structures 20 a and 20 b that function as selection transistors are formed on a silicon semiconductor substrate 10.

詳細には、先ず、シリコン半導体基板１０の表層に例えばＳＴＩ法により素子分離構造１１を形成し、素子活性領域を確定する。   Specifically, first, the element isolation structure 11 is formed on the surface layer of the silicon semiconductor substrate 10 by, for example, the STI method to determine the element active region.

次に、素子活性領域に不純物、ここではホウ素（Ｂ）を例えばドーズ量３．０×１０１３／ｃｍ２、加速エネルギー３００ｋｅＶの条件でイオン注入し、Ｎ活性領域にウェル１２を形成する。Next, an impurity, here boron (B), is ion-implanted into the element active region under a condition of a dose amount of 3.0 × 10 13 / cm 2 and an acceleration energy of 300 keV, for example, to form a well 12 in the N active region.

次に、素子活性領域に熱酸化等により膜厚３．０ｎｍ程度の薄いゲート絶縁膜１３を形成し、ゲート絶縁膜１３上にＣＶＤ法により膜厚１８０ｎｍ程度の多結晶シリコン膜及び膜厚２９ｎｍ程度の例えばシリコン窒化膜を堆積し、シリコン窒化膜、多結晶シリコン膜、及びゲート絶縁膜１３をリソグラフィー及びそれに続くドライエッチングにより電極形状に加工する。このとき、ゲート絶縁膜１３上にゲート電極１４をパターン形成される。   Next, a thin gate insulating film 13 having a thickness of about 3.0 nm is formed in the element active region by thermal oxidation or the like, and a polycrystalline silicon film having a thickness of about 180 nm and a thickness of about 29 nm are formed on the gate insulating film 13 by a CVD method. For example, a silicon nitride film is deposited, and the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 13 are processed into an electrode shape by lithography and subsequent dry etching. At this time, the gate electrode 14 is patterned on the gate insulating film 13.

次に、キャップ膜１５をマスクとして素子活性領域に不純物、ここでは砒素（Ａｓ）を例えばドーズ量５．０×１０１４／ｃｍ２、加速エネルギー１０ｋｅＶの条件でイオン注入し、いわゆるＬＤＤ領域１６を形成する。Next, using the cap film 15 as a mask, an impurity, for example, arsenic (As) here is ion-implanted into the element active region under the conditions of a dose amount of 5.0 × 10 14 / cm 2 and an acceleration energy of 10 keV to form a so-called LDD region 16. Form.

次に、全面に例えばシリコン酸化膜をＣＶＤ法により堆積し、このシリコン酸化膜をいわゆるエッチバックする。このとき、ゲート電極１４及びキャップ膜１５の側面のみにシリコン酸化膜が残り、サイドウォール絶縁膜１７が形成される。   Next, for example, a silicon oxide film is deposited on the entire surface by a CVD method, and this silicon oxide film is so-called etched back. At this time, the silicon oxide film remains only on the side surfaces of the gate electrode 14 and the cap film 15, and the sidewall insulating film 17 is formed.

次に、キャップ膜１５及びサイドウォール絶縁膜１７をマスクとして素子活性領域に不純物、ここではリン（Ｐ）をＬＤＤ領域１６よりも不純物濃度が高くなる条件、例えばドーズ量５．０×１０１４／ｃｍ２、加速エネルギー１３ｋｅＶの条件でイオン注入し、ＬＤＤ領域１６と重畳されるソース／ドレイン領域１８を形成して、トランジスタ構造２０ａ，２０ｂを完成させる。このとき同時に、ロジック回路領域でも、ソース／ドレイン領域を適宜形成して、トランジスタ構造を完成させる。Next, using the cap film 15 and the side wall insulating film 17 as a mask, impurities, in this case, phosphorus (P) in the element active region have a higher impurity concentration than the LDD region 16, for example, a dose of 5.0 × 10 14 / Ions are implanted under the conditions of cm 2 and acceleration energy of 13 keV to form the source / drain regions 18 overlapping the LDD regions 16 to complete the transistor structures 20a and 20b. At the same time, in the logic circuit region, source / drain regions are appropriately formed to complete the transistor structure.

続いて、図２Ｂに示すように、トランジスタ構造２０ａ，２０ｂの保護膜２１及び絶縁膜２２を形成する。その後、ソース／ドレイン領域１８の一方と接続される不図示のプラグを形成する。
詳細には、トランジスタ構造２０ａ，２０ｂを覆うように、保護膜２１及び絶縁膜２２を順次堆積する。ここで、保護膜２１としては、シリコン酸化膜を材料とし、ＣＶＤ法により膜厚２０ｎｍ程度に堆積する。絶縁膜２２としては、例えばプラズマＳｉＯ膜(膜厚２０ｎｍ程度)、プラズマＳｉＮ膜(膜厚８０ｎｍ程度)及びプラズマＴＥＯＳ膜(膜厚１０００ｎｍ程度)を順次成膜した積層構造を形成し、積層後、化学機械研磨（ＣＭＰ）により膜厚が７００ｎｍ程度となるまで研磨する。Subsequently, as shown in FIG. 2B, the protective film 21 and the insulating film 22 of the transistor structures 20a and 20b are formed. Thereafter, a plug (not shown) connected to one of the source / drain regions 18 is formed.
Specifically, the protective film 21 and the insulating film 22 are sequentially deposited so as to cover the transistor structures 20a and 20b. Here, as the protective film 21, a silicon oxide film is used as a material, and is deposited to a film thickness of about 20 nm by a CVD method. As the insulating film 22, for example, a laminated structure in which a plasma SiO film (film thickness of about 20 nm), a plasma SiN film (film thickness of about 80 nm) and a plasma TEOS film (film thickness of about 1000 nm) are sequentially formed is formed. Polishing is performed by chemical mechanical polishing (CMP) until the film thickness reaches about 700 nm.

次に、ソース／ドレイン領域１８の一方へのビア孔（不図示）を形成する。
詳細には、絶縁膜２２及び保護膜２１をリソグラフィー及びそれに続くドライエッチングにより加工し、ソース／ドレイン領域１８の一方の表面の一部を露出させるビア孔を形成する。Next, a via hole (not shown) to one of the source / drain regions 18 is formed.
Specifically, the insulating film 22 and the protective film 21 are processed by lithography and subsequent dry etching to form a via hole that exposes a part of one surface of the source / drain region 18.

次に、ビア孔の内壁面を覆うように、スパッタ法により例えばＴｉＮ膜を膜厚７５ｎｍ程度に堆積して、不図示の下地膜（グルー膜）を形成する。そして、ＣＶＤ法によりグルー膜を介してビア孔を埋め込むように、Ｗ，ＴｉＡｌＮ，ＴｉＮ，Ｔｉ，Ａｌ，Ｃｕ，Ｒｕ，ＳＲＯ，Ｉｒの単膜又は積層膜、ここではＷ膜を形成する。その後、ＣＭＰにより絶縁膜をストッパーとしてＷ膜及びグルー膜を研磨し、ビア孔内をグルー膜を介してＷで埋め込むプラグ（不図示）を形成する。   Next, a TiN film, for example, is deposited to a thickness of about 75 nm by a sputtering method so as to cover the inner wall surface of the via hole to form a base film (glue film) (not shown). Then, a single film or a laminated film of W, TiAlN, TiN, Ti, Al, Cu, Ru, SRO, and Ir, here, a W film is formed so as to fill the via hole through the glue film by the CVD method. Thereafter, the W film and the glue film are polished by CMP using the insulating film as a stopper to form a plug (not shown) that fills the via hole with W through the glue film.

続いて、図２Ｃに示すように、酸化防止膜３７及びプラズマＴＥＯＳ膜３８を形成した後、トランジスタ構造２０ａ，２０ｂのソース／ドレイン領域１８の他方と接続される各プラグ４２を形成する。   Subsequently, as shown in FIG. 2C, after forming the antioxidant film 37 and the plasma TEOS film 38, each plug 42 connected to the other of the source / drain regions 18 of the transistor structures 20a and 20b is formed.

詳細には、先ず上記のプラグ（不図示）の酸化防止膜３７を、ＣＶＤ法等により例えばＳｉＯＮを材料として膜厚１３０ｎｍ程度に形成する。
次に、プラズマＣＶＤ法により、膜厚２００ｎｍ程度のプラズマＴＥＯＳ膜３８を形成する。Specifically, first, the antioxidant film 37 of the plug (not shown) is formed to a thickness of about 130 nm by using, for example, SiON as a material by a CVD method or the like.
Next, a plasma TEOS film 38 having a thickness of about 200 nm is formed by plasma CVD.

次に、プラズマＴＥＯＳ膜３８、酸化防止膜３７、絶縁膜２２、及び保護膜２１をリソグラフィー及びそれに続くドライエッチングにより加工し、ソース／ドレイン領域１８の他方の表面の一部を露出させるビア孔３９を形成する。   Next, the plasma TEOS film 38, the antioxidant film 37, the insulating film 22, and the protective film 21 are processed by lithography and subsequent dry etching to expose a part of the other surface of the source / drain region 18. Form.

次に、ビア孔３９の各壁面を覆うように、スパッタ法により例えばＴｉＮ膜を膜厚７５ｎｍ程度に堆積して、下地膜（グルー膜）４１を形成する。そして、ＣＶＤ法によりグルー膜４１を介してビア孔３９を埋め込むように、Ｗ，ＴｉＡｌＮ，ＴｉＮ，Ｔｉ，Ａｌ，Ｃｕ，Ｒｕ，ＳＲＯ，Ｉｒの単膜又は積層膜、ここではＷ膜を形成する。その後、ＣＭＰによりプラズマＴＥＯＳ膜３８をストッパーとしてＷ膜及びグルー膜４１を研磨する。以上により、ビア孔３９内をグルー膜４１を介してＷで埋め込むプラグ４２を形成する。   Next, a base film (glue film) 41 is formed by depositing, for example, a TiN film with a film thickness of about 75 nm by sputtering so as to cover each wall surface of the via hole 39. Then, a single film or a laminated film of W, TiAlN, TiN, Ti, Al, Cu, Ru, SRO, and Ir, in this case, a W film is formed so as to fill the via hole 39 via the glue film 41 by the CVD method. . Thereafter, the W film and the glue film 41 are polished by CMP using the plasma TEOS film 38 as a stopper. In this way, the plug 42 that fills the via hole 39 with W via the glue film 41 is formed.

続いて、図３Ａに示すように、後述の強誘電体メモリキャパシタ構造３０ａ，３０ｂを形成するための保護下地膜４３、下部電極層４４、強誘電体膜４５、下層上部電極層４６、及び上層上部電極層４７を順次形成する。   Subsequently, as shown in FIG. 3A, a protective base film 43, a lower electrode layer 44, a ferroelectric film 45, a lower upper electrode layer 46, and an upper layer for forming later-described ferroelectric memory capacitor structures 30a and 30b are formed. The upper electrode layer 47 is formed sequentially.

詳細には、先ず、強誘電体膜４５の後述する酸素アニール処理に起因するプラグ４２の異常酸化、及びプラグ４２の形成時に当該プラグ４２内に取り込まれた水素の強誘電体膜４５への影響を共に抑制するため、導電膜である保護下地膜４３を、例えばスパッタ法により膜厚１００ｎｍ程度に形成する。保護下地膜４３の材料としては、ＴｉＡｌＮの単層、ＴｉＮとＴｉＡｌＮとの積層構造等、ここではＴｉＮとＴｉＡｌＮとの積層構造とする。   Specifically, first, abnormal oxidation of the plug 42 caused by an oxygen annealing process to be described later of the ferroelectric film 45, and the influence of hydrogen taken into the plug 42 when the plug 42 is formed on the ferroelectric film 45. In order to suppress both, a protective base film 43 that is a conductive film is formed to a thickness of about 100 nm by, for example, sputtering. The material of the protective base film 43 is a TiAlN single layer, a laminated structure of TiN and TiAlN, or the like, here a laminated structure of TiN and TiAlN.

次に、スパッタ法により、膜厚１００ｎｍ程度に例えばＩｒを堆積し、下部電極層４４を形成する。
次に、ＭＯＣＶＤ法により、４５０℃〜６５０℃程度、ここでは５５０℃にて下部電極層４４上に強誘電体である例えばＰＺＴからなる強誘電体膜４５を膜厚１００ｎｍ程度に堆積する。この際、強誘電体膜４５が成膜当初アモルファス状態にある場合はＲＴＡ処理を施して当該強誘電体膜４５を結晶化する。既に強誘電体４５が結晶化している場合は必ずしもＲＴＡ処理を必要としない。Next, Ir, for example, is deposited to a thickness of about 100 nm by sputtering to form the lower electrode layer 44.
Next, a ferroelectric film 45 made of a ferroelectric material such as PZT is deposited to a thickness of about 100 nm on the lower electrode layer 44 at about 450 ° C. to 650 ° C., here 550 ° C., by MOCVD. At this time, if the ferroelectric film 45 is initially in an amorphous state, the ferroelectric film 45 is crystallized by performing RTA treatment. When the ferroelectric 45 has already been crystallized, the RTA process is not necessarily required.

次に、反応性スパッタ法により、強誘電体膜４５上に例えば導電性酸化物であるＩｒＯ２を膜厚１００ｎｍ程度に堆積し、下層上部電極層４６を形成する。
そして、スパッタ法により、下層上部電極層４６上に例えばＩｒを膜厚１００ｎｍ程度に堆積し、上部電極層４７を形成する。Next, for example, IrO 2 , which is a conductive oxide, is deposited on the ferroelectric film 45 to a thickness of about 100 nm by a reactive sputtering method to form a lower upper electrode layer 46.
Then, for example, Ir is deposited to a thickness of about 100 nm on the lower upper electrode layer 46 by sputtering to form the upper electrode layer 47.

なお、下部電極層４４、強誘電体膜４５、下層上部電極層４６、及び上層上部電極層４７の材料としては、上記の場合も含め、Ｉｒ，ＩｒＯｘ（典型的にはｘ＝２），Ｐｔ，ＳＲＯ，ＬＮＯ，ＬＳＣＯ，Ｒｕ，ＲｕＯ２、ＳｒＲｕＯ３等から選ばれた少なくとも１種がそれぞれ用いられる。The materials of the lower electrode layer 44, the ferroelectric film 45, the lower upper electrode layer 46, and the upper upper electrode layer 47 include Ir, IrOx (typically x = 2), Pt, including the above cases. , SRO, LNO, LSCO, Ru, RuO 2 , SrRuO 3 and the like are used.

続いて、図３Ｂに示すように、ハードマスク材料４８を形成する。
詳細には、上層上部電極層４７上に、ＣＶＤ法等により例えばＴＥＯＳ膜を膜厚６００ｎｍ程度に堆積し、ハードマスク材料４８を形成する。Subsequently, as shown in FIG. 3B, a hard mask material 48 is formed.
More specifically, a hard mask material 48 is formed on the upper upper electrode layer 47 by depositing, for example, a TEOS film with a thickness of about 600 nm by a CVD method or the like.

続いて、図３Ｃに示すように、強誘電体メモリキャパシタ構造３０ａ，３０ｂを形成する。   Subsequently, as shown in FIG. 3C, ferroelectric memory capacitor structures 30a and 30b are formed.

詳細には、ハードマスク材料４８を用い、例えば４００℃にて、上層上部電極層４７、下層上部電極層４６、強誘電体膜４５、下部電極層４４、及び保護下地膜４３を一括エッチングする。そして、ハードマスク材料４８をウェットエッチング等で除去する。以上により、素子活性領域にプラグ４２と保護下地膜４３を介し、下部電極層４４からなる下部電極５１と、下層上部電極層４６及び上層上部電極層４７の積層構造である上部電極５２とで強誘電体膜４５を挟持してなる、強誘電体メモリキャパシタ構造３０ａ，３０ｂが完成する。ここで、図示の例では、強誘電体メモリキャパシタ構造３０ａ，３０ｂ間距離は例えば０．１８μｍ程度であり、両者が極めて近接する部分の断面を示している。   Specifically, using the hard mask material 48, the upper upper electrode layer 47, the lower upper electrode layer 46, the ferroelectric film 45, the lower electrode layer 44, and the protective base film 43 are collectively etched at 400 ° C., for example. Then, the hard mask material 48 is removed by wet etching or the like. As described above, the lower electrode 51 formed of the lower electrode layer 44 and the upper electrode 52 having a laminated structure of the lower upper electrode layer 46 and the upper upper electrode layer 47 are strong in the element active region through the plug 42 and the protective base film 43. Ferroelectric memory capacitor structures 30a and 30b each having the dielectric film 45 interposed therebetween are completed. Here, in the illustrated example, the distance between the ferroelectric memory capacitor structures 30a and 30b is, for example, about 0.18 μm, and shows a cross section of a portion where both are very close to each other.

続いて、図４Ａに示すように、強誘電体メモリキャパシタ構造３０ａ，３０ｂを覆う水素拡散防止膜５３を形成した後、層間絶縁膜５４を形成する。   Subsequently, as shown in FIG. 4A, after forming a hydrogen diffusion preventing film 53 covering the ferroelectric memory capacitor structures 30a and 30b, an interlayer insulating film 54 is formed.

詳細には、先ず、強誘電体メモリキャパシタ構造３０ａ，３０ｂを覆うように、プラズマＴＥＯＳ膜３８上に金属酸化膜、例えばＡｌ酸化物（アルミナ）を材料としてスパッタ法により膜厚３０ｎｍ程度に堆積し、水素拡散防止膜５３を形成する。この水素拡散防止膜５３により、例えば後工程により形成されるシリコン酸化膜等からの水分・水素の強誘電体膜４５への浸入が抑止され、強誘電体膜４５へのダメージが防止される。水素拡散防止膜５３としては、アルミナの代わりに、Ａｌ窒化物、Ｔａ酸化物、Ｔａ窒化物、Ｔｉ酸化物、及びＺｒ酸化物から選ばれた一種を用いても良い。   Specifically, first, a metal oxide film, for example, an Al oxide (alumina) is deposited on the plasma TEOS film 38 to a thickness of about 30 nm by a sputtering method so as to cover the ferroelectric memory capacitor structures 30a and 30b. Then, a hydrogen diffusion preventing film 53 is formed. The hydrogen diffusion preventing film 53 prevents moisture and hydrogen from entering the ferroelectric film 45 from, for example, a silicon oxide film formed in a later process, and prevents damage to the ferroelectric film 45. As the hydrogen diffusion preventing film 53, one kind selected from Al nitride, Ta oxide, Ta nitride, Ti oxide, and Zr oxide may be used instead of alumina.

次に、強誘電体膜４５に対して低ダメージとなる材料・条件、例えばＣＶＤ法により含有水分量の抑制されたＰＥ−ＴＥＯＳ−ＳｉＯを用いて、水素拡散防止膜５３を介して強誘電体メモリキャパシタ構造３０ａ，３０ｂを覆うように、ＰＥ−ＴＥＯＳ−ＳｉＯを膜厚１．４μｍ程度に堆積して層間絶縁膜５４を形成する。このとき、強誘電体メモリキャパシタ構造３０ａ，３０ｂが近接して配置されており、強誘電体膜４５に対して低ダメージとなる材料・条件で層間絶縁膜５４を形成したため、強誘電体メモリキャパシタ構造３０ａ，３０ｂ間の領域を層間絶縁膜５４で完全に埋め込むことはできず、層間絶縁膜５４内の当該領域に空隙（ボイド）５５が発生する。   Next, the material and conditions that cause low damage to the ferroelectric film 45, for example, PE-TEOS-SiO in which the moisture content is suppressed by the CVD method, are used for the ferroelectric through the hydrogen diffusion prevention film 53. An interlayer insulating film 54 is formed by depositing PE-TEOS-SiO to a thickness of about 1.4 μm so as to cover the memory capacitor structures 30a and 30b. At this time, since the ferroelectric memory capacitor structures 30a and 30b are arranged close to each other and the interlayer insulating film 54 is formed with a material and conditions that cause low damage to the ferroelectric film 45, the ferroelectric memory capacitor is formed. The region between the structures 30 a and 30 b cannot be completely filled with the interlayer insulating film 54, and a void 55 is generated in the region in the interlayer insulating film 54.

ここで、強誘電体膜４５に対して低ダメージとなる条件、即ちさほど緻密ではなくとも含有水分量を抑制した状態でボイド５５の発生を容認する条件であれば、例えばＨＤＰ−ＣＶＤ法を用いて層間絶縁膜５４を形成しても良い。   Here, for example, the HDP-CVD method is used as long as it is a condition that causes a low damage to the ferroelectric film 45, that is, a condition that allows the generation of the void 55 in a state where the contained moisture content is suppressed even if it is not so dense. Alternatively, the interlayer insulating film 54 may be formed.

続いて、図４Ｂに示すように、層間絶縁膜５４の表層を平坦化する。
詳細には、層間絶縁膜５４の表層を例えばＣＭＰ法により除去し、層間絶縁膜５４の表面を平坦化する。ここで図示のように、層間絶縁膜５４に内包されるようにボイド５５が発生した場合には、ボイド５５の上部を適宜開口させる程度に研磨除去する。このとき、層間絶縁膜５４の表面は、当該表面からボイド５５の上部が開口した状態で平坦化される。ボイド５５の開口部を５５ａと記す。Subsequently, as shown in FIG. 4B, the surface layer of the interlayer insulating film 54 is planarized.
Specifically, the surface layer of the interlayer insulating film 54 is removed by, for example, a CMP method, and the surface of the interlayer insulating film 54 is planarized. Here, as shown in the figure, when the void 55 is generated so as to be included in the interlayer insulating film 54, it is polished and removed to such an extent that the upper portion of the void 55 is appropriately opened. At this time, the surface of the interlayer insulating film 54 is planarized with the upper portion of the void 55 opened from the surface. The opening of the void 55 is denoted as 55a.

ここで、層間絶縁膜５４を形成した後に、当該層間絶縁膜５４の脱水処理及び膜質改善を目的として、層間絶縁膜５４にプラズマ処理を施しても好適である。このプラズマ処理は例えば、Ｎ２ガス種又はＮ２Ｏガス種を用いて、２００℃〜４５０℃の温度で実行する。Here, after the interlayer insulating film 54 is formed, the interlayer insulating film 54 is preferably subjected to plasma treatment for the purpose of dehydrating the interlayer insulating film 54 and improving the film quality. This plasma treatment is performed at a temperature of 200 ° C. to 450 ° C. using N 2 gas species or N 2 O gas species, for example.

続いて、図４Ｃに示すように、層間絶縁膜５４上に金属酸化膜、例えばＡｌ酸化物（アルミナ）を材料として、水素拡散防止膜５６を形成する。この水素拡散防止膜５６は、水素拡散防止膜５３と同様に、強誘電体膜４５の特性劣化を防止する機能を有している。即ち、水素拡散防止膜５６により、水素拡散防止膜５３と相俟って、例えば後工程により形成されるシリコン酸化膜等からの水分・水素の強誘電体膜４５への浸入がより確実に抑止され、強誘電体膜４５へのダメージが防止される。水素拡散防止膜５６としては、アルミナの代わりに、Ａｌ窒化物、Ｔａ酸化物、Ｔａ窒化物、Ｔｉ酸化物、及びＺｒ酸化物から選ばれた一種を用いても良い。   4C, a hydrogen diffusion preventing film 56 is formed on the interlayer insulating film 54 using a metal oxide film, for example, Al oxide (alumina). Similar to the hydrogen diffusion preventing film 53, the hydrogen diffusion preventing film 56 has a function of preventing characteristic deterioration of the ferroelectric film 45. That is, the hydrogen diffusion preventive film 56, together with the hydrogen diffusion preventive film 53, more reliably inhibits the entry of moisture and hydrogen into the ferroelectric film 45 from, for example, a silicon oxide film formed in a later process. Thus, damage to the ferroelectric film 45 is prevented. As the hydrogen diffusion preventing film 56, one kind selected from Al nitride, Ta oxide, Ta nitride, Ti oxide, and Zr oxide may be used instead of alumina.

本実施形態では、水素拡散防止膜５６を、ボイド５５の少なくとも内壁面を完全に覆う条件で層間絶縁膜５４上に形成する。水素拡散防止膜５６を上記の条件を満たすように形成することから、その形成法として被覆性に優れたＭＯ−ＣＶＤ法を用いる。ここでは、成長温度２００℃〜５００℃、圧力０．２torr〜１．０torrで、流量１０ｓｌｍでＯ２＋Ｏ３の混合ガスと、流量１００ｓｃｃｍのＴＭＡ（Ａｌ（ＣＨ３）３）とをチャンバー内へ交互に供給しながら、水素拡散防止膜５６を膜厚５０ｎｍ程度に成長させる（無ＡＬＤ（Atomic
Layer Deposition）法）。In the present embodiment, the hydrogen diffusion preventing film 56 is formed on the interlayer insulating film 54 under the condition that at least the inner wall surface of the void 55 is completely covered. Since the hydrogen diffusion prevention film 56 is formed so as to satisfy the above-described conditions, the MO-CVD method having excellent coverage is used as the formation method. Here, a mixed gas of O 2 + O 3 at a growth temperature of 200 ° C. to 500 ° C., a pressure of 0.2 torr to 1.0 torr, and a flow rate of 10 slm, and TMA (Al (CH 3 ) 3 ) at a flow rate of 100 sccm into the chamber. While alternately supplying, the hydrogen diffusion preventing film 56 is grown to a thickness of about 50 nm (non-ALD (Atomic)
Layer Deposition)).

ここで、水素拡散防止膜５６をＭＯ−ＣＶＤ法により単層膜として形成する代わりに、２層膜として形成しても良い。この場合、例えば先ずスパッタ法により水素拡散防止膜５６の材料膜を膜厚２０ｎｍ程度に堆積し、続いてＭＯ−ＣＶＤ法により水素拡散防止膜５６の材料膜を膜厚５０ｎｍ程度に堆積する。又は、先ずＭＯ−ＣＶＤ法により水素拡散防止膜５６の材料膜を膜厚５０ｎｍ程度に堆積し、続いてスパッタ法により水素拡散防止膜５６の材料膜を膜厚２０ｎｍ程度に堆積する。   Here, the hydrogen diffusion preventing film 56 may be formed as a two-layer film instead of being formed as a single-layer film by the MO-CVD method. In this case, for example, the material film of the hydrogen diffusion preventing film 56 is first deposited to a film thickness of about 20 nm by sputtering, and then the material film of the hydrogen diffusion preventing film 56 is deposited to a film thickness of about 50 nm by the MO-CVD method. Alternatively, the material film of the hydrogen diffusion preventing film 56 is first deposited to a film thickness of about 50 nm by the MO-CVD method, and then the material film of the hydrogen diffusion preventing film 56 is deposited to the film thickness of about 20 nm by the sputtering method.

後者の場合では、ＭＯ−ＣＶＤ法の材料膜によりボイド５５の少なくとも内壁が完全に覆われた状態とされ、スパッタ法の材料膜によりボイド５５の開口５５ａが確実に閉塞される。   In the latter case, at least the inner wall of the void 55 is completely covered by the MO-CVD method material film, and the opening 55a of the void 55 is reliably closed by the sputtering method material film.

続いて、図５Ａに示すように、水素拡散防止膜５６上を覆うキャップ絶縁膜５７を形成する。
詳細には、例えばＣＶＤ法により、シリコン酸化膜を膜厚３０ｎｍ程度に堆積し、キャップ絶縁膜５７を形成する。Subsequently, as shown in FIG. 5A, a cap insulating film 57 covering the hydrogen diffusion preventing film 56 is formed.
Specifically, a cap insulating film 57 is formed by depositing a silicon oxide film with a film thickness of about 30 nm by, eg, CVD.

上記のように水素拡散防止膜５６を形成することにより、ボイド５５の内壁は水素拡散防止膜５６により覆われ、若干の空洞部分が残るとしても殆ど閉塞する。この閉塞部分は、実質的にみれば、水素拡散防止膜５６の層間絶縁膜５４上の部分に比して厚く膜材料が堆積した状態とされており、強誘電体膜４５に対する水分・水素の堅固なブロック機能を果たすことになる。そして、キャップ絶縁膜５７により、仮に前記空洞部分の上部が開口されていたとしても、ボイド５５の部分は水素拡散防止膜５６によりほぼ充填された状態で完全に密閉された状態となり、強誘電体膜４５に対する側面方向からの確実な前記ブロック機能が実現する。   By forming the hydrogen diffusion preventing film 56 as described above, the inner wall of the void 55 is covered with the hydrogen diffusion preventing film 56 and is almost closed even if a slight cavity portion remains. The blocking portion is substantially in a state in which the film material is deposited thicker than the portion of the hydrogen diffusion preventing film 56 on the interlayer insulating film 54, and moisture / hydrogen with respect to the ferroelectric film 45 is deposited. It will perform a solid block function. Even if the upper portion of the cavity portion is opened by the cap insulating film 57, the void 55 portion is almost completely filled with the hydrogen diffusion preventing film 56 and is completely sealed. The reliable blocking function from the side surface direction with respect to the film 45 is realized.

続いて、図５Ｂに示すように、強誘電体メモリキャパシタ構造３０ａ，３０ｂの上部電極５２と接続されるプラグ６０を形成する。   Subsequently, as shown in FIG. 5B, a plug 60 connected to the upper electrode 52 of the ferroelectric memory capacitor structure 30a, 30b is formed.

ここでは、先ず、リソグラフィー及びドライエッチングにより、上記のプラグ（不図示）の上方に整合した部位でキャップ絶縁膜５７、水素拡散防止膜５６、層間絶縁膜５４、水素拡散防止膜５３、プラズマＴＥＯＳ膜３８、及び酸化防止膜３７をパターニングする。このパターニングにより、上記のプラグ（不図示）の表面の少なくとも一部を露出させるビア孔（不図示）を形成する。   Here, first, a cap insulating film 57, a hydrogen diffusion preventing film 56, an interlayer insulating film 54, a hydrogen diffusion preventing film 53, and a plasma TEOS film are formed by lithography and dry etching at a position aligned above the plug (not shown). 38 and the antioxidant film 37 are patterned. By this patterning, a via hole (not shown) that exposes at least a part of the surface of the plug (not shown) is formed.

次に、上記のビア孔（不図示）の内壁面にグルー膜を形成した後、当該ビア孔をグルー膜を介してＷで充填するプラグ（不図示）を形成する。   Next, after forming a glue film on the inner wall surface of the via hole (not shown), a plug (not shown) for filling the via hole with W through the glue film is formed.

次に、リソグラフィー及びドライエッチングにより、強誘電体メモリキャパシタ構造３０ａ，３０ｂの上部電極５２の上方に整合した部位で、キャップ絶縁膜５７、水素拡散防止膜５６、層間絶縁膜５４、及び水素拡散防止膜５３をパターニングする。このパターニングにより、各上部電極５２の表面の一部を露出させるビア孔５８を形成する。   Next, a cap insulating film 57, a hydrogen diffusion preventing film 56, an interlayer insulating film 54, and a hydrogen diffusion preventing part are aligned at positions above the upper electrodes 52 of the ferroelectric memory capacitor structures 30a and 30b by lithography and dry etching. The film 53 is patterned. By this patterning, a via hole 58 that exposes a part of the surface of each upper electrode 52 is formed.

その後、強誘電体メモリキャパシタ構造３０ａ，３０ｂのエッチング時に受けたダメージを回復するために、酸素アニール処理を実行する。ここでは例えば、処理温度５００℃、酸素雰囲気で６０分間のアニール処理を実行する。本実施形態では、強誘電体メモリキャパシタ構造３０ａ，３０ｂとプラグ４２との間に保護下地膜４３が設けられているため、この酸素アニール処理を実行してもプラグ４２の異常酸化が防止される。それと共に、保護下地膜４３によりプラグ４２の形成時に当該プラグ４２内に取り込まれた水素の発生が抑止される。   Thereafter, an oxygen annealing process is performed in order to recover the damage received during the etching of the ferroelectric memory capacitor structures 30a and 30b. Here, for example, annealing is performed for 60 minutes in a processing temperature of 500 ° C. and in an oxygen atmosphere. In this embodiment, since the protective base film 43 is provided between the ferroelectric memory capacitor structures 30a and 30b and the plug 42, abnormal oxidation of the plug 42 is prevented even if this oxygen annealing process is performed. . At the same time, generation of hydrogen taken into the plug 42 when the plug 42 is formed is suppressed by the protective base film 43.

次に、ビア孔５８の各壁面を覆うように、スパッタ法により例えばＴｉＮ膜を膜厚７５ｎｍ程度に堆積して、下地膜（グルー膜）５９を形成する。そして、ＣＶＤ法によりグルー膜５９を介してビア孔５８を埋め込むように、Ｗ，ＴｉＡｌＮ，ＴｉＮ，Ｔｉ，Ａｌ，Ｃｕ，Ｒｕ，ＳＲＯ，Ｉｒの単膜又は積層膜、ここではＷ膜を形成する。その後、キャップ絶縁膜５７をストッパーとしてＷ膜及びグルー膜５９を研磨し、ビア孔５８内をグルー膜５９を介してＷで埋め込むプラグ６０を形成する。   Next, a base film (glue film) 59 is formed by depositing, for example, a TiN film with a film thickness of about 75 nm by sputtering so as to cover each wall surface of the via hole 58. Then, a single film or a laminated film of W, TiAlN, TiN, Ti, Al, Cu, Ru, SRO, and Ir, in this case, a W film is formed so as to fill the via hole 58 through the glue film 59 by the CVD method. . Thereafter, the W film and the glue film 59 are polished using the cap insulating film 57 as a stopper to form a plug 60 that fills the via hole 58 with W via the glue film 59.

続いて、図５Ｃに示すように、プラグ６０及び上記のプラグ（不図示）と接続される配線６４をそれぞれ形成する。   Subsequently, as shown in FIG. 5C, plugs 60 and wirings 64 connected to the plugs (not shown) are formed.

詳細には、先ず、スパッタ法により、例えばＴｉＮを膜厚６０ｎｍ程度に堆積してバリアメタル膜６１を形成する。   Specifically, first, a barrier metal film 61 is formed by depositing, for example, TiN to a thickness of about 60 nm by sputtering.

次に、スパッタ法により、例えばＡｌ−Ｃｕ合金を膜厚３６０ｎｍ程度に堆積して配線層６２を形成する。
次に、スパッタ法により、例えばＴｉＮとＴｉの積層膜を膜厚７０ｎｍ程度に堆積してバリアメタル膜６３を形成する。Next, for example, an Al—Cu alloy is deposited to a film thickness of about 360 nm by sputtering to form the wiring layer 62.
Next, a barrier metal film 63 is formed by depositing, for example, a laminated film of TiN and Ti to a thickness of about 70 nm by sputtering.

次に、バリアメタル膜６１、配線層６２、及びバリアメタル膜６３をリソグラフィー及びドライエッチングによりパターニングする。このパターニングにより、プラグ６０と接続される各配線６４が形成される。ここで、配線６４と同時に、上記のプラグ（不図示）と接続される配線が形成される。   Next, the barrier metal film 61, the wiring layer 62, and the barrier metal film 63 are patterned by lithography and dry etching. By this patterning, each wiring 64 connected to the plug 60 is formed. Here, a wiring connected to the plug (not shown) is formed simultaneously with the wiring 64.

しかる後、層間絶縁膜や上層配線、保護絶縁膜等の形成を経て、本実施形態によるスタック型のＦｅＲＡＭが完成する。   Thereafter, through the formation of an interlayer insulating film, an upper layer wiring, a protective insulating film, etc., the stack type FeRAM according to the present embodiment is completed.

以上説明したように、本実施形態によれば、層間絶縁膜５４から水分や水素を発生させることなく、ボイド５５が発生しても強誘電体キャパシタ構造３０ａ，３０ｂには悪影響を及ぼすことなく高いキャパシタ特性を確実に保持し、信頼性の高いＦｅＲＡＭが実現する。   As described above, according to the present embodiment, moisture and hydrogen are not generated from the interlayer insulating film 54, and even if the void 55 is generated, the ferroelectric capacitor structures 30a and 30b are not adversely affected. A highly reliable FeRAM is realized that reliably retains capacitor characteristics.

（第２の実施形態）
本実施形態では、第１の実施形態と同様にスタック型のＦｅＲＡＭの製造方法を示すが、第１の実施形態の装置構成に加え、配線の層間絶縁膜にも本発明を適用する。(Second Embodiment)
In the present embodiment, a manufacturing method of a stack type FeRAM is shown as in the first embodiment, but the present invention is also applied to an interlayer insulating film of wiring in addition to the device configuration of the first embodiment.

第１の実施形態では説明を省略したが、強誘電体キャパシタ構造３０ａ，３０ｂの各上部電極５２と接続される配線は、例えば、各々層間絶縁膜に形成されたプラグを介して多層、例えば全体で５層に積層され、多層配線構造とされる。ここでは便宜上、配線、当該配線を覆う層間絶縁膜（水素拡散防止膜、キャップ絶縁膜）、及び上層の配線と接続されるプラグからなる構成を、各層の配線構造と称する。第１の実施形態の図５Ｃでは、この多層配線構造のうち、１層目の配線構造の配線６４が形成された様子が示されている。   Although the description is omitted in the first embodiment, the wiring connected to each upper electrode 52 of the ferroelectric capacitor structures 30a, 30b is, for example, a multilayer, for example, the whole via plugs formed in the interlayer insulating film. Thus, a multilayer wiring structure is formed by laminating five layers. Here, for the sake of convenience, a configuration including a wiring, an interlayer insulating film (hydrogen diffusion preventing film, cap insulating film) covering the wiring, and a plug connected to the upper wiring is referred to as a wiring structure of each layer. FIG. 5C of the first embodiment shows a state in which the wiring 64 of the first wiring structure is formed in the multilayer wiring structure.

本実施形態では、上記の多層配線構造のうち、最上層を除く少なくとも１層に本発明を適用する。
図６Ａ〜図７Ｃは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法のうち、その主要工程のみを示す概略断面図である。図示の例では、多層配線構造のうちの最上層を除く或る１層（５層構造であれば、５層目を除く１層目〜４層目のうちの１層）の形成工程を示している。従ってこの場合、当該或る１層が１層目の配線構造であれば、配線下にはプラグ６０等が接続されており、２層目〜４層目のうちの１層であれば、配線下にはその下層の配線構造のプラグ等が接続されている。以下では便宜上、プラグ６０等又は上記のプラグ等を含む下部構造を、単に下部構造１００として示す。In the present embodiment, the present invention is applied to at least one layer excluding the uppermost layer in the multilayer wiring structure.
FIG. 6A to FIG. 7C are schematic cross-sectional views showing only the main steps in the stack type FeRAM manufacturing method according to the second embodiment. In the illustrated example, a process of forming a certain layer excluding the uppermost layer of the multilayer wiring structure (if the five-layer structure, one of the first to fourth layers excluding the fifth layer) is shown. ing. Therefore, in this case, if the certain one layer is the first layer wiring structure, the plug 60 or the like is connected under the wiring, and if it is one of the second to fourth layers, the wiring Underneath, a plug or the like of the underlying wiring structure is connected. Hereinafter, for convenience, the lower structure including the plug 60 or the like or the above-described plug or the like is simply referred to as the lower structure 100.

先ず、図６Ａに示すように、第１の実施形態における図６Ｃの配線６４と同様に、プラグ６０等又は上記のプラグ等と接続される配線１０４（バリアメタル膜と同様のバリアメタル膜１０１、配線層６２と同様の配線層１０２、及びバリアメタル膜６３と同様のバリアメタル膜１０３からなる）を形成する。隣接する配線１０４間距離は例えば０．１８μｍ程度であり、両者は極めて近接しているものとする。なお、上述のように、配線１０４が１層目の配線構造のものであれば、配線１０４は配線６４と同一である。   First, as shown in FIG. 6A, like the wiring 64 of FIG. 6C in the first embodiment, a wiring 104 (a barrier metal film 101 similar to a barrier metal film, A wiring layer 102 similar to the wiring layer 62 and a barrier metal film 103 similar to the barrier metal film 63 are formed. The distance between adjacent wirings 104 is, for example, about 0.18 μm, and both are very close to each other. As described above, the wiring 104 is the same as the wiring 64 if the wiring 104 has a first-layer wiring structure.

続いて、配線１０４を覆う層間絶縁膜１０５を形成する。
詳細には、強誘電体メモリキャパシタ構造３０ａ，３０ｂの強誘電体膜４５に対して低ダメージとなる材料・条件、例えばＣＶＤ法により含有水分量の抑制されたＰＥ−ＴＥＯＳ−ＳｉＯを用いて、配線１０４を覆うように下部構造１００上に層間絶縁膜１０５を形成する。このとき、各配線１０４が近接して配置されており、強誘電体膜４５に対して低ダメージとなる材料・条件で層間絶縁膜１０５を形成したため、各配線１０４間の領域を層間絶縁膜１０５で完全に埋め込むことはできず、層間絶縁膜１０５内の当該領域に空隙（ボイド）１０６が発生する。Subsequently, an interlayer insulating film 105 covering the wiring 104 is formed.
Specifically, materials and conditions that cause low damage to the ferroelectric film 45 of the ferroelectric memory capacitor structures 30a and 30b, for example, PE-TEOS-SiO whose moisture content is suppressed by the CVD method, An interlayer insulating film 105 is formed on the lower structure 100 so as to cover the wiring 104. At this time, since the wirings 104 are arranged close to each other and the interlayer insulating film 105 is formed with a material and conditions that cause low damage to the ferroelectric film 45, the region between the wirings 104 is formed in the interlayer insulating film 105. Therefore, a gap 106 is generated in the region in the interlayer insulating film 105.

ここで、強誘電体膜４５に対して低ダメージとなる条件、即ちさほど緻密ではなくとも含有水分量を抑制した状態でボイド１０６の発生を容認する条件であれば、例えばＨＤＰ−ＣＶＤ法を用いて層間絶縁膜１０５を形成しても良い。   Here, for example, an HDP-CVD method is used as long as it is a condition that causes low damage to the ferroelectric film 45, that is, a condition that allows the generation of the void 106 in a state in which the contained moisture content is suppressed even if it is not so dense. Alternatively, the interlayer insulating film 105 may be formed.

続いて、図６Ｂに示すように、層間絶縁膜１０５の表層を平坦化する。
詳細には、層間絶縁膜１０５の表層を例えばＣＭＰ法により除去し、層間絶縁膜１０５の表面を平坦化する。ここで図示のように、層間絶縁膜５４に内包されるようにボイド１０６が発生した場合には、ボイド１０６の上部を適宜開口させる程度に研磨除去する。このとき、層間絶縁膜１０５の表面は、当該表面からボイド１０６の上部が開口した状態で平坦化される。ボイド１０６の開口部を１０６ａと記す。Subsequently, as shown in FIG. 6B, the surface layer of the interlayer insulating film 105 is planarized.
Specifically, the surface layer of the interlayer insulating film 105 is removed by, for example, a CMP method, and the surface of the interlayer insulating film 105 is planarized. Here, as shown in the figure, when the void 106 is generated so as to be included in the interlayer insulating film 54, it is polished and removed to such an extent that the upper portion of the void 106 is appropriately opened. At this time, the surface of the interlayer insulating film 105 is planarized with the upper portion of the void 106 opened from the surface. The opening of the void 106 is denoted as 106a.

ここで、層間絶縁膜１０５を形成した後に、当該層間絶縁膜１０５の脱水処理及び膜質改善を目的として、層間絶縁膜１０５にプラズマ処理を施しても好適である。このプラズマ処理は例えば、Ｎ２ガス種又はＮ２Ｏガス種を用いて、２００℃〜４５０℃の温度で実行する。Here, after the interlayer insulating film 105 is formed, the interlayer insulating film 105 is preferably subjected to plasma treatment for the purpose of dehydrating the interlayer insulating film 105 and improving the film quality. This plasma treatment is performed at a temperature of 200 ° C. to 450 ° C. using N 2 gas species or N 2 O gas species, for example.

続いて、図６Ｃに示すように、層間絶縁膜１０５上に金属酸化膜、例えばＡｌ酸化物（アルミナ）を材料として水素拡散防止膜１０７を形成する。この水素拡散防止膜１０７は、強誘電体膜４５の特性劣化を防止する機能を有している。即ち、水素拡散防止膜１０７により、例えば外界や後工程により形成される上層の配線構造からの水分・水素の強誘電体膜４５への浸入が抑止され、強誘電体膜４５へのダメージが防止される。本実施形態では、更に水素拡散防止膜５３，５６が形成されており、水素拡散防止膜１０７により、これら水素拡散防止膜５３，５６と相俟って、水分・水素の強誘電体膜４５への浸入がより確実に抑止され、強誘電体膜４５へのダメージが防止される。水素拡散防止膜１０７としては、アルミナの代わりに、Ａｌ窒化物、Ｔａ酸化物、Ｔａ窒化物、Ｔｉ酸化物、及びＺｒ酸化物から選ばれた一種を用いても良い。   Subsequently, as shown in FIG. 6C, a hydrogen diffusion preventing film 107 is formed on the interlayer insulating film 105 using a metal oxide film, for example, Al oxide (alumina). This hydrogen diffusion preventing film 107 has a function of preventing the characteristic deterioration of the ferroelectric film 45. In other words, the hydrogen diffusion prevention film 107 prevents moisture and hydrogen from entering the ferroelectric film 45 from, for example, the upper wiring structure formed by the outside world or a subsequent process, and prevents damage to the ferroelectric film 45. Is done. In this embodiment, hydrogen diffusion preventing films 53 and 56 are further formed. The hydrogen diffusion preventing film 107 and the hydrogen diffusion preventing films 53 and 56 are combined with the moisture / hydrogen ferroelectric film 45. Is more reliably prevented, and damage to the ferroelectric film 45 is prevented. As the hydrogen diffusion preventing film 107, one kind selected from Al nitride, Ta oxide, Ta nitride, Ti oxide, and Zr oxide may be used instead of alumina.

本実施形態では、水素拡散防止膜１０７を、ボイド１０６の少なくとも内壁面を完全に覆う条件で層間絶縁膜１０５上に形成する。水素拡散防止膜１０７を上記の条件を満たすように形成することから、その形成法として被覆性に優れたＭＯ−ＣＶＤ法を用いる。ここでは、成長温度２００℃〜５００℃、圧力０．２torr〜１．０torrで、流量１０ｓｌｍでＯ2＋Ｏ3の混合ガスと、流量１００ｓｃｃｍのＴＭＡ（Ａｌ（ＣＨ3）3）とをチャンバー内へ交互に供給しながら、水素拡散防止膜１０７を膜厚５０ｎｍ程度に成長させる（ＡＬＤ（Atomic Layer Deposition）法）。 In this embodiment, the hydrogen diffusion preventing film 107 is formed on the interlayer insulating film 105 under the condition that at least the inner wall surface of the void 106 is completely covered. Since the hydrogen diffusion prevention film 107 is formed so as to satisfy the above-described conditions, the MO-CVD method having excellent coverage is used as the formation method. Here, a mixed gas of O 2 + O 3 at a growth temperature of 200 ° C. to 500 ° C., a pressure of 0.2 torr to 1.0 torr, and a flow rate of 10 slm, and TMA (Al (CH 3 ) 3 ) at a flow rate of 100 sccm into the chamber. While supplying alternately, the hydrogen diffusion preventing film 107 is grown to a film thickness of about 50 nm ( ALD (Atomic Layer Deposition) method).

ここで、水素拡散防止膜１０７をＭＯ−ＣＶＤ法により単層膜として形成する代わりに、２層膜として形成しても良い。この場合、例えば先ずスパッタ法により水素拡散防止膜１０７の材料膜を膜厚２０ｎｍ程度に堆積し、続いてＭＯ−ＣＶＤ法により水素拡散防止膜１０７の材料膜を膜厚５０ｎｍ程度に堆積する。又は、先ずＭＯ−ＣＶＤ法により水素拡散防止膜１０７の材料膜を膜厚５０ｎｍ程度に堆積し、続いてスパッタ法により水素拡散防止膜１０７の材料膜を膜厚２０ｎｍ程度に堆積する。   Here, the hydrogen diffusion preventing film 107 may be formed as a two-layer film instead of being formed as a single-layer film by the MO-CVD method. In this case, for example, the material film of the hydrogen diffusion preventing film 107 is first deposited to a film thickness of about 20 nm by sputtering, and then the material film of the hydrogen diffusion preventing film 107 is deposited to a film thickness of about 50 nm by the MO-CVD method. Alternatively, the material film of the hydrogen diffusion preventing film 107 is first deposited to a film thickness of about 50 nm by the MO-CVD method, and then the material film of the hydrogen diffusion preventing film 107 is deposited to the film thickness of about 20 nm by the sputtering method.

後者の場合では、ＭＯ−ＣＶＤ法の材料膜によりボイド１０６の少なくとも内壁が完全に覆われた状態とされ、スパッタ法の材料膜によりボイド１０６の開口１０６ａが確実に閉塞される。   In the latter case, at least the inner wall of the void 106 is completely covered by the MO-CVD method material film, and the opening 106 a of the void 106 is reliably closed by the sputtering method material film.

続いて、図７Ａに示すように、水素拡散防止膜１０７上を覆うキャップ絶縁膜１０８を形成する。
詳細には、例えばＣＶＤ法により、シリコン酸化膜を膜厚３０ｎｍ程度に堆積し、キャップ絶縁膜１０８を形成する。Subsequently, as shown in FIG. 7A, a cap insulating film 108 covering the hydrogen diffusion preventing film 107 is formed.
More specifically, a silicon oxide film is deposited to a thickness of about 30 nm by, eg, CVD, and the cap insulating film 108 is formed.

上記のように水素拡散防止膜１０７を形成することにより、ボイド１０６の内壁は水素拡散防止膜１０７により覆われ、若干の空洞部分が残るとしても殆ど閉塞する。この閉塞部分は、実質的にみれば、水素拡散防止膜１０７の層間絶縁膜１０５上の部分に比して厚く膜材料が堆積した状態とされており、強誘電体膜４５に対する水分・水素の堅固なブロック機能を果たすことになる。そして、キャップ絶縁膜１０８により、仮に前記空洞部分の上部が開口されていたとしても、ボイド１０６の部分は水素拡散防止膜１０７によりほぼ充填された状態で完全に密閉された状態となり、強誘電体膜４５に対する側面方向からの確実な前記ブロック機能が実現する。   By forming the hydrogen diffusion prevention film 107 as described above, the inner wall of the void 106 is covered with the hydrogen diffusion prevention film 107 and is almost closed even if a slight cavity portion remains. The blocking portion is substantially in a state where the film material is deposited thicker than the portion of the hydrogen diffusion preventing film 107 on the interlayer insulating film 105, and moisture / hydrogen is deposited on the ferroelectric film 45. It will perform a solid block function. Even if the upper portion of the hollow portion is opened by the cap insulating film 108, the void 106 portion is completely sealed with the hydrogen diffusion preventing film 107, and the ferroelectric body The reliable blocking function from the side surface direction with respect to the film 45 is realized.

続いて、図７Ｂに示すように、配線１０４の表面の一部を露出させるビア孔１１１を形成する。
詳細には、リソグラフィー及びドライエッチングにより、配線１０４の上方に整合した部位で、キャップ絶縁膜１０８、水素拡散防止膜１０７、及び層間絶縁膜１０５をパターニングする。このパターニングにより、各配線１０４の表面の一部を露出させるビア孔１１１を形成する。Subsequently, as shown in FIG. 7B, a via hole 111 exposing a part of the surface of the wiring 104 is formed.
Specifically, the cap insulating film 108, the hydrogen diffusion preventing film 107, and the interlayer insulating film 105 are patterned at a position aligned above the wiring 104 by lithography and dry etching. By this patterning, a via hole 111 exposing a part of the surface of each wiring 104 is formed.

続いて、図７Ｃに示すように、配線１０４と接続されるプラグ１１３を形成する。
詳細には、ビア孔１１１の各壁面を覆うように、スパッタ法により例えばＴｉＮ膜を膜厚７５ｎｍ程度に堆積して、下地膜（グルー膜）１１２を形成する。そして、ＣＶＤ法によりグルー膜１１２を介してビア孔１１１を埋め込むように、Ｗ，ＴｉＡｌＮ，ＴｉＮ，Ｔｉ，Ａｌ，Ｃｕ，Ｒｕ，ＳＲＯ，Ｉｒの単膜又は積層膜、ここではＷ膜を形成する。その後、キャップ絶縁膜１０８をストッパーとしてＷ膜及びグルー膜１１２を研磨し、ビア孔１１１内をグルー膜１１２を介してＷで埋め込むプラグ１１３を形成する。Subsequently, as shown in FIG. 7C, a plug 113 connected to the wiring 104 is formed.
More specifically, a base film (glue film) 112 is formed by depositing, for example, a TiN film with a film thickness of about 75 nm by sputtering so as to cover each wall surface of the via hole 111. Then, a single film or a laminated film of W, TiAlN, TiN, Ti, Al, Cu, Ru, SRO, and Ir, in this case, a W film is formed so as to fill the via hole 111 through the glue film 112 by the CVD method. . Thereafter, the W film and the glue film 112 are polished using the cap insulating film 108 as a stopper, and a plug 113 that fills the via hole 111 with W via the glue film 112 is formed.

以上により、配線１０４、層間絶縁膜１０５、水素拡散防止膜１０７、キャップ絶縁膜１０８、及びプラグ１１３からなる配線構造１１０が完成する。   Thus, the wiring structure 110 including the wiring 104, the interlayer insulating film 105, the hydrogen diffusion preventing film 107, the cap insulating film 108, and the plug 113 is completed.

以上説明したように、本実施形態によれば、層間絶縁膜５４，１０５から水分や水素を発生させることなく、ボイド５５，１０６が発生しても強誘電体キャパシタ構造３０ａ，３０ｂには悪影響を及ぼすことなく高いキャパシタ特性を確実に保持し、信頼性の高いＦｅＲＡＭが実現する。   As described above, according to the present embodiment, the ferroelectric capacitor structures 30a and 30b are adversely affected even if the voids 55 and 106 are generated without generating moisture or hydrogen from the interlayer insulating films 54 and 105. Thus, a high-reliability FeRAM can be realized that reliably retains high capacitor characteristics without any influence.

なお、本実施形態では、第１の実施形態の装置構成に加えて、多層配線構造を構成する配線構造のうちの少なくとも１層である配線構造１１０に本発明を適用した場合について例示したが、工程数を削減することを考慮して、配線構造１１０のみに本発明を適用するようにしても良い。この場合、強誘電体メモリキャパシタ構造３０ａ，３０ｂの層間絶縁膜５４を例えばＨＤＰ−ＣＶＤ法により、可及的にボイドが発生しない条件で形成し、その後に上述のように配線構造１１０を形成する。この場合でも、層間絶縁膜５４，１０５の双方に本発明を適用した場合に比べれば劣るものの、高いキャパシタ特性を保持し、信頼性の高いＦｅＲＡＭを実現させることができる。   In this embodiment, in addition to the device configuration of the first embodiment, the case where the present invention is applied to the wiring structure 110 which is at least one of the wiring structures constituting the multilayer wiring structure is illustrated. In consideration of reducing the number of processes, the present invention may be applied only to the wiring structure 110. In this case, the interlayer insulating film 54 of the ferroelectric memory capacitor structures 30a and 30b is formed, for example, by HDP-CVD under the condition that voids are not generated as much as possible, and then the wiring structure 110 is formed as described above. . Even in this case, although it is inferior to the case where the present invention is applied to both of the interlayer insulating films 54 and 105, it is possible to realize a FeRAM having high capacitor characteristics and high reliability.

（変形例）
以下、第２の実施形態の変形例について説明する。本例では、第２の実施形態の装置構成に加え、多層配線構造の最上層の配線構造にも本発明を適用する。(Modification)
Hereinafter, modifications of the second embodiment will be described. In this example, in addition to the device configuration of the second embodiment, the present invention is applied to the uppermost wiring structure of the multilayer wiring structure.

図８Ａ〜図８Ｃは、第２の実施形態の変形例によるスタック型のＦｅＲＡＭの製造方法のうち、その主要工程のみを示す概略断面図である。図示の例では、多層配線構造のうちの最上層の配線構造の形成工程を示している。以下では便宜上、最上層の配線構造の下部構造を、単に下部構造２００として示す。   FIG. 8A to FIG. 8C are schematic cross-sectional views showing only the main steps in the manufacturing method of the stack type FeRAM according to the modification of the second embodiment. In the example shown in the drawing, a process of forming the uppermost wiring structure of the multilayer wiring structure is shown. In the following, for convenience, the lower structure of the uppermost wiring structure is simply shown as the lower structure 200.

先ず、図８Ａに示すように、第１の実施形態における図６Ｃの配線６４と同様に、プラグ１１３等と接続される配線１２４（バリアメタル膜と同様のバリアメタル膜１２１、配線層６２と同様の配線層１２２、及びバリアメタル膜６３と同様のバリアメタル膜１２３からなる）を形成する。隣接する配線１０４は近接しているものの、下層の配線構造の配線間距離（例えば、隣接する配線１０４間距離）ほど近接するものではない。   First, as shown in FIG. 8A, like the wiring 64 of FIG. 6C in the first embodiment, the wiring 124 connected to the plug 113 or the like (the same as the barrier metal film 121 and the wiring layer 62 similar to the barrier metal film). And a barrier metal film 123 similar to the barrier metal film 63). Although adjacent wirings 104 are close to each other, they are not as close as the distance between wirings in the lower wiring structure (for example, the distance between adjacent wirings 104).

続いて、配線１２４を覆う層間絶縁膜１２５を形成する。
詳細には、強誘電体膜４５に対して低ダメージとなる材料・条件、例えばＣＶＤ法により含有水分量の抑制されたＰＥ−ＴＥＯＳ−ＳｉＯを用いて、配線１２４を覆うように下部構造２００上に層間絶縁膜１２５を形成する。このとき、各配線１２４が近接して配置されており、強誘電体メモリキャパシタ構造３０ａ，３０ｂの強誘電体膜４５に対して低ダメージとなる材料・条件で層間絶縁膜１２５を形成したため、各配線１２４間の領域を層間絶縁膜１２５で完全に埋め込むことはできず、層間絶縁膜１２５内の当該領域に空隙１２６が発生する。 Subsequently, an interlayer insulating film 125 that covers the wiring 124 is formed.
Specifically, on the lower structure 200 so as to cover the wiring 124 using materials and conditions that cause low damage to the ferroelectric film 45, for example, PE-TEOS-SiO in which the moisture content is suppressed by the CVD method. Then, an interlayer insulating film 125 is formed. At this time, the wirings 124 are arranged close to each other, and the interlayer insulating film 125 is formed with a material and conditions that cause low damage to the ferroelectric film 45 of the ferroelectric memory capacitor structures 30a and 30b. A region between the wirings 124 cannot be completely filled with the interlayer insulating film 125, and a void 126 is generated in the region in the interlayer insulating film 125.

通常、最上層の層間絶縁膜は平坦化しない。そこで本例では、層間絶縁膜１２５を成膜した状態で、空隙１２６の上部が開口する条件（言わば、隣接する配線１２４間の領域を完全に埋め込み空隙を層間絶縁膜１２５内に閉じ込めない条件）で、当該層間絶縁膜１２５を形成する。空隙１２６の開口部を１２６ａと記す。 Usually, the uppermost interlayer insulating film is not planarized. Therefore, in this example, the condition in which the upper portion of the gap 126 is opened in a state where the interlayer insulating film 125 is formed (in other words, a condition in which the region between adjacent wirings 124 is completely buried and the gap is not confined in the interlayer insulating film 125). Thus, the interlayer insulating film 125 is formed. The opening part of the space | gap 126 is described as 126a.

ここで、強誘電体膜４５に対して低ダメージとなる条件、即ちさほど緻密ではなくとも含有水分量を抑制した状態で空隙１２６の発生を容認する条件であれば、例えばＨＤＰ−ＣＶＤ法を用いて層間絶縁膜１２５を形成しても良い。 Here, for example, the HDP-CVD method is used as long as it is a condition that causes low damage to the ferroelectric film 45, that is, a condition that allows the generation of the void 126 in a state where the moisture content is not so dense. Alternatively, the interlayer insulating film 125 may be formed.

ここで、層間絶縁膜１０５を形成した後に、当該層間絶縁膜１０５の脱水処理及び膜質改善を目的として、層間絶縁膜１０５にプラズマ処理を施しても好適である。このプラズマ処理は例えば、Ｎ２ガス種又はＮ２Ｏガス種を用いて、２００℃〜４５０℃の温度で実行する。Here, after the interlayer insulating film 105 is formed, the interlayer insulating film 105 is preferably subjected to plasma treatment for the purpose of dehydrating the interlayer insulating film 105 and improving the film quality. This plasma treatment is performed at a temperature of 200 ° C. to 450 ° C. using N 2 gas species or N 2 O gas species, for example.

続いて、図８Ｂに示すように、層間絶縁膜１２５上に金属酸化膜、例えばＡｌ酸化物（アルミナ）を材料として水素拡散防止膜１２７を形成する。この水素拡散防止膜１０７は、強誘電体膜４５の特性劣化を防止する機能を有している。即ち、水素拡散防止膜１２７により、例えば外界からの水分・水素の強誘電体膜４５への浸入が抑止され、強誘電体膜４５へのダメージが防止される。本実施形態では、更に水素拡散防止膜５３，５６，１０７が形成されており、水素拡散防止膜１２７により、これら水素拡散防止膜５３，５６，１０７と相俟って、水分・水素の強誘電体膜４５への浸入がより確実に抑止され、強誘電体膜４５へのダメージが防止される。水素拡散防止膜１２７としては、アルミナの代わりに、Ａｌ窒化物、Ｔａ酸化物、Ｔａ窒化物、Ｔｉ酸化物、及びＺｒ酸化物から選ばれた一種を用いても良い。   Subsequently, as shown in FIG. 8B, a hydrogen diffusion preventing film 127 is formed on the interlayer insulating film 125 using a metal oxide film, for example, Al oxide (alumina) as a material. This hydrogen diffusion preventing film 107 has a function of preventing the characteristic deterioration of the ferroelectric film 45. That is, the hydrogen diffusion preventing film 127 prevents, for example, moisture and hydrogen from entering the ferroelectric film 45 from the outside, and prevents damage to the ferroelectric film 45. In the present embodiment, hydrogen diffusion preventing films 53, 56, and 107 are further formed. The hydrogen diffusion preventing film 127, together with the hydrogen diffusion preventing films 53, 56, and 107, is a moisture / hydrogen ferroelectric. Intrusion into the body film 45 is more reliably prevented, and damage to the ferroelectric film 45 is prevented. As the hydrogen diffusion preventing film 127, one kind selected from Al nitride, Ta oxide, Ta nitride, Ti oxide, and Zr oxide may be used instead of alumina.

本例では、水素拡散防止膜１２７を、空隙１２６の少なくとも内壁面を完全に覆う条件で層間絶縁膜１２５上に形成する。水素拡散防止膜１２７を上記の条件を満たすように形成することから、その形成法として被覆性に優れたＭＯ−ＣＶＤ法を用いる。ここでは、成長温度２００℃〜５００℃、圧力０．２torr〜１．０torrで、流量１０ｓｌｍでＯ2＋Ｏ3の混合ガスと、流量１００ｓｃｃｍのＴＭＡ（Ａｌ（ＣＨ3）3）とをチャンバー内へ交互に供給しながら、水素拡散防止膜１２７を膜厚５０ｎｍ程度に成長させる（ＡＬＤ（Atomic Layer Deposition）法）。 In this example, the hydrogen diffusion preventing film 127 is formed on the interlayer insulating film 125 under the condition that at least the inner wall surface of the gap 126 is completely covered. Since the hydrogen diffusion prevention film 127 is formed so as to satisfy the above-described conditions, the MO-CVD method having excellent coverage is used as the formation method. Here, a mixed gas of O 2 + O 3 at a growth temperature of 200 ° C. to 500 ° C., a pressure of 0.2 torr to 1.0 torr, and a flow rate of 10 slm, and TMA (Al (CH 3 ) 3 ) at a flow rate of 100 sccm into the chamber. While supplying alternately, the hydrogen diffusion preventing film 127 is grown to a film thickness of about 50 nm ( ALD (Atomic Layer Deposition) method).

ここで、水素拡散防止膜１２７をＭＯ−ＣＶＤ法により単層膜として形成する代わりに、２層膜として形成しても良い。この場合、例えば先ずスパッタ法により水素拡散防止膜１２７の材料膜を膜厚２０ｎｍ程度に堆積し、続いてＭＯ−ＣＶＤ法により水素拡散防止膜１２７の材料膜を膜厚５０ｎｍ程度に堆積する。又は、先ずＭＯ−ＣＶＤ法により水素拡散防止膜１２７の材料膜を膜厚５０ｎｍ程度に堆積し、続いてスパッタ法により水素拡散防止膜１２７の材料膜を膜厚２０ｎｍ程度に堆積する。   Here, the hydrogen diffusion preventing film 127 may be formed as a two-layer film instead of being formed as a single-layer film by the MO-CVD method. In this case, for example, a material film of the hydrogen diffusion preventing film 127 is first deposited to a thickness of about 20 nm by sputtering, and then a material film of the hydrogen diffusion preventing film 127 is deposited to a thickness of about 50 nm by the MO-CVD method. Alternatively, the material film of the hydrogen diffusion preventing film 127 is first deposited to a film thickness of about 50 nm by MO-CVD, and then the material film of the hydrogen diffusion preventing film 127 is deposited to a film thickness of about 20 nm by the sputtering method.

後者の場合では、ＭＯ−ＣＶＤ法の材料膜により空隙１２６の少なくとも内壁が完全に覆われた状態とされ、スパッタ法の材料膜により空隙１２６の開口１２６ａが確実に閉塞される。 In the latter case, at least the inner wall of the gap 126 is completely covered by the MO-CVD method material film, and the opening 126a of the gap 126 is reliably closed by the sputtering method material film.

続いて、図８Ｃに示すように、水素拡散防止膜１２７上を覆うカバー膜１２８を形成する。
詳細には、例えばＰＥ−ＣＶＤ法により、シリコン窒化膜を膜厚３０ｎｍ程度に堆積し、カバー膜１２８を形成する。Subsequently, as shown in FIG. 8C, a cover film 128 covering the hydrogen diffusion preventing film 127 is formed.
Specifically, for example, a silicon nitride film is deposited to a thickness of about 30 nm by PE-CVD, and the cover film 128 is formed.

上記のように水素拡散防止膜１２７を形成することにより、空隙１２６の内壁は水素拡散防止膜１２７により覆われ、若干の空洞部分が残るとしても殆ど閉塞する。この閉塞部分は、実質的にみれば、水素拡散防止膜１２７の層間絶縁膜１２５上の部分に比して厚く膜材料が堆積した状態とされており、強誘電体膜４５に対する水分・水素の堅固なブロック機能を果たすことになる。そして、カバー膜１２８により、仮に前記空洞部分の上部が開口されていたとしても、空隙１２６の部分は水素拡散防止膜１２７によりほぼ充填された状態で完全に密閉された状態となり、強誘電体膜４５に対する側面方向からの確実な前記ブロック機能が実現する。 By forming the hydrogen diffusion preventing film 127 as described above, the inner wall of the void 126 is covered with the hydrogen diffusion preventing film 127 and is almost closed even if a slight cavity portion remains. The blocking portion is substantially in a state where the film material is deposited thicker than the portion of the hydrogen diffusion prevention film 127 on the interlayer insulating film 125, and the moisture / hydrogen with respect to the ferroelectric film 45 is deposited. It will perform a solid block function. Even if the upper part of the hollow portion is opened by the cover film 128, the portion of the void 126 is completely sealed with the hydrogen diffusion preventing film 127, and the ferroelectric film The reliable block function from the side surface direction with respect to 45 is realized.

以上により、配線１２４、層間絶縁膜１２５、水素拡散防止膜１２７、及びカバー膜１２８からなる最上層の配線構造１３０が完成する。   Thus, the uppermost wiring structure 130 including the wiring 124, the interlayer insulating film 125, the hydrogen diffusion preventing film 127, and the cover film 128 is completed.

以上説明したように、本例によれば、層間絶縁膜５４，１０５，１２５から水分や水素を発生させることなく、空隙５５，１０６，１２６が発生しても強誘電体キャパシタ構造３０ａ，３０ｂには悪影響を及ぼすことなく高いキャパシタ特性を確実に保持し、信頼性の高いＦｅＲＡＭが実現する。 As described above, according to the present example, the ferroelectric capacitor structures 30a and 30b can be formed even if the gaps 55, 106, and 126 are generated without generating moisture or hydrogen from the interlayer insulating films 54, 105, and 125. Reliably retains high capacitor characteristics without adverse effects and realizes a highly reliable FeRAM.

なお、本例では、第２の実施形態の装置構成に加えて、多層配線構造を構成する配線構造のうちの最上層の配線構造１３０に本発明を適用した場合について例示したが、工程数を削減することを考慮して、以下のように実行しても良い。
（１）第１の実施形態に加えて、配線構造１３０のみに本発明を適用する。
（２）配線構造１１０，１３０のみに本発明を適用する。
（３）配線構造１３０のみに本発明を適用する。In this example, in addition to the device configuration of the second embodiment, the case where the present invention is applied to the uppermost wiring structure 130 of the wiring structures constituting the multilayer wiring structure is exemplified. In consideration of the reduction, it may be executed as follows.
(1) In addition to the first embodiment, the present invention is applied only to the wiring structure 130.
(2) The present invention is applied only to the wiring structures 110 and 130.
(3) The present invention is applied only to the wiring structure 130.

（１）では、強誘電体メモリキャパシタ構造３０ａ，３０ｂの層間絶縁膜５４上に第１の実施形態に従って水素拡散防止膜５６等を形成した後、配線構造１１０の層間絶縁膜１０５を同様に、ＨＤＰ−ＣＶＤ法により、可及的に空隙が発生しない条件で形成する。しかる後、上述のように配線構造１３０を形成する。 In (1), after forming the hydrogen diffusion prevention film 56 and the like on the interlayer insulating film 54 of the ferroelectric memory capacitor structures 30a and 30b according to the first embodiment, the interlayer insulating film 105 of the wiring structure 110 is similarly formed. By HDP-CVD method, it forms on the conditions which a space | gap does not generate | occur | produce as much as possible. Thereafter, the wiring structure 130 is formed as described above.

（２）では、強誘電体メモリキャパシタ構造３０ａ，３０ｂの層間絶縁膜５４を例えばＨＤＰ−ＣＶＤ法により、可及的に空隙が発生しない条件で形成した後、上述のように配線構造１１０，１３０を順次形成する。 In (2), after the interlayer insulating film 54 of the ferroelectric memory capacitor structures 30a and 30b is formed by, for example, the HDP-CVD method under the condition that no gap is generated as much as possible, the wiring structures 110 and 130 are formed as described above. Are sequentially formed.

（３）では、強誘電体メモリキャパシタ構造３０ａ，３０ｂの層間絶縁膜５４を例えばＨＤＰ−ＣＶＤ法により、可及的に空隙が発生しない条件で形成した後、配線構造１１０の層間絶縁膜１０５を同様に、ＨＤＰ−ＣＶＤ法により、可及的に空隙が発生しない条件で形成する。しかる後、上述のように配線構造１３０を形成する。 In (3), after the interlayer insulating film 54 of the ferroelectric memory capacitor structures 30a and 30b is formed under the condition that no gap is generated as much as possible by, for example, HDP-CVD, the interlayer insulating film 105 of the wiring structure 110 is formed. Similarly, it is formed by HDP-CVD under the condition that voids are not generated as much as possible. Thereafter, the wiring structure 130 is formed as described above.

（１）〜（３）の手法でも、層間絶縁膜５４，１０５，１２５の全てに本発明を適用した場合に比べれば劣るものの、高いキャパシタ特性を保持し、信頼性の高いＦｅＲＡＭを実現させることができる。   Even in the methods (1) to (3), although it is inferior to the case where the present invention is applied to all of the interlayer insulating films 54, 105, and 125, it is possible to realize a FeRAM having high capacitor characteristics and high reliability. Can do.

本発明によれば、（第１及び第２の）層間絶縁膜から水分や水素を発生させることなく、空隙が発生してもキャパシタ構造には悪影響を及ぼすことなく高いキャパシタ特性を確実に保持し、信頼性の高い半導体装置が実現する。 According to the present invention, without generating moisture or hydrogen from the (first and second) interlayer insulating films, even if voids are generated, high capacitor characteristics can be reliably maintained without adversely affecting the capacitor structure. A highly reliable semiconductor device is realized.

Claims (12)

半導体基板と、
前記半導体基板の上方に形成されており、下部電極と上部電極とにより強誘電体を材料とするキャパシタ膜を挟持してなるキャパシタ構造と、
前記キャパシタ構造を覆う第１の層間絶縁膜と、
前記第１の層間絶縁膜上に形成された、前記キャパシタ構造の特性劣化を防止する第１の水素拡散防止膜と
を含み、
前記第１の層間絶縁膜の表層部分には第１の空隙があり、前記第１の空隙の上部が前記第１の層間絶縁膜の表面から開口した状態とされており、
前記第１の水素拡散防止膜は、前記第１の空隙の少なくとも内壁面上に形成され、かつ、前記第１の空隙上に閉塞部分を有することを特徴とする半導体装置。A semiconductor substrate;
A capacitor structure formed above the semiconductor substrate and having a capacitor film made of a ferroelectric material sandwiched between a lower electrode and an upper electrode;
A first interlayer insulating film covering the capacitor structure;
A first hydrogen diffusion prevention film formed on the first interlayer insulating film to prevent deterioration of characteristics of the capacitor structure;
Wherein the surface layer portion of the first interlayer insulating film has a first gap, which is a state in which an upper portion of the first gap is open from the surface of the first interlayer insulating film,
The first hydrogen barrier film may be formed on at least an inner wall surface of said first gap, and wherein a has an occlusion on the first gap. 前記第１の水素拡散防止膜は、Ａｌ酸化物，Ａｌ窒化物，Ｔａ酸化物，Ｔａ窒化物，Ｔｉ酸化物，及びＺｒ酸化物よりなる群から選ばれた１種を材料として形成されていることを特徴とする請求項１に記載の半導体装置。  The first hydrogen diffusion preventing film is formed by using one selected from the group consisting of Al oxide, Al nitride, Ta oxide, Ta nitride, Ti oxide, and Zr oxide. The semiconductor device according to claim 1. 前記第１の層間絶縁膜は、その上面が平坦化されており、
当該平坦化により前記第１の空隙の上部が前記第１の層間絶縁膜の表面から開口した状態とされていることを特徴とする請求項１に記載の半導体装置。The upper surface of the first interlayer insulating film is flattened,
2. The semiconductor device according to claim 1, wherein an upper portion of the first gap is opened from a surface of the first interlayer insulating film by the planarization. 前記第１の層間絶縁膜は、含有水分量の抑制されたＰＥ−ＴＥＯＳ−ＳｉＯからなることを特徴とする請求項１に記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the first interlayer insulating film is made of PE-TEOS-SiO in which a moisture content is suppressed. 前記第１の水素拡散防止膜上に形成されたキャップ絶縁膜を更に含むことを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, further comprising a cap insulating film formed on the first hydrogen diffusion preventing film. 前記第１の水素拡散防止膜の上方に形成された配線と、
前記配線を覆う第２の層間絶縁膜と、
前記第２の層間絶縁膜上に形成された、前記キャパシタ構造の特性劣化を防止する第２の水素拡散防止膜と
を更に含み、
前記第２の層間絶縁膜の表層部分には第２の空隙が発生し、前記第２の空隙の上部が前記第２の層間絶縁膜の表面から開口した状態とされており、
前記第２の水素拡散防止膜は、前記第２の空隙の少なくとも内壁面を覆うように形成されていることを特徴とする請求項１に記載の半導体装置。A wiring formed above the first hydrogen diffusion prevention film;
A second interlayer insulating film covering the wiring;
A second hydrogen diffusion preventing film formed on the second interlayer insulating film to prevent deterioration of characteristics of the capacitor structure;
Wherein the surface layer portion of the second interlayer insulating film being a state second void is generated, in which the upper portion of the second gap is open from the surface of the second interlayer insulating film,
The semiconductor device according to claim 1, wherein the second hydrogen diffusion prevention film is formed so as to cover at least an inner wall surface of the second gap . 半導体基板の上方に、下部電極と上部電極とにより強誘電体を材料とするキャパシタ膜を挟持してなるキャパシタ構造を形成する工程と、
前記キャパシタ構造を覆うように第１の層間絶縁膜を形成する工程と、
前記第１の層間絶縁膜の表層部分に発生した第１の空隙の上部を、前記第１の層間絶縁膜の表面から開口させる工程と、
前記第１の層間絶縁膜上に、前記第１の空隙の少なくとも内壁面を覆いつつ、前記第１の空隙を閉塞するように、前記キャパシタ構造の特性劣化を防止する第１の水素拡散防止膜を形成する工程と
を含むことを特徴とする半導体装置の製造方法。Forming a capacitor structure in which a capacitor film made of a ferroelectric material is sandwiched between a lower electrode and an upper electrode above a semiconductor substrate;
Forming a first interlayer insulating film so as to cover the capacitor structure;
Opening an upper portion of the first gap generated in a surface layer portion of the first interlayer insulating film from a surface of the first interlayer insulating film;
On the first interlayer insulating film, wherein while covering at least an inner wall surface of the first gap, so as to close said first gap, the first hydrogen diffusion preventing film for preventing the characteristic degradation of the capacitor structure Forming a semiconductor device. A method for manufacturing a semiconductor device, comprising: 前記第１の水素拡散防止膜を、Ａｌ酸化物，Ａｌ窒化物，Ｔａ酸化物，Ｔａ窒化物，Ｔｉ酸化物，及びＺｒ酸化物よりなる群から選ばれた１種を材料として形成することを特徴とする請求項７に記載の半導体装置の製造方法。  Forming the first hydrogen diffusion preventive film using as a material one selected from the group consisting of Al oxide, Al nitride, Ta oxide, Ta nitride, Ti oxide, and Zr oxide; 8. The method of manufacturing a semiconductor device according to claim 7, wherein 前記第１の水素拡散防止膜を、ＭＯ−ＣＶＤ法により形成することを特徴とする請求項８に記載の半導体装置の製造方法。  9. The method of manufacturing a semiconductor device according to claim 8, wherein the first hydrogen diffusion preventing film is formed by an MO-CVD method. ＭＯ−ＣＶＤ法により下層を成膜する工程と、スパッタ法により上層を成膜する工程とを任意の順序で行って、前記第１の水素拡散防止膜を形成することを特徴とする請求項８に記載の半導体装置の製造方法。  9. The first hydrogen diffusion prevention film is formed by performing a step of forming a lower layer by an MO-CVD method and a step of forming an upper layer by a sputtering method in an arbitrary order. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. 前記第１の空隙の上部を前記第１の層間絶縁膜の表面から開口させる工程では、前記第１の層間絶縁膜の上面を平坦化し、当該平坦化により前記第１の空隙の上部が前記第１の層間絶縁膜の表面から開口した状態とすることを特徴とする請求項７に記載の半導体装置の製造方法。In the step of opening the upper portion of the first gap from the surface of the first interlayer insulating film, the upper surface of the first interlayer insulating film is flattened, and the upper portion of the first gap is flattened by the flattening. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is opened from the surface of the one interlayer insulating film. 前記第１の水素拡散防止膜の上方に配線を形成する工程と、
前記配線を覆うように、第２の層間絶縁膜を形成する工程と、
前記第２の層間絶縁膜の表層部分に発生した第２の空隙の上部を、前記第２の層間絶縁膜の表面から開口させる工程と、
前記第２の層間絶縁膜上に、前記第２の空隙の少なくとも内壁面を覆うように、前記キャパシタ構造の特性劣化を防止する第２の水素拡散防止膜を形成する工程と
を更に含むことを特徴とする請求項７に記載の半導体装置の製造方法。Forming a wiring above the first hydrogen diffusion preventing film;
Forming a second interlayer insulating film so as to cover the wiring;
Opening an upper portion of a second gap generated in a surface layer portion of the second interlayer insulating film from a surface of the second interlayer insulating film;
Forming a second hydrogen diffusion preventive film for preventing characteristic deterioration of the capacitor structure so as to cover at least the inner wall surface of the second gap on the second interlayer insulating film. 8. The method of manufacturing a semiconductor device according to claim 7, wherein
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