JP4967904B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4967904B2 JP4967904B2 JP2007199394A JP2007199394A JP4967904B2 JP 4967904 B2 JP4967904 B2 JP 4967904B2 JP 2007199394 A JP2007199394 A JP 2007199394A JP 2007199394 A JP2007199394 A JP 2007199394A JP 4967904 B2 JP4967904 B2 JP 4967904B2
- Authority
- JP
- Japan
- Prior art keywords
- alignment marker
- film
- semiconductor device
- metal film
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 91
- 239000003550 marker Substances 0.000 claims description 83
- 229910052751 metal Inorganic materials 0.000 claims description 59
- 239000002184 metal Substances 0.000 claims description 59
- 239000011229 interlayer Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 31
- 239000010410 layer Substances 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 238000002161 passivation Methods 0.000 claims description 20
- 238000001514 detection method Methods 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 34
- 238000004519 manufacturing process Methods 0.000 description 15
- 229910004298 SiO 2 Inorganic materials 0.000 description 14
- 238000005530 etching Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1は、実施の形態1にかかる半導体装置のアライメントマーカー部の構造について示す平面図である。図1に示すように、実施の形態1にかかる半導体装置のアライメントマーカー部は、金属膜6の全面に開口部5が設けられている。金属膜6の下には、金属膜6と同様の形状をしたポリシリコン膜3が設けられている。ここで、開口部5間の距離は、等しいのが好ましい。また、金属膜6端部から最も近傍にある開口部5と、金属膜6端部との距離は、開口部5間の距離と等しいのが好ましい。なお、図1においては、金属膜6は、+の平面形状をしているが、これに限るものではない。
図11は、実施の形態2にかかる半導体装置のアライメントマーカー部の構造を示す平面図である。図11に示すように、実施の形態2にかかる半導体装置のアライメントマーカー部は、断面の構造が実施の形態1にかかる半導体装置のアライメントマーカー部と同様であり、平面形状が台形状である。具体的には、半導体基板10の回路領域11が設けられていない四隅のうち三カ所に、台形状を二つ並べた二重線のような第1のパターン12が設けられており、残りの一カ所に台形状を三つ並べた三重線のような第2のパターン13が設けられている。
2 SiO2層
3 ポリシリコン膜
4 層間絶縁膜
5 開口部
6 金属膜
7 パッシベーション膜
Claims (2)
- 半導体基板上にアライメントマーカー部の設けられた半導体装置において、
前記アライメントマーカー部は、
前記半導体基板の表面に設けられた層間絶縁膜と、
前記層間絶縁膜に設けられた複数の開口部と、
前記層間絶縁膜と、前記開口部と、の表面に選択的に設けられた位置検出用の金属膜と、
前記層間絶縁膜と、前記金属膜と、の表面に設けられたパッシベーション膜と、
前記半導体基板の表面層に設けられた、ポリシリコン層からなる絶縁層と、
前記絶縁層と、前記層間絶縁膜と、の間に設けられた配線層と、
を備え、
前記開口部は、前記層間絶縁膜が選択的に除去されることにより設けられ前記配線層に達し、前記層間絶縁膜に対して所定の高さを有し、
前記金属膜は、前記開口部の内部に埋め込まれるように複数の前記開口部にわたって設けられ前記開口部を介して前記配線層と接し、かつ、前記開口部の内部に埋め込まれた部分が窪んで連続的に凹凸のある形状となっており、
前記半導体基板上に少なくとも二つ以上の前記アライメントマーカー部が設けられたことを特徴とする半導体装置。 - 前記開口部の内部に埋め込まれて窪んだ部分が前記金属膜の全面にわたって複数設けられ、前記金属膜の全面が連続的な凹凸のある形状となっていることを特徴とする請求項1に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007199394A JP4967904B2 (ja) | 2007-07-31 | 2007-07-31 | 半導体装置 |
US12/132,074 US8183700B2 (en) | 2007-07-31 | 2008-06-03 | Semiconductor device having alignment mark and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007199394A JP4967904B2 (ja) | 2007-07-31 | 2007-07-31 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011259548A Division JP5382096B2 (ja) | 2011-11-28 | 2011-11-28 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009038115A JP2009038115A (ja) | 2009-02-19 |
JP4967904B2 true JP4967904B2 (ja) | 2012-07-04 |
Family
ID=40337360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007199394A Expired - Fee Related JP4967904B2 (ja) | 2007-07-31 | 2007-07-31 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8183700B2 (ja) |
JP (1) | JP4967904B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9245851B2 (en) | 2013-07-18 | 2016-01-26 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8164753B2 (en) * | 2009-06-05 | 2012-04-24 | Nanya Technology Corp. | Alignment mark arrangement and alignment mark structure |
US9673243B2 (en) * | 2009-09-17 | 2017-06-06 | Sionyx, Llc | Photosensitive imaging devices and associated methods |
US8901715B1 (en) | 2013-07-05 | 2014-12-02 | Infineon Technologies Ag | Method for manufacturing a marked single-crystalline substrate and semiconductor device with marking |
JP6378117B2 (ja) * | 2015-03-13 | 2018-08-22 | 東芝メモリ株式会社 | アライメントマークの形成方法および半導体装置 |
CN109817605A (zh) * | 2018-05-29 | 2019-05-28 | 苏州能讯高能半导体有限公司 | 半导体器件及其制备方法 |
JP7321792B2 (ja) * | 2019-06-26 | 2023-08-07 | 株式会社ジャパンディスプレイ | 異方性導電膜及び表示装置 |
TWI763153B (zh) * | 2020-11-27 | 2022-05-01 | 新唐科技股份有限公司 | 對準標記結構 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2995749B2 (ja) * | 1989-05-30 | 1999-12-27 | ソニー株式会社 | 半導体装置 |
KR950002171B1 (ko) * | 1990-03-12 | 1995-03-14 | 후지쓰 가부시끼가이샤 | 얼라인먼트마크및반도체장치 |
JPH0629405A (ja) * | 1992-07-10 | 1994-02-04 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2590711B2 (ja) | 1993-11-26 | 1997-03-12 | 日本電気株式会社 | 半導体装置の製造方法 |
JP3081994B2 (ja) * | 1997-10-22 | 2000-08-28 | セイコーインスツルメンツ株式会社 | 半導体装置 |
JP3019822B2 (ja) | 1997-10-31 | 2000-03-13 | 日本電気株式会社 | 半導体集積回路及びその製造方法 |
JP3159168B2 (ja) * | 1998-05-15 | 2001-04-23 | 日本電気株式会社 | 半導体装置とその製造方法 |
JP4352579B2 (ja) | 2000-05-16 | 2009-10-28 | 沖電気工業株式会社 | 半導体チップ及びその製造方法 |
JP4504515B2 (ja) * | 2000-06-13 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP4487481B2 (ja) * | 2002-01-16 | 2010-06-23 | 富士電機システムズ株式会社 | 半導体装置およびその製造方法 |
JP2004079693A (ja) * | 2002-08-14 | 2004-03-11 | Sony Corp | 半導体装置及びその製造方法 |
JP2005236187A (ja) | 2004-02-23 | 2005-09-02 | Seiko Epson Corp | 半導体装置の製造方法、電子機器 |
-
2007
- 2007-07-31 JP JP2007199394A patent/JP4967904B2/ja not_active Expired - Fee Related
-
2008
- 2008-06-03 US US12/132,074 patent/US8183700B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9245851B2 (en) | 2013-07-18 | 2016-01-26 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US8183700B2 (en) | 2012-05-22 |
JP2009038115A (ja) | 2009-02-19 |
US20090032979A1 (en) | 2009-02-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4967904B2 (ja) | 半導体装置 | |
US10504846B2 (en) | Semiconductor device | |
US9245851B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
US7821638B2 (en) | Alignment mark | |
US8274166B2 (en) | Semiconductor device and method of manufacturing the same | |
US9620431B2 (en) | Chip package including recess in side edge | |
US20060186405A1 (en) | Semiconductor device and manufacturing process therefor | |
JP4816601B2 (ja) | 固体撮像素子及び固体撮像素子の製造方法 | |
US6344697B2 (en) | Semiconductor device comprising layered positional detection marks and manufacturing method thereof | |
JP5148825B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US8593000B2 (en) | Semiconductor device and manufacturing method thereof | |
US9059182B2 (en) | Method for producing bonding connection of semiconductor device | |
JP4412922B2 (ja) | 半導体装置 | |
JP5382096B2 (ja) | 半導体装置およびその製造方法 | |
JP2003203852A (ja) | アライメントマーク構造およびその製造方法、アライメントマーク検出方法 | |
US11367712B2 (en) | Semiconductor device and manufacturing method thereof | |
US9711469B2 (en) | Semiconductor structure having recess and manufacturing method thereof | |
JP2008218624A (ja) | 認識マークおよび半導体装置 | |
JP6268781B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US20100270672A1 (en) | Semiconductor device | |
KR101060699B1 (ko) | 웨이퍼 정렬 장치 및 그 방법 | |
JP2000012432A (ja) | アライメントマークの周辺構造 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20091112 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20091112 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20091112 |
|
A625 | Written request for application examination (by other person) |
Free format text: JAPANESE INTERMEDIATE CODE: A625 Effective date: 20100615 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20110422 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110914 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110927 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111128 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111220 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120220 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120306 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120319 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150413 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4967904 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |