JP4864307B2 - エアーギャップを選択的に形成する方法及び当該方法により得られる装置 - Google Patents
エアーギャップを選択的に形成する方法及び当該方法により得られる装置 Download PDFInfo
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- JP4864307B2 JP4864307B2 JP2004284815A JP2004284815A JP4864307B2 JP 4864307 B2 JP4864307 B2 JP 4864307B2 JP 2004284815 A JP2004284815 A JP 2004284815A JP 2004284815 A JP2004284815 A JP 2004284815A JP 4864307 B2 JP4864307 B2 JP 4864307B2
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- dielectric material
- air gap
- etching
- manufacturing
- dielectric
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Description
(i)等方性エッチング(MEMSに応用する):これは、SiO2犠牲層を溶解するためHFを使用することが含まれる。ここで、他の非反応性フィルム(例えばSiC)をエッチング停止材として使用する。その後、エッチングソースを非共形のCVD SiO2層によりシールする。
(ii)非等方性エッチング:これは、非等方性ドライエッチングにより材料を除去することが含まれる。このとき、専用のマスクを有すること、その後のドライエッチング及びストリップオペレーションをさらに行うことが必要である。その後、共形のCVD SiO2は、エアーギャップが形成されるラインの上面に積層され、共形CVD SiO2に続いて非共形CVD SiO2が積層される。
上記半導体装置は積層体を含み、
該積層体は、
第1誘電体材料からなる第1誘電体層と、
第2誘電体材料からなる第2誘電体層とを少なくとも有する方法を開示している。上記第2誘電体層は上記第1誘電体層上に位置する。上記第1誘電体層及び任意ではあるが上記第2誘電体層は、第1エッチング物質に対して耐性を有する。
第1エッチング化合物に対して耐性を有する第1誘電体材料(1)と、
上記第1誘電体材料(1)上の第2誘電体材料(2)と、を有し、
当該方法は、
第2エッチング化合物により、上記積層体中に少なくとも1つのホールをエッチング形成する工程と、
少なくとも局所的に、上記第1誘電体材料(1)中の上記ホールの側壁を、化学的及び/又は機械的に、上記第1エッチング化合物によりエッチング可能な誘電体材料(4)に変換する変換工程と、
少なくとも、変換された誘電体材料(4)上にバリアー層(5)を積層する工程と、
上記ホールに電気伝導性材料を析出させる工程と、
上記変換された誘電体材料(4)を露出するため、上記電気伝導性材料の過剰堆積部分を取り除く工程と、
上記変換された誘電体材料(4)を取り除くため、上記第1エッチング化合物を上記の変換された誘電体材料(4)に接触させる工程と、を含み、
上記の積層体に少なくとも1つのホールをエッチング形成する工程と、上記変換工程とが同時に行われることを特徴とする方法を開示している。
上記積層体は、第1エッチング化合物に対して耐性を有する第1誘電体材料と、上記第1誘電体材料上に第2誘電体材料とを含む方法において、
上記方法は、
第2エッチング化合物で、上記積層体に少なくとも1つのホールをエッチング形成する工程と、
少なくとも局所的に、上記第1誘電体材料(1)中の上記ホールの側壁を、化学的及び/又は機械的に誘電体材料(4)に変換して、上記誘電体材料(4)を上記第1エッチング化合物によりエッチング可能とする工程と、
上記ホール内に電気伝導性材料を析出させる工程と、
上記変換された誘電体材料を露出するために、上記伝導性材料の過剰堆積部分を取り除く工程と、
上記変換された誘電体材料を取り除くため、上記第1エッチング化合物を、上記変換された誘電体材料に接触させる工程とを備えることを特徴とする方法を開示している。
標準的なプロセス工程を使用して、誘電体(1)として超低誘電率材料(ULK)を、また誘電体(2)としてSiO2を積層させることにより図10に示した構造を作製した。標準的なレジスト及び標準的な193nm光学リソグラフィーによりレジストパターンを作製した。ホールを形成するために、標準的なプラズマエッチング系を使用して、レジストパターンを誘電性積層体に写し取る。プラズマは、アルゴン、酸素、及び過フッ化炭化水素分子を含む。酸素及び過フッ化炭化水素分子を使用して、標準的なアッシュ系のプラズマにより灰化される。ホール内に及び当該領域上にTaN/Taバリアー層(5)及び銅(6)を積層し、その後標準的な系により当該領域上を取り除いた。その後、変換された誘電体を、希釈されたフッ酸により取り除いた。この希釈されたフッ酸により、ワイヤに近接するエアーギャップ(7)を作製する。
全プロセスを図7に示す。最初に、50/200/50/275/13nmのSi3N4/SiO2/SiC/SiOC:H/SiO2からなるスタックを、プラズマ気相成長法(PE−CVD)により、Si(100)ウエハ上に形成した。193nmの波長の光学リソグラフィーによりパターニングを行った。低圧においてはCF4/CH2F2/Ar/O2プラズマを、高圧においてはO2/CF4プラズマをそれぞれ使用して、Lam Exelan2300TMチャンバー内で、ドライエッチ及びレジスト灰化を行った。ドライエッチング及びレジスト灰化の両プロセスを注意深く制御して、SiOC:Hトレンチの側壁において、欠陥のあるSiOXフィルムとした(図7(a))。その後、15/10nmTaTa(N)の拡散層及び100nmのCuシード層を、イオン化物理的気相成長法(i−CVD)により形成した。図7(b)に示すように、銅電解メッキによりトレンチを充填し、化学的機械的研磨法(CMP)により、溢れた金属を取り除いた。SiOC:Hと対比して、HFは選択的にSiOXを溶解する。これにより、図7(c)に示すように、側壁にエアーギャップが形成される。HFの浸漬時間を制御して、SiCO:H層、Ta/Ta(N)拡散バリアー層及び銅伝導体への攻撃が最小となるようにSiOX層を取り除く。その後、図7(d)に示すように、50/330/500nmSiC/SiO2/Si3N4不動態層を上面に積層させた。
エアーギャップを有するか若しくは有さないプロセスサンプル(エアーギャップの形成に関しては上記具体例に記載されている)をウエハレベルで完全な電気的評価を行った。ウエハD07、D09、D10、D11、D18、D19、D20、D21、D22及びD23を加工してエアーギャップを形成した。全てのサンプルは、様々な配線形状及び様々なインターラインスペーシングを有する構造から構成される。より詳細に言えば、ウエハ上の様々な構造体間のインターラインスペーシングは、0.15nm、0.20nm、若しくは0.25nmのいずれかであった。ウエハD10を除いて、加工処理後、ウエハの全ての構造体上に不動態層を積層させた。ウエハD08は、エアーギャップが形成されておらず、参照サンプルとして用いた。様々なウエハの主な特徴を表1に示した。
表1 加工処理されたサンプルの特徴
表2:エアーギャップを有するウエハに対する平均RCディレイ
表3:エアーギャップを有するウエハと有さないウエハに対する平均RCディレイ
**:352個のダイスのデータの平均(8つのウエハ)
表4:エアーギャップを有するウエハと有さないウエハに対する平均RCディレイ
**:352個のダイスのデータの平均(8つのウエハ)
図10は、L/Sのインターラインスペーシングが150/150nm、200/200nm及び250/250nmの、Cu/SiOC:H/エアーギャップ/不動態構造の断面SEM図である。いくつかのイメージを分析した結果、エアーギャップの大きさは25〜35nmの厚さ、約275nmの高さを有する。これらの大きさは、不動態化されていないエアーギャップ構造より小さい。このエアーギャップ構造は、不動態層の成長が、エアーキャビティを貫通しないことを意味する。一般的に、エアーギャップの幅は、SiCO:Hの酸化後のSiOXフィルムの厚さに対応する。RIE(エッチング)プロセスの間これを調整してもよい。このRIE(エッチング)プロセスは、誘電体材料にホールをエッチング形成する為に使用される。上記具体例は、本発明に係るいくつかの方法及び材料を開示している。本発明に係る製造方法及び製造装置を容易に修正することができ、この製造方法と材料を容易に変更することができる。そのような修正は、当業者であれば、本明細書に記載された発明の開示及び実施例を考察することにより、明らかである。従って、本発明は、本明細書に記載された特定の実施の形態及び実施例に限定することを意図するものではなく、添付の特許請求の範囲に具体化された発明の真の技術的範囲及び思想から想到するあらゆる修正及び変更をカバーする。全てのパテント、応用例及び本発明に引用された他の引用文献を全体的に引用して援用する。
Claims (22)
- 半導体装置の積層体にエアーギャップ(7)を形成するための方法であって、
当該積層体は、第1エッチング化合物に対して耐性を有する第1誘電体材料(1)と、上記第1誘電体材料(1)上の第2誘電体材料(2)と、を有し、
当該方法は、
第2エッチング化合物により、上記積層体に少なくとも1つのホールをエッチング形成する工程と、
少なくとも局所的に、上記第1誘電体材料(1)中の上記ホールの側壁を、化学的及び/又は機械的に、上記第1エッチング化合物によりエッチング可能な誘電体材料(4)に変換する変換工程と、
少なくとも、変換された誘電体材料(4)上にバリアー層(5)を積層する工程と、
上記ホールに電気伝導性材料を析出させる工程と、
上記変換された誘電体材料(4)を露出するため、上記電気伝導性材料の過剰堆積部分を取り除く工程と、
上記変換された誘電体材料(4)を取り除くため、上記第1エッチング化合物を上記の変換された誘電体材料(4)に接触させる工程と、を含み、
上記の積層体に少なくとも1つのホールをエッチング形成する工程と、上記変換工程とが同時に行われることを特徴とするエアーギャップ作製方法。 - 上記第2誘電体材料(2)は、上記第1エッチング化合物に対して耐性を有することを特徴とする請求項1記載のエアーギャップ作製方法。
- 上記積層体が、上記第2誘電体材料(2)の上面にハードマスク若しくは金属ハードマスクをさらに備えることを特徴とする請求項1記載のエアーギャップ作製方法。
- 上記第2誘電体材料(2)がハードマスク若しくは金属ハードマスクにより置き換えられていることを特徴とする請求項1〜3のいずれかに記載のエアーギャップ作製方法。
- 上記第1エッチング化合物が、フッ酸(HF)を含むことを特徴とする請求項1〜4のいずれかに記載のエアーギャップ作製方法。
- 上記の少なくとも1つのホールをエッチング形成する工程が、酸化プラズマにより行われることを特徴とする請求項1〜5のいずれかに記載のエアーギャップ作製方法。
- 上記の少なくとも1つのホールをエッチング形成する工程が、N2/H2含有プラズマにより行われることを特徴とする請求項1〜5のいずれかに記載のエアーギャップ作製方法。
- 上記酸化プラズマが、酸素を含有することを特徴とする請求項6記載のエアーギャップ作製方法。
- 上記酸化プラズマが、さらにハイドロフルオロカーボン化合物及び/又はフルオロカーボン化合物を含むことを特徴とする請求項6記載のエアーギャップ作製方法。
- 上記第1誘電体材料(1)がSiCO:H材料であることを特徴とする請求項1〜9のいずれかに記載のエアーギャップ製造方法。
- 上記第1誘電体材料(1)が、上記第2誘電体材料(2)より多孔性であることを特徴とする請求項1〜10のいずれかに記載のエアーギャップ作製方法。
- 上記電気伝導性材料が、金属、カーボンナノチューブ及び伝導性ポリマーからなる群から選択される少なくとも1つを含んでなることを特徴とする請求項1〜11のいずれかに記載のエアーギャップ作製方法。
- 上記電気伝導性材料が銅であることを特徴とする請求項12記載のエアーギャップ作製方法。
- 上記誘電体材料(4)が、1μm以下の膜厚を有することを特徴とする請求項1〜13のいずれかに記載のエアーギャップ作製方法。
- 上記誘電体材料(4)が、500nm以下の膜厚を有することを特徴とする請求項14に記載のエアーギャップ作製方法。
- 上記誘電体材料(4)が、100nm以下の膜厚を有することを特徴とする請求項15に記載のエアーギャップ作製方法。
- 上記誘電体材料(4)が、50nm以下の膜厚を有することを特徴とする請求項16に記載のエアーギャップ作製方法。
- 請求項1〜17のいずれかに記載された方法を含む、エアーギャップを備える半導体装置の作製方法。
- 上記変換工程後にバリアー層を積層する工程をさらに含むことを特徴とする請求項18記載のエアーギャップを有する半導体装置の作製方法。
- 上記接触工程の後に、上記積層体上にキャップ層を積層させる工程をさらに含むことを特徴とする請求項18又は19に記載のエアーギャップを有する半導体装置の作製方法。
- 上記キャップ層がSiC層であることを特徴とする請求項20記載のエアーギャップを有する半導体装置の作製方法。
- 請求項18〜21のいずれかに係る半導体装置の作製方法により得ることができる装置。
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JP2005123607A (ja) | 2005-05-12 |
ATE505813T1 (de) | 2011-04-15 |
US7319274B2 (en) | 2008-01-15 |
US20060177990A1 (en) | 2006-08-10 |
DE602004032198D1 (de) | 2011-05-26 |
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