JP4856014B2 - Circuit module and manufacturing method thereof - Google Patents

Circuit module and manufacturing method thereof Download PDF

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JP4856014B2
JP4856014B2 JP2007170190A JP2007170190A JP4856014B2 JP 4856014 B2 JP4856014 B2 JP 4856014B2 JP 2007170190 A JP2007170190 A JP 2007170190A JP 2007170190 A JP2007170190 A JP 2007170190A JP 4856014 B2 JP4856014 B2 JP 4856014B2
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lid
carrier substrate
ceramic
solder
ceramic carrier
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JP2009010170A (en
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洋一 北村
実 橋本
達也 金子
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2007170190A priority Critical patent/JP4856014B2/en
Priority to US12/007,972 priority patent/US7738263B2/en
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Priority to US12/591,240 priority patent/US8240037B2/en
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
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    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
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    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2924/097Glass-ceramics, e.g. devitrified glass
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
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Description

本発明は、電子部品を内蔵する回路モジュールとその製造方法に関し、特に、キャビティ内への異物の混入が防止された回路モジュールとその製造方法に関するものである。   The present invention relates to a circuit module incorporating an electronic component and a manufacturing method thereof, and more particularly to a circuit module in which foreign matter is prevented from entering a cavity and a manufacturing method thereof.

通信機器、衛星、レーダー等に使われる高周波回路モジュールは、信頼性が高く、長寿命であることが不可欠である。そのため、高周波電子部品を搭載した回路部は、キャビティを備えたキャップで密閉された構造となっている。
また、高周波回路モジュールは、高周波電子部品から外部への電磁波の漏洩、ならびに、外部から高周波電子部品への電磁波の干渉を遮断するため、キャップに、金属もしくは導電性表面を有する誘電体が用いられている。それと、高周波回路モジュールは、各回路部間の電磁波の干渉を遮断する必要があるものでは、キャビティが隔壁により小部屋に分割され、これらの分割された各キャビティに各回路部が収納された構造となっている。
例えば、ハーメチックシールされたピン端子を備えた金属の平板上の容器本体と、間仕切りにより形成された複数のキャビティを設けた金属製のキャップ(この後、リッドと記す)とで、高周波回路部を気密封止した高周波回路モジュールがある(例えば、特許文献1参照)。
High-frequency circuit modules used for communication equipment, satellites, radars, etc. must have high reliability and long life. Therefore, the circuit portion on which the high-frequency electronic component is mounted has a structure sealed with a cap having a cavity.
In addition, in a high frequency circuit module, a metal or a dielectric having a conductive surface is used for a cap in order to block leakage of electromagnetic waves from high frequency electronic components to the outside and interference of electromagnetic waves from outside to high frequency electronic components. ing. In addition, the high-frequency circuit module has a structure in which the cavity is divided into small rooms by partition walls, and each circuit part is accommodated in each of these divided cavities in the case where it is necessary to block the interference of electromagnetic waves between each circuit part. It has become.
For example, a high-frequency circuit unit is composed of a container body on a metal flat plate having pin terminals hermetically sealed and a metal cap (hereinafter referred to as a lid) provided with a plurality of cavities formed by partitions. There is a hermetically sealed high-frequency circuit module (see, for example, Patent Document 1).

上記、高周波回路モジュールでは、平板上の容器本体が金属であるため、信号等を取り出す端子の絶縁にハーメチックシールが用いられている。しかし、最近は、平板上の容器本体は、金属に替えて誘電体基板が用いられ、容器本体の製造工程の簡略化とコスト低減が図られている。
例えば、誘電体基板の平板上の容器本体に、電子部品を搭載するための配線パターンが設けられたセラミック基板を用いた気密封止型半導体装置がある(例えば、特許文献2参照)。
そして、平板上の容器本体がセラミック基板等の誘電体基板であると、リッドの接合に、金属の容器本体で用いられた溶接を使用することができないため、平板上の容器本体へのリッドの接合には、はんだ付けや接着が用いられている。
In the above high-frequency circuit module, since the container body on the flat plate is made of metal, a hermetic seal is used to insulate a terminal for taking out a signal or the like. However, recently, a dielectric substrate is used instead of metal for the container body on the flat plate, and the manufacturing process of the container body is simplified and the cost is reduced.
For example, there is a hermetically sealed semiconductor device using a ceramic substrate provided with a wiring pattern for mounting an electronic component on a container body on a flat plate of a dielectric substrate (for example, see Patent Document 2).
If the container body on the flat plate is a dielectric substrate such as a ceramic substrate, the welding used in the metal container body cannot be used for joining the lid. Soldering or adhesion is used for joining.

特告平07−073123号公報(第2頁、第1図)No. 07-073123 (2nd page, Fig. 1) 特開2001−68576号公報(第3頁、第1図)JP 2001-68576 A (page 3, FIG. 1)

しかし、はんだ付けによるセラミック基板の平板上の容器本体とリッドとの接合では、はんだペーストが用いられので、はんだペースト中のフラックスの残留に起因するボイドが、接合時の加熱により破裂して、はんだボールが、電子部品を収納するキャビティ内空間に飛散する。また、はんだ層に残留するフラックスも電子部品を収納するキャビティ内空間に飛散する。回路モジュールにおける、キャビティ内空間へのはんだボールやフラックスの飛散は、封止された電子部品の動作や特性に影響を与えるとの問題があった。
また、接着によるセラミック基板の平板上の容器本体とリッドとの接合には、導電性樹脂が用いられる。この場合でも、導電性樹脂の塗布に起因して導電性樹脂中に生じたボイドが、平板上の容器本体とリッドとの接合時に破裂して、導電性樹脂粒子が、電子部品を収納するキャビティ内空間に飛散し、封止された電子部品の動作や特性に影響を与えるとの問題が考えられる。
However, since the solder paste is used to join the container body on the flat plate of the ceramic substrate and the lid by soldering, voids resulting from residual flux in the solder paste burst due to heating during joining, and solder Balls scatter into the space in the cavity that houses the electronic components. In addition, the flux remaining in the solder layer also scatters in the cavity space that houses the electronic component. In the circuit module, the scattering of solder balls and flux into the space in the cavity has a problem of affecting the operation and characteristics of the sealed electronic component.
A conductive resin is used for bonding the container body and the lid on the flat plate of the ceramic substrate by bonding. Even in this case, the void generated in the conductive resin due to the application of the conductive resin is ruptured when the container body on the flat plate and the lid are joined, and the conductive resin particles are contained in the cavity for storing the electronic components. There is a problem that the operation and characteristics of the sealed electronic component are affected by scattering into the inner space.

この発明は、上述のような課題を解決するためになされたもので、その目的は、はんだ付けや接着により、セラミック基板等の誘電体基板で形成された平板上の容器本体とリッドとが接合され、且つ容器内に密閉される電子部品の動作や特性に、はんだ付けや接着に起因した不具合が生じない、高信頼性の回路モジュールとその製造方法を得ることである。   The present invention has been made to solve the above-described problems. The purpose of the present invention is to join a container body and a lid on a flat plate formed of a dielectric substrate such as a ceramic substrate by soldering or bonding. In addition, the present invention is to obtain a highly reliable circuit module and a method for manufacturing the same, which do not cause problems due to soldering or adhesion in the operation and characteristics of the electronic components sealed in the container.

本発明に係わる回路モジュールは、電子部品を搭載するためのセラミックキャリア基板と、セラミックキャリア基板の表面に設けられたセラミック基板パッドと、キャビティを有し、且つ底面がはんだでセラミック基板パッドに接合されたリッドとを備えた回路モジュールであって、リッドが、キャビティに隣接した突部と該突部を挟んでキャビティに隣接したへこみ部とからなる段差を設けた段差付リッドであり、突部がセラミック基板パッドと所定の間隔をあけてセラミックキャリア基板と接触しており、へこみ部がセラミック基板パッドとはんだで接合されるとともに突部のキャビティ空間側と対向する側にはんだの隙間が設けられているものである。 A circuit module according to the present invention has a ceramic carrier substrate for mounting electronic components, a ceramic substrate pad provided on the surface of the ceramic carrier substrate, a cavity, and a bottom surface joined to the ceramic substrate pad with solder. The lid is a stepped lid provided with a step composed of a protrusion adjacent to the cavity and a recess adjacent to the cavity across the protrusion. The ceramic substrate pad is in contact with the ceramic carrier substrate at a predetermined interval, and the indented portion is bonded to the ceramic substrate pad with solder, and a solder gap is provided on the side of the protrusion facing the cavity space side. It is what.

本発明に係わる回路モジュールは、リッドが、キャビティに隣接した突部と該突部を挟んでキャビティに隣接したへこみ部とからなる段差を設けた段差付リッドであり、突部がセラミック基板パッドと所定の間隔をあけてセラミックキャリア基板と接触しており、へこみ部がセラミック基板パッドとはんだで接合されるとともに突部のキャビティ空間側と対向する側にはんだの隙間が設けられているものであるので、リッドをセラミックキャリア基板に接合するのに用いられるプリコートはんだ層中に取り込まれていたボイドが破裂しても、溶融した液体のはんだ微粒子や残留フラックス成分がキャビティ内に飛散するのを防止でき、飛散物に起因するショートや腐蝕等がなく、高い信頼性を有するとの効果が得られる。 In the circuit module according to the present invention, the lid is a stepped lid provided with a step including a protrusion adjacent to the cavity and a dent adjacent to the cavity across the protrusion, and the protrusion is connected to the ceramic substrate pad. It is in contact with the ceramic carrier substrate at a predetermined interval, the indented portion is joined with the ceramic substrate pad by solder, and a solder gap is provided on the side of the protrusion facing the cavity space side. Therefore, even if the voids taken in the precoat solder layer used to join the lid to the ceramic carrier substrate burst, it is possible to prevent the molten liquid solder particles and residual flux components from scattering into the cavity. In addition, there is no short circuit or corrosion caused by the scattered matter, and an effect of having high reliability can be obtained.

実施の形態1.
図1は、本発明の実施の形態1に係わる回路モジュールの断面模式図である。
図1に示すように、本実施の形態の回路モジュール100は、セラミック基板からなる平板状の誘電体容器本体(この後、セラミックキャリア基板と記す)1と、このセラミックキャリア基板1の表面に設けられたセラミック基板パッド2と、セラミックキャリア基板1の回路部に実装される電子部品3と、この電子部品3を収納する複数個の凹部であるキャビティ4を有し、且つ独特の形状のリッド(この後、段差付リッドと記す)5と、この段差付リッド5の底面をセラミック基板パッド2に接合するはんだ6とを備えている。
図2は、本実施の形態の回路モジュール100に用いられる段差付リッド5のキャビティ4が形成された側の平面(a)とこの平面のM−M断面(b)との模式図である。
図2に示すように、段差付リッド5は底面に段差が設けられ、この段差により段差付リッド5の底面のキャビティ4空間側の縁部が突部7となっており、段差付リッド5の底面の突部7以外の部分がへこみ部となっている。そして、突部7は、キャビティ4を囲っている。
また、本実施の形態の回路モジュール100では、段差付リッド5の底面の突部7がセラミックキャリア基板1と接触するとともに、段差付リッド5の底面のへこみ部がセラミック基板パッド2にはんだ6で接合されている。また、突部7とセラミック基板パッド2との間には所定の間隔が設けられており、突部7のキャビティ4空間側と対向する側の全てがはんだ6で接合されるのではなく、隙間8が設けられている。
Embodiment 1 FIG.
FIG. 1 is a schematic cross-sectional view of a circuit module according to Embodiment 1 of the present invention.
As shown in FIG. 1, a circuit module 100 according to the present embodiment is provided on a flat dielectric container body (hereinafter referred to as a ceramic carrier substrate) 1 made of a ceramic substrate and on the surface of the ceramic carrier substrate 1. A ceramic substrate pad 2, an electronic component 3 mounted on a circuit portion of the ceramic carrier substrate 1, and a cavity 4 that is a plurality of recesses for housing the electronic component 3, and has a unique shape lid ( After this, a stepped lid) 5 and solder 6 for joining the bottom surface of the stepped lid 5 to the ceramic substrate pad 2 are provided.
FIG. 2 is a schematic view of the plane (a) on the side where the cavity 4 of the stepped lid 5 used in the circuit module 100 of the present embodiment is formed and the MM cross section (b) of this plane.
As shown in FIG. 2, the stepped lid 5 is provided with a step on the bottom surface, and by this step, the edge of the bottom surface of the stepped lid 5 on the cavity 4 space side becomes a protrusion 7. A portion other than the protrusion 7 on the bottom is a dent. The protrusion 7 surrounds the cavity 4.
In the circuit module 100 according to the present embodiment, the protrusion 7 on the bottom surface of the stepped lid 5 contacts the ceramic carrier substrate 1, and the dent portion on the bottom surface of the stepped lid 5 is soldered to the ceramic substrate pad 2. It is joined. Further, a predetermined gap is provided between the protrusion 7 and the ceramic substrate pad 2, and not all of the side of the protrusion 7 facing the cavity 4 space side is joined by the solder 6, but a gap 8 is provided.

本実施の形態の回路モジュール100では、セラミックキャリア基板1に、例えば表面および内部に導体層を有するLTCC基板が用いられ、金属性の段差付リッド5には、例えば、コバール材が用いられる。
セラミックキャリア基板1が、線膨張係数が5.5ppm/℃前後のLTCC基板の場合に、線膨張係数が4.7ppm/℃前後とセラミックキャリア基板1の線膨張係数に近いコバール材を段差付リッド5に用いることは、段差付リッド5のはんだ接合時の熱ストレスを低減させるので、回路モジュール100の信頼性の面から好ましい。
図2に示す金属性の段差付リッド5は、エッチング、MIM(Metal Injection Mold)、鋳造等にて製造される。また、図3に断面模式図を示すプレスにて製造した金属性の段差付リッド5も用いることができる。
In the circuit module 100 of the present embodiment, for example, an LTCC substrate having a conductor layer on the surface and inside is used for the ceramic carrier substrate 1, and for example, a Kovar material is used for the metallic stepped lid 5.
When the ceramic carrier substrate 1 is an LTCC substrate having a linear expansion coefficient of about 5.5 ppm / ° C., a Kovar material having a linear expansion coefficient of about 4.7 ppm / ° C. and close to the linear expansion coefficient of the ceramic carrier substrate 1 is provided with a stepped lid. 5 is preferable from the viewpoint of the reliability of the circuit module 100 because it reduces thermal stress during solder joining of the stepped lid 5.
The metallic stepped lid 5 shown in FIG. 2 is manufactured by etching, MIM (Metal Injection Mold), casting or the like. Moreover, the metallic stepped lid 5 manufactured with the press which shows a cross-sectional schematic diagram in FIG. 3 can also be used.

また、コバール製の段差付リッド5は、はんだの濡れ性の向上と錆を防止するため、例えば、ニッケル下地の金めっき等のめっき処理を施すのが好ましい。この時の金めっきの厚さは、例えば、フラッシュ金めっきにより0.1μm以下にすることが、コスト面から有利である。また、金めっきの厚さを薄くすることは、はんだの主構成材料であるSnとの金属間化合物の生成を抑制し、はんだとの接合の信頼性を向上させる。
また、段差付リッド5にニッケル下地の金めっき処理がされていると、回路モジュールの製造において、段差付リッド5の仮固定が容易となる。
コバール製の段差付リッド5は、ニッケルめっきのみのものでも良い。ニッケルめっきのみの段差付リッド5は、水素還元炉や酸素濃度が極めて低い(例えば、10ppm程度以下)特殊な炉で処理して、はんだの濡れを阻害する酸化物層がニッケルめっき表面に形成するのを防止することにより、用いることができる。
はんだ6には、例えば、Sn−3Ag−0.5Cuはんだが用いられる。セラミック基板パッド2には、導電性であるとともに、はんだプリコート層を形成できる材料が用いられる。
In addition, the stepped lid 5 made of Kovar is preferably subjected to a plating treatment such as gold plating on a nickel base in order to improve solder wettability and prevent rust. It is advantageous from the viewpoint of cost that the thickness of the gold plating at this time is, for example, 0.1 μm or less by flash gold plating. Further, reducing the thickness of the gold plating suppresses the formation of an intermetallic compound with Sn, which is the main constituent material of the solder, and improves the reliability of bonding with the solder.
Further, when the stepped lid 5 is gold-plated with a nickel base, the stepped lid 5 can be temporarily fixed in the manufacture of the circuit module.
The Kovar stepped lid 5 may be nickel plating only. The stepped lid 5 made only of nickel plating is processed in a hydrogen reduction furnace or a special furnace having a very low oxygen concentration (for example, about 10 ppm or less), and an oxide layer that inhibits solder wetting is formed on the nickel plating surface. It can be used by preventing this.
For example, Sn-3Ag-0.5Cu solder is used for the solder 6. The ceramic substrate pad 2 is made of a conductive material that can form a solder precoat layer.

本実施の形態の回路モジュール100の製造方法を説明する。
図4は、本実施の形態の回路モジュール100の製造工程を示す模式図である。
まず、図4(a)に示すように、準備工程として、はんだをプリコート可能なセラミック基板パッド2を設けたセラミックキャリア基板1を準備する。準備するセラミックキャリア基板1としては、例えば、縦が18mm、横が17mm、厚さが0.7mmの寸法のものが挙げられる。
次に、図4(b)に示すように、はんだペースト塗布工程として、はんだペーストを厚さが150μm前後の印刷ステンシルを用いて供給し、セラミック基板パッド2上に、はんだペースト層9を形成する。
A method for manufacturing the circuit module 100 of the present embodiment will be described.
FIG. 4 is a schematic diagram showing a manufacturing process of the circuit module 100 of the present embodiment.
First, as shown in FIG. 4A, as a preparation step, a ceramic carrier substrate 1 provided with a ceramic substrate pad 2 that can be precoated with solder is prepared. Examples of the ceramic carrier substrate 1 to be prepared include those having dimensions of 18 mm in length, 17 mm in width, and 0.7 mm in thickness.
Next, as shown in FIG. 4B, as a solder paste application process, the solder paste is supplied using a printing stencil having a thickness of about 150 μm to form a solder paste layer 9 on the ceramic substrate pad 2. .

次に、プリコートはんだ形成工程として、セラミック基板パッド2上にはんだペースト層9が形成されたセラミックキャリア基板1をリフロー炉(図示せず)にて加熱し、はんだを一度溶融させる。加熱工程の終了後、はんだを冷却固化させることによって、図4(c)に示すように、プリコートはんだ層10を形成する。形成されたプリコートはんだ層10の形状はドーム状であり、その最大厚さ(高さ)は130μm前後である。
この時、はんだペースト中に含まれていた大部分のフラックスは、リフロー工程中のはんだが溶融した段階で、はんだとの比重差によってプリコートはんだ層10の表面または周囲に排斥され移動する。
しかし、フラックスのごく一部は、フラックスに含まれている溶剤の揮発に伴う発泡や振動、リフロー炉の搬送機構による振動、溶融状態のはんだの対流等により、はんだ層の中に取り残され、図4(c)に示すように、プリコートはんだ層10中にボイド11となって留まる。
プリコートはんだ工程が完了した時点では、プリコートはんだ層10を覆う不要になったフラックスが存在するが、セラミックキャリア基板1を有機溶剤等で洗浄することにより、溶解除去され、図4(c)に示すように、フラックスはプリコートはんだ層10の表面には残っていない。
Next, as a precoat solder forming step, the ceramic carrier substrate 1 having the solder paste layer 9 formed on the ceramic substrate pad 2 is heated in a reflow furnace (not shown) to melt the solder once. After the heating step is completed, the solder is cooled and solidified to form the precoat solder layer 10 as shown in FIG. The formed precoat solder layer 10 has a dome shape, and its maximum thickness (height) is around 130 μm.
At this time, most of the flux contained in the solder paste is moved to the surface or the periphery of the precoat solder layer 10 due to the difference in specific gravity with the solder at the stage where the solder in the reflow process is melted.
However, a small part of the flux is left in the solder layer due to foaming and vibration accompanying the volatilization of the solvent contained in the flux, vibration by the transport mechanism of the reflow furnace, convection of the molten solder, etc. As shown in FIG. 4C, the voids 11 remain in the precoat solder layer 10.
At the time when the precoat soldering process is completed, there is an unnecessary flux covering the precoat solder layer 10, but it is dissolved and removed by washing the ceramic carrier substrate 1 with an organic solvent or the like, as shown in FIG. Thus, no flux remains on the surface of the precoat solder layer 10.

次に、電子部品の実装工程として、図4(d)に示すように、セラミック基板パッド2にプリコートはんだ層10が設けられたセラミックキャリア基板1の所定の位置に電子部品(部品や半導体素子)3が実装される。
通常、電子部品3は、樹脂製の接着剤(図示せず)などでダイボンドし、この接着剤が硬化した後、金ワイヤ等で電極間を接続することにより実装される。
Next, as an electronic component mounting step, as shown in FIG. 4D, an electronic component (component or semiconductor element) is placed at a predetermined position on the ceramic carrier substrate 1 in which the precoat solder layer 10 is provided on the ceramic substrate pad 2. 3 is implemented.
Usually, the electronic component 3 is mounted by die-bonding with a resin adhesive (not shown) or the like, and after the adhesive is cured, the electrodes are connected with a gold wire or the like.

次に、段差付リッド5のセラミックキャリア基板1への仮固定工程として、まず、段差付リッド5を準備する。例えば、上記寸法のセラミックキャリア基板1に対しては、縦が16mm、横が15mm、厚さが1.0mmの寸法の段差付リッド5を準備する。
そして、位置合わせ装置や治具を用いて、セラミックキャリア基板1のプリコートはんだ層10と段差付リッド5の接合部とを位置合わせする。
そして、図4(e)に示すようにして、バネやクリップ等の加圧固定治具(図示せず)を用い、段差付リッド5をプリコートはんだ層10に仮固定する。
Next, as a step for temporarily fixing the stepped lid 5 to the ceramic carrier substrate 1, first, the stepped lid 5 is prepared. For example, for the ceramic carrier substrate 1 having the above dimensions, a stepped lid 5 having a dimension of 16 mm in length, 15 mm in width, and 1.0 mm in thickness is prepared.
Then, the precoat solder layer 10 of the ceramic carrier substrate 1 and the joint portion of the stepped lid 5 are aligned using an alignment device or a jig.
Then, as shown in FIG. 4E, the stepped lid 5 is temporarily fixed to the precoat solder layer 10 using a pressure fixing jig (not shown) such as a spring or a clip.

次に、段差付リッド5のセラミックキャリア基板1への接合工程として、まず、段差付リッド5が仮固定されたセラミックキャリア基板1を、リフロー炉に投入する。そして、リフロー炉内を、フラックスを用いないはんだ接合(フラックスレスはんだ接合)を行うに必要な低酸素濃度(例えば、酸素濃度が1000ppm以下)にして、リフロー炉の温度を、はんだの溶融温度を超える温度(例えば、Sn−3Ag−0.5Cuはんだの場合であれば220℃以上)まで上昇させる。リフロー炉内の酸素濃度を低くするには、高濃度な窒素雰囲気とすることにより実現する。
そして低酸素濃度のリフロー炉内でプリコートはんだ層10を再溶融(リフロー)させ、加圧固定治具によって溶融したはんだの中に、段差付リッド5の接合部を押し込み、段差付リッド5とセラミックキャリア基板1とをはんだ接合する。その後、冷却することによりはんだ6を固化させて、図4(f)に示す回路モジュール100を得る。
また、段差付リッド5とセラミックキャリア基板1とのはんだ接合に、低酸素濃度のリフロー炉に替えて、加熱・加圧機構と窒素雰囲気を維持できるチャンバーを有する専用のリッド搭載装置も用いることができる。
本実施の形態の回路モジュール100の製造方法では、電子部品の実装工程がプリコートはんだ形成工程の後に設けられているが、段差付リッド5のセラミックキャリア基板1への仮固定工程前であれば、どの時点で行われても良い。
Next, as a step of bonding the stepped lid 5 to the ceramic carrier substrate 1, first, the ceramic carrier substrate 1 on which the stepped lid 5 is temporarily fixed is put into a reflow furnace. Then, the inside of the reflow furnace is set to a low oxygen concentration (for example, oxygen concentration is 1000 ppm or less) necessary for performing solder joining without using flux (fluxless solder joining), and the temperature of the reflow furnace is set to the melting temperature of the solder. The temperature is increased to above (for example, in the case of Sn-3Ag-0.5Cu solder, 220 ° C. or higher). In order to reduce the oxygen concentration in the reflow furnace, a high concentration nitrogen atmosphere is used.
Then, the precoat solder layer 10 is remelted (reflowed) in a low oxygen concentration reflow furnace, and the joined portion of the stepped lid 5 is pushed into the molten solder by a pressure fixing jig. The carrier substrate 1 is soldered. Thereafter, the solder 6 is solidified by cooling to obtain the circuit module 100 shown in FIG.
In addition, instead of using a low oxygen concentration reflow furnace, a dedicated lid mounting device having a heating / pressurizing mechanism and a chamber capable of maintaining a nitrogen atmosphere may be used for solder bonding between the stepped lid 5 and the ceramic carrier substrate 1. it can.
In the manufacturing method of the circuit module 100 of the present embodiment, the electronic component mounting step is provided after the precoat solder forming step, but if the stepped lid 5 is before the temporary fixing step to the ceramic carrier substrate 1, It can be done at any point.

本実施の形態の回路モジュール100が、キャビティ4内の空間への、はんだボールやフラックスの飛散が防止された構造であり、その製造方法が、はんだボールやフラックスをキャビティ4内の空間へ飛散させない方法であることを説明する。
図5は、底面に段差を設けていないリッド55を用いた従来の回路モジュール500の一例を示す断面模式図である。
図5に示すように、リッド55の底面が、セラミックキャリア基板1のセラミック基板パッド2の直上にあり、リッド55の底面は平坦で突部がなく、且つ底面の幅がセラミック基板パッド2の幅より狭く、キャビティ54の空間側の壁部の面(この後、内側面と記す)、および、壁部の内側面と対向する面(この後、外側面と記す)とに、はんだフィレット50が形成されていること以外、本実施の形態の回路モジュール100と同様である。
The circuit module 100 of the present embodiment has a structure in which solder balls and flux are prevented from scattering into the space in the cavity 4, and the manufacturing method does not cause the solder balls and flux to be scattered into the space in the cavity 4. Explain that it is a method.
FIG. 5 is a schematic cross-sectional view showing an example of a conventional circuit module 500 using a lid 55 having no step on the bottom surface.
As shown in FIG. 5, the bottom surface of the lid 55 is directly above the ceramic substrate pad 2 of the ceramic carrier substrate 1, the bottom surface of the lid 55 is flat and has no protrusions, and the width of the bottom surface is the width of the ceramic substrate pad 2. The solder fillet 50 is narrower on the space side wall surface of the cavity 54 (hereinafter referred to as an inner surface) and the surface facing the inner surface of the wall portion (hereinafter referred to as an outer surface). Except for being formed, the circuit module 100 is the same as that of the present embodiment.

従来の回路モジュール500は、上記のような構造であるので、リッド55とセラミックキャリア基板1とを接合する工程において、リッド55の底面が、溶融したプリコートはんだ層に、加圧固定治具からの外力で押し込まれると、プリコートはんだ層中に取り込まれていたボイドが破裂し、溶融した液体のはんだ微粒子や残留フラックス成分が、キャビティ54内に飛散し、キャビティ54内の配線部分、実装された電子部品や半導体素子の表面、回路接続部に付着したり、キャビティ内を動き回る固形の異物として留まる。特に、図5に示すような、キャビティ54の壁部の内側面にはんだのフイレット50を生じた構造では、キャビティ54内にはんだの露出部があり、はんだ微粒子や残留フラックス成分のキャビティ54内への飛散が生じ易い。
そして、飛散物がはんだの場合にはショート、飛散物がフラックスの場合には腐蝕等が発生して、回路モジュールの信頼性が損なわれる。
Since the conventional circuit module 500 has the structure as described above, in the process of joining the lid 55 and the ceramic carrier substrate 1, the bottom surface of the lid 55 is applied to the melted precoat solder layer from the pressure fixing jig. When pushed in by an external force, the voids taken into the precoat solder layer burst, and the molten liquid solder fine particles and residual flux components are scattered in the cavity 54, and the wiring portion in the cavity 54 and the mounted electrons It remains as a solid foreign substance that adheres to the surface of a component or semiconductor element, a circuit connection portion, or moves around in the cavity. In particular, in the structure in which the solder fillet 50 is formed on the inner surface of the wall portion of the cavity 54 as shown in FIG. 5, there is an exposed portion of the solder in the cavity 54, and the solder particles and residual flux components enter the cavity 54. Is likely to occur.
When the scattered material is solder, a short circuit occurs. When the scattered material is a flux, corrosion or the like occurs, and the reliability of the circuit module is impaired.

これに対して、本実施の形態の回路モジュール100は、段差付リッド5の底面のキャビティ4空間側の縁部がキャビティ4を囲う突部7となっているとともに、この突部7とセラミック基板パッド2との間に所定の間隔が設けられ、突部7とセラミック基板パッド2とが直接接しないようにしてある。そのため、段差付リッド5の底面のへこみ部が、溶融したプリコートはんだ層に、加圧固定治具からの外力で押し込まれると、底面の突部7が、直ちにセラミックキャリア基板1の表面と接し、はんだ6が、キャビティ4内部と完全にシャットアウトされ、段差付リッド5のキャビティ4内部に、はんだ6が露出しない構造になっている。また、突部7とセラミック基板パッド2とに間隔を設け、段差付リッド5をキャビティ4内部から離れたところではんだと接合しているので、溶融したはんだが、突部7の下を潜りキャビティ4内に浸入するのが防止できる。
本実施の形態の回路モジュール100は、段差付リッド5の底面の突部7により、キャビティ内部にはんだ6を露出させない構造であるので、例え、プリコートはんだ層中に取り込まれていたボイドが破裂しても、溶融した液体のはんだ微粒子や残留フラックス成分がキャビティ4内に飛散するのが防止され、飛散物に起因するショートや腐蝕等のない、信頼性の高いものである。
それと、本実施の形態の回路モジュールの製造方法では、製造時、キャビティ4内に液体のはんだ微粒子や残留フラックス成分が飛散しない高信頼性の回路モジュールを得ることができる。
また、段差付リッド5は、その底面に突部7が設けられているので、バネやクリップ等の加圧固定治具の加圧力が高い場合であっても、段差付リッド5が必要以上に沈み込まないという効果もある。
On the other hand, in the circuit module 100 of the present embodiment, the edge of the bottom surface of the stepped lid 5 on the cavity 4 space side is a protrusion 7 that surrounds the cavity 4, and the protrusion 7 and the ceramic substrate A predetermined interval is provided between the pad 2 and the protrusion 7 and the ceramic substrate pad 2 so as not to be in direct contact with each other. Therefore, when the recessed portion on the bottom surface of the stepped lid 5 is pushed into the melted precoat solder layer by an external force from the pressure fixing jig, the protrusion 7 on the bottom surface immediately contacts the surface of the ceramic carrier substrate 1, The solder 6 is completely shut out from the inside of the cavity 4 so that the solder 6 is not exposed inside the cavity 4 of the stepped lid 5. Further, since the protrusion 7 and the ceramic substrate pad 2 are spaced apart and the stepped lid 5 is joined to the solder at a distance from the inside of the cavity 4, the molten solder dives under the protrusion 7 and enters the cavity 4. Intrusion can be prevented.
Since the circuit module 100 of the present embodiment has a structure in which the solder 6 is not exposed inside the cavity by the protrusion 7 on the bottom surface of the stepped lid 5, for example, the void taken into the precoat solder layer is ruptured. However, it is possible to prevent the molten liquid solder fine particles and residual flux components from being scattered in the cavity 4, and there is no short circuit or corrosion caused by the scattered matter, and the reliability is high.
In addition, in the circuit module manufacturing method of the present embodiment, a highly reliable circuit module in which liquid solder fine particles and residual flux components are not scattered in the cavity 4 at the time of manufacturing can be obtained.
Further, since the stepped lid 5 is provided with the protrusion 7 on the bottom surface, the stepped lid 5 is more than necessary even when the pressure of a pressure fixing jig such as a spring or a clip is high. There is also an effect of not sinking.

本実施の形態の回路モジュール100の有効性を確認するため、以下のような評価試験を実施した。
評価サンプルとしての本実施の形態の回路モジュール100と、比較サンプルとしての従来の回路モジュール500とを、各々20個調製した。
第1の評価試験として、キャビティ内に付着していないはんだやフラックス片等、移動可能な異物を検出するためのピンド試験(PIND試験:Particle Impact Noise Detection Test「微粒子衝撃振動ノイズ検出試験」)を、MIL規格(MIL-STD883,method 2020)に準拠して、実施した。
第2の評価試験として、ピンド試験終了後の評価サンプルと比較サンプルとの全てについて、キャビティ内の異物の目視観察を行なった。
目視観察の方法は、まず、リッドの天井部分を薄膜状態になるまで研削・研磨して、リッドの天井部分の厚さが50μm以下まで薄くした後、鋭利な刃物によりリッドの天井部分を切開・開封した。次に、高倍率の光学顕微鏡を用い、セラミックキャリア基板1の配線上や金ワイヤ部分への異物付着の有無を確認した。評価サンプルに対しては、異物付着に加えて、キャビティの壁部の内側面に形成されるはんだフィレットの有無も確認した。
評価サンプルと比較サンプルとの評価結果を表1にまとめて示した。
表1から明らかなように、比較サンプルには20個のサンプルの内、ピンド不良品が4個と異物付着品が2個認められたが、評価サンプルには、20個のサンプルの全てに、ピンド不良、異物付着、フィレット形成が認められなかった。
すなわち、本実施の形態の回路モジュール100は、段差付リッド5のキャビティ4内への飛散物がない、信頼性に優れた回路モジュールであることが確認された。
本実施の形態の回路モジュール100の説明に用いた段差付リッド5では2個のキャビティを有するが、これに限定されるものではなく、1個であっても、寸法的に形成できるならば2個より多い複数であっても良い。
In order to confirm the effectiveness of the circuit module 100 of the present embodiment, the following evaluation test was performed.
20 circuit modules 100 of the present embodiment as evaluation samples and 20 conventional circuit modules 500 as comparative samples were prepared.
As a first evaluation test, a pinned test (PIND test: Particle Impact Noise Detection Test) for detecting movable foreign matter such as solder and flux pieces not adhering in the cavity In accordance with the MIL standard (MIL-STD883, method 2020).
As a second evaluation test, the foreign matter in the cavity was visually observed for all of the evaluation sample and the comparative sample after completion of the pinned test.
The method of visual observation is to first grind and polish the ceiling part of the lid until it becomes a thin film state. After the thickness of the ceiling part of the lid is reduced to 50 μm or less, the ceiling part of the lid is incised and sharpened with a sharp blade. Opened. Next, using a high-magnification optical microscope, the presence or absence of foreign matter on the wiring of the ceramic carrier substrate 1 or on the gold wire portion was confirmed. For the evaluation sample, in addition to the adhesion of foreign matter, the presence or absence of solder fillets formed on the inner surface of the cavity wall was also confirmed.
Table 1 summarizes the evaluation results of the evaluation sample and the comparative sample.
As is apparent from Table 1, among the 20 samples, 4 pinned defective products and 2 foreign matter adhered products were recognized in the comparative samples, but the evaluation samples included all 20 samples. Pinning failure, foreign matter adhesion, and fillet formation were not observed.
That is, it was confirmed that the circuit module 100 according to the present embodiment is a highly reliable circuit module that has no scattered matter into the cavity 4 of the stepped lid 5.
The stepped lid 5 used in the description of the circuit module 100 of the present embodiment has two cavities, but is not limited to this. There may be more than a plurality.

Figure 0004856014
Figure 0004856014

実施の形態2.
図6は、本実施の形態の回路モジュールに用いられる段差付リッドのキャビティが形成された側の平面(a)とこの平面のN−N断面(b)との模式図である。
本実施の形態の回路モジュールは、図6に示す、底面の突部27のセラミックキャリア基板1と接する面29以外が金めっきされている段差付リッド25を用いた以外、実施の形態1の回路モジュールと同様である。
突部27のセラミックキャリア基板1と接する面29以外が金めっきされている段差付リッド25は、実施の形態1におけるニッケル下地の金めっきがされた段差付リッド5から、セラミックキャリア基板1と接する面29の金めっきを除去することにより、実現できる。金めっきの除去方法には、例えば、レーザ除去方法や機械的な切削除去方法が挙げられる。
Embodiment 2. FIG.
FIG. 6 is a schematic diagram of the plane (a) on the side where the cavity of the stepped lid used in the circuit module of the present embodiment is formed and the NN cross section (b) of this plane.
The circuit module according to the present embodiment is the circuit according to the first embodiment except that the stepped lid 25 shown in FIG. 6 except for the surface 29 of the bottom protrusion 27 other than the surface 29 in contact with the ceramic carrier substrate 1 is gold-plated. Similar to modules.
The stepped lid 25 that is gold-plated except for the surface 29 of the protrusion 27 that contacts the ceramic carrier substrate 1 is in contact with the ceramic carrier substrate 1 from the stepped lid 5 that is gold-plated on the nickel base in the first embodiment. This can be realized by removing the gold plating on the surface 29. Examples of the gold plating removal method include a laser removal method and a mechanical cutting removal method.

本実施の形態の回路モジュールは、段差付リッド25の底面における突部27のセラミックキャリア基板1と接する面29に金めっきがないので、はんだの溶融温度以上のリフロー炉中での加熱時間が1分を超える場合やプリコートはんだの量が非常に多い場合に起こる、溶融したはんだが溢れ、数μm以下の局所的な間隙をも伝って金めっき面を濡れ広がり、キャビティ24内部にはい上がってしまう現象を防止できる。
濡れ広がったはんだは、ボイドが無いので異物飛散の原因とはならないが、本実施の形態の回路モジュールは、キャビティ24内部に濡れ広がったはんだ自身によって起こる可能性のある不具合も防止できる。
In the circuit module of the present embodiment, there is no gold plating on the surface 29 in contact with the ceramic carrier substrate 1 of the protrusion 27 on the bottom surface of the stepped lid 25, so that the heating time in the reflow furnace above the melting temperature of the solder is 1 When the amount of pre-coat solder is exceeded or the amount of pre-coated solder is very large, the molten solder overflows, the gold-plated surface is wetted and propagates through a local gap of several μm or less, and rises into the cavity 24. The phenomenon can be prevented.
The wet spread solder does not cause foreign matter scattering because there is no void, but the circuit module of the present embodiment can also prevent problems that may occur due to the solder spread in the cavity 24 itself.

実施の形態3.
本実施の形態の回路モジュールの製造方法は、金めっき処理された段差付リッド5とセラミックキャリア基板1に形成したプリコートはんだ層10との仮固定工程の直前に、プリコートはんだ層10へ段差付リッド5を位置合わせした後に、段差付リッド5をプリコートはんだ層10に仮接合する工程を追加して設けたこと以外、実施の形態1の回路モジュールの製造方法と同様である。
例えば、はんだにSn−3Ag−0.5Cuはんだを用いた場合、このはんだの融点の220℃よりもやや低い温度領域(210℃〜220℃未満の温度)の環境で、プリコートはんだ層10と位置合わせされた段差付リッド5に、500g〜2kg程度の荷重を数秒〜数十秒与えてプリコートはんだ層10に接触させる。すると、プリコートはんだ層10に局所的な軟化状態が形成され、図7に示すように、段差付リッド5がプリコートはんだ層10に仮接合される。
本実施の形態では、仮接合の温度を220℃よりもやや低い温度領域としたが、用いられるはんだの融点に応じて、その融点よりやや低い温度領域(融点から10℃低い温度から融点未満の温度)が適宜用いられる。
Embodiment 3 FIG.
The manufacturing method of the circuit module according to the present embodiment includes a stepped lid on the precoat solder layer 10 immediately before the temporary fixing step between the gold-plated stepped lid 5 and the precoat solder layer 10 formed on the ceramic carrier substrate 1. The method is the same as that of the circuit module manufacturing method according to the first embodiment except that a step of temporarily bonding the stepped lid 5 to the precoat solder layer 10 is provided after aligning 5.
For example, when Sn-3Ag-0.5Cu solder is used as the solder, the position of the precoat solder layer 10 is the same as that of the solder in a temperature range slightly lower than the melting point 220 ° C. A load of about 500 g to 2 kg is applied to the combined stepped lid 5 for several seconds to several tens of seconds to bring it into contact with the precoat solder layer 10. Then, a local softened state is formed in the precoat solder layer 10, and the stepped lid 5 is temporarily joined to the precoat solder layer 10 as shown in FIG. 7.
In the present embodiment, the temperature of the temporary bonding is set to a temperature range slightly lower than 220 ° C., but depending on the melting point of the solder used, a temperature range slightly lower than the melting point (temperature lower than the melting point by 10 ° C. to lower than the melting point). Temperature) is used as appropriate.

本実施の形態の回路モジュールの製造方法では、段差付リッド5をプリコートはんだ層10に仮接合する工程が設けられ、段差付リッド5がプリコートはんだ層10に仮接合されている。そのため、段差付リッド5をセラミックキャリア基板1へ接合するリフローを実施するまでの準備段階において、ハンドリングの誤り等により起こる段差付リッド5の位置ずれが防止でき、回路モジュールの製造における歩留まりを向上できる。
実施の形態1の回路モジュールの製造方法では、電子部品の実装工程が仮固定工程の前にが設けられているが、本実施の形態の回路モジュールの製造方法では仮接合する工程前であれば、どの時点で行われても良い。
In the circuit module manufacturing method of the present embodiment, a step of temporarily bonding the stepped lid 5 to the precoat solder layer 10 is provided, and the stepped lid 5 is temporarily bonded to the precoat solder layer 10. Therefore, in the preparatory stage until the reflow for bonding the stepped lid 5 to the ceramic carrier substrate 1 is performed, the stepped lid 5 can be prevented from being displaced due to an error in handling and the like, and the yield in manufacturing the circuit module can be improved. .
In the circuit module manufacturing method according to the first embodiment, the electronic component mounting step is provided before the temporary fixing step. However, in the circuit module manufacturing method according to the present embodiment, if the step is before the temporary bonding step, It can be done at any time.

実施の形態4.
図8は、本発明の実施の形態4に係わる回路モジュールの断面模式図である。
図8に示すように、本実施の形態の回路モジュール300は、セラミックキャリア基板1に段差付リッド5を接合するのに、導電性樹脂36を用いた以外、実施の形態1の回路モジュールと同様である。
本実施の形態の回路モジュール300に用いられる導電性樹脂36としては、銀粒子を含んだエポキシ系樹脂が挙げられる。
また、段差付リッド5は、ニッケルめっきのみのものが、導電性樹脂36との接着性の観点から好ましい。
Embodiment 4 FIG.
FIG. 8 is a schematic cross-sectional view of a circuit module according to Embodiment 4 of the present invention.
As shown in FIG. 8, the circuit module 300 according to the present embodiment is the same as the circuit module according to the first embodiment except that the conductive resin 36 is used to join the stepped lid 5 to the ceramic carrier substrate 1. It is.
Examples of the conductive resin 36 used in the circuit module 300 of the present embodiment include an epoxy resin containing silver particles.
Further, the stepped lid 5 is preferably only nickel plated from the viewpoint of adhesiveness to the conductive resin 36.

本実施の形態の回路モジュール300の製造方法を説明する。
まず、実施の形態1の回路モジュールに用いたのと同様のセラミックキャリア基板1を準備する。
次に、導電性樹脂塗布工程として、未硬化状態の液体の導電性樹脂を、ディスペンサ装置を用いて供給し、セラミック基板パッド2上に、導電性樹脂層を形成する。そして、予備加熱を行い、導電性樹脂を半硬化状態にして、固形のプリコート導電性樹脂層を形成する。この半硬化状態のプリコート導電性樹脂層は、樹脂が完全硬化に至る前段階で硬化反応を停止させたものであり、再加熱により再度液状になる。
次に、実施の形態1と同様にして、セラミックキャリア基板1の所定の位置に電子部品(部品や半導体素子)3を実装する。
次に、加熱機構付きのマウンター(図示せず)のステージに、プリコート導電性樹脂層が形成されたセラミックキャリア基板1を固定する。そして、加熱機構付きのマウンターのヘッドで、段差付リッド5をピックアップする。さらに、加熱機構付きのマウンターの位置決め機能を用いて、段差付リッド5の接合部とセラミックキャリア基板1のプリコート導電性樹脂層とを位置合わせする。
A method for manufacturing the circuit module 300 of the present embodiment will be described.
First, the same ceramic carrier substrate 1 as that used in the circuit module of the first embodiment is prepared.
Next, as a conductive resin coating step, an uncured liquid conductive resin is supplied using a dispenser device, and a conductive resin layer is formed on the ceramic substrate pad 2. Then, preheating is performed to make the conductive resin semi-cured to form a solid precoat conductive resin layer. This semi-cured pre-coated conductive resin layer is obtained by stopping the curing reaction at a stage before the resin is completely cured, and becomes liquid again by reheating.
Next, in the same manner as in the first embodiment, an electronic component (component or semiconductor element) 3 is mounted at a predetermined position on the ceramic carrier substrate 1.
Next, the ceramic carrier substrate 1 on which the precoat conductive resin layer is formed is fixed to the stage of a mounter (not shown) with a heating mechanism. And the lid 5 with a level | step difference is picked up with the head of the mounter with a heating mechanism. Furthermore, the bonding part of the stepped lid 5 and the precoat conductive resin layer of the ceramic carrier substrate 1 are aligned using the positioning function of the mounter with a heating mechanism.

次に、段差付リッド5の接合部をセラミックキャリア基板1のプリコート導電性樹脂層に接触させ、加熱機構付きマウンターのヘッドとステージとを加熱し、プリコート導電性樹脂層の再溶融に必要な温度まで上昇させる。
プリコート導電性樹脂層が溶融した時点で、ヘッドを降下させ、段差付リッド5の接合部を溶融した導電性樹脂層中に押し込む。
導電性樹脂36が完全硬化するまで段差付リッド5を保持し、導電性樹脂36を硬化させて、段差付リッド5をセラミックキャリア基板1に接着接合した後、加熱機構付きマウンターのヘッドとステージとの双方を冷却する。冷却後、加熱機構付きマウンターから取り出して、回路モジュール300が完成する。
本実施の形態の回路モジュール300の製造方法では、電子部品の実装工程がプリコート導電性樹脂層形成後に設けられているが、加熱機構付きのマウンターのステージに、プリコート導電性樹脂層を形成したセラミックキャリア基板1を固定する前であれば、どの時点で行われても良い。
Next, the joint of the stepped lid 5 is brought into contact with the precoat conductive resin layer of the ceramic carrier substrate 1, the head and the stage of the mounter with a heating mechanism are heated, and the temperature necessary for remelting the precoat conductive resin layer Raise to.
When the precoat conductive resin layer is melted, the head is lowered and the joint portion of the stepped lid 5 is pushed into the melted conductive resin layer.
The stepped lid 5 is held until the conductive resin 36 is completely cured, the conductive resin 36 is cured, and the stepped lid 5 is bonded and bonded to the ceramic carrier substrate 1. Cool both sides. After cooling, the circuit module 300 is completed by removing from the mounter with a heating mechanism.
In the method for manufacturing circuit module 300 of the present embodiment, the electronic component mounting step is provided after the precoat conductive resin layer is formed, but the ceramic in which the precoat conductive resin layer is formed on the stage of the mounter with a heating mechanism is provided. As long as it is before fixing the carrier substrate 1, it may be performed at any time.

本実施の形態の回路モジュール300、および、その製造方法においては、セラミック基板パッド2上に、導電性樹脂層を形成する際に、導電性樹脂層中にボイドが取り込まれる。そして、加熱機構付きマウンターにおいて、加熱され再溶融したプリコート導電性樹脂層中に、段差付リッド5の接合部が押し込まれると、ボイドが破裂し、溶融状態の樹脂の一部が分離して飛散する。
しかし、本実施の形態の回路モジュールおよびその製造方法では、底面のキャビティ4空間側の縁部に突部7が設けられ、且つ突部7がキャビティ4を囲っている段差付リッド5が用いられているので、キャビティ4内への樹脂の飛散が防止できる。
また、本実施の形態の回路モジュールおよびその製造方法では、段差付リッド5が用いられており、加熱機構付きマウンターの加圧力を特に配慮する必要がなく、例え、段差付リッド5が強く押しつけられても、突部7がセラミックキャリア基板1に接することにより、スペーサの機能を果たすので、段差付リッド5の接着面が必要以上に沈み込み導電性樹脂を外部に排出することを防止するとの効果も得られる。
In the circuit module 300 according to the present embodiment and the manufacturing method thereof, voids are taken into the conductive resin layer when the conductive resin layer is formed on the ceramic substrate pad 2. Then, in the mounter with a heating mechanism, when the joined portion of the stepped lid 5 is pushed into the pre-coated conductive resin layer that has been heated and remelted, the void bursts and a part of the molten resin is separated and scattered. To do.
However, in the circuit module and the manufacturing method thereof according to the present embodiment, the stepped lid 5 is used in which the protrusion 7 is provided at the edge of the bottom surface on the cavity 4 space side and the protrusion 7 surrounds the cavity 4. Therefore, the resin can be prevented from scattering into the cavity 4.
Further, in the circuit module and the manufacturing method thereof according to the present embodiment, the stepped lid 5 is used, and there is no need to particularly consider the pressure applied by the mounter with a heating mechanism. For example, the stepped lid 5 is strongly pressed. However, since the projection 7 functions as a spacer by contacting the ceramic carrier substrate 1, it is possible to prevent the adhesive surface of the stepped lid 5 from sinking more than necessary and discharging the conductive resin to the outside. Can also be obtained.

実施の形態5.
本実施の形態の回路モジュールの製造方法は、段差付リッド5の接合部をセラミックキャリア基板1のプリコート導電性樹脂層に接触させた後の工程が、加熱機構付きマウンターのヘッドのみの加熱により、段差付リッド5のみを加熱し、段差付リッド5側からプリコート導電性樹脂層に入熱させ、プリコート導電性樹脂層の段差付リッド5と接触する局所を軟化状態とした後、導電性樹脂層を再度冷却して、段差付リッド5をセラミックキャリア基板1に仮接着する仮接着工程と、仮接着された段差付リッド5をバネやクリップ等の加圧固定治具によって仮固定したものを、加熱乾燥炉中で高温に保持して導電性樹脂を完全硬化させた後、室温まで冷却して加熱乾燥炉から取り出す本接着工程とを用いる以外、実施の形態4の回路モジュールの製造方法と同様である。
本実施の形態において、仮接着に要する時間は導電性樹脂の種類や加熱機構付きマウンターの設定温度によって変わるが、通常は1秒〜数秒である。
Embodiment 5 FIG.
In the method of manufacturing the circuit module according to the present embodiment, the step after bringing the joint portion of the stepped lid 5 into contact with the precoat conductive resin layer of the ceramic carrier substrate 1 is performed by heating only the head of the mounter with a heating mechanism. Only the stepped lid 5 is heated, heat is applied to the precoat conductive resin layer from the stepped lid 5 side, and the local contact with the stepped lid 5 of the precoat conductive resin layer is softened, and then the conductive resin layer Is cooled again and temporarily bonded the stepped lid 5 to the ceramic carrier substrate 1, and the temporarily bonded stepped lid 5 is temporarily fixed by a pressure fixing jig such as a spring or a clip, The circuit module according to the fourth embodiment is used except that the conductive bonding resin is completely cured by being held at a high temperature in a heating and drying furnace, and then cooled to room temperature and taken out from the heating and drying furnace. Is the same as the method of manufacturing.
In the present embodiment, the time required for temporary bonding varies depending on the type of conductive resin and the set temperature of the mounter with a heating mechanism, but is usually 1 second to several seconds.

本実施の形態の回路モジュールの製造方法では、段差付リッド5がセラミックキャリア基板1に仮接着されており、ハンドリング時に段差付リッド5がずれたり、脱落することがないので、段差付リッド5がセラミックキャリア基板1に仮接着されたものを大量に作製し、この大量に作製された仮接着品を加熱乾燥炉で加熱し、多くの仮接着品の導電性樹脂を一括して硬化することにより、セラミックキャリア基板1に段差付リッド5を接着接合でき、回路モジュールの生産性が向上する。   In the circuit module manufacturing method of the present embodiment, the stepped lid 5 is temporarily bonded to the ceramic carrier substrate 1, and the stepped lid 5 is not displaced or dropped during handling. By producing a large amount of temporarily bonded products on the ceramic carrier substrate 1, heating the large number of temporarily bonded products in a heating and drying furnace, and curing the conductive resins of many temporarily bonded products at once. Then, the stepped lid 5 can be adhesively bonded to the ceramic carrier substrate 1, and the productivity of the circuit module is improved.

本発明に係わる回路モジュールは、電子部品が収納されるキャビティ内に異物が残留しない回路モジュールであり、高い信頼性が要求される電子機器に有効に利用できる。   The circuit module according to the present invention is a circuit module in which no foreign matter remains in the cavity in which the electronic component is accommodated, and can be effectively used for an electronic device that requires high reliability.

実施の形態1に係わる回路モジュールの断面模式図である。2 is a schematic cross-sectional view of a circuit module according to Embodiment 1. FIG. 実施の形態1に係わる回路モジュールに用いられる段差付リッドのキャビティが形成された側の平面(a)とこの平面のM−M断面(b)との模式図である。It is a schematic diagram of the plane (a) on the side where the cavity of the stepped lid used in the circuit module according to Embodiment 1 is formed and the MM cross section (b) of this plane. 実施の形態1に係わる回路モジュールに用いられるプレス加工にて製造された段差付リッドの断面模式図である。3 is a schematic cross-sectional view of a stepped lid manufactured by press working used in the circuit module according to Embodiment 1. FIG. 実施の形態1に係わる回路モジュールの製造工程を示す模式図である。FIG. 3 is a schematic diagram illustrating a manufacturing process of the circuit module according to the first embodiment. 底面に段差を設けていないリッドを用いた従来の回路モジュールの断面模式図である。It is a cross-sectional schematic diagram of the conventional circuit module using the lid which does not provide the level | step difference in the bottom face. 実施の形態2に係わる回路モジュールに用いられる段差付リッドのキャビティが形成された側の平面(a)とこの平面のN−N断面との模式図である。It is a schematic diagram of the plane (a) on the side where the cavity of the stepped lid used in the circuit module according to Embodiment 2 is formed and the NN cross section of this plane. 実施の形態3に係わる回路モジュールの製造方法における段差付リッドがプリコートはんだ層に仮接合された状態を示す断面模式図である。FIG. 9 is a schematic cross-sectional view showing a state where a stepped lid in a circuit module manufacturing method according to Embodiment 3 is temporarily joined to a precoat solder layer. 実施の形態4に係わる回路モジュールの断面模式図である。6 is a schematic cross-sectional view of a circuit module according to Embodiment 4. FIG.

符号の説明Explanation of symbols

1 セラミックキャリア基板、2 セラミック基板パッド、3 電子部品、
4 キャビティ、5 段差付リッド、6 はんだ、7 突部、8 隙間、
9 はんだペースト層、10 プリコートはんだ層、11 ボイド、24 キャビティ、
25 段差付リッド、27 突部、29 突部のセラミックキャリア基板と接する面、
36 導電性樹脂、50 はんだフィレット、54 キャビティ、55 リッド、
100,300,500 回路モジュール。
1 ceramic carrier substrate, 2 ceramic substrate pad, 3 electronic components,
4 cavity, 5 stepped lid, 6 solder, 7 protrusion, 8 gap,
9 Solder paste layer, 10 Precoat solder layer, 11 Void, 24 cavity,
25 Lid with steps, 27 protrusions, 29 surfaces of the protrusions in contact with the ceramic carrier substrate,
36 conductive resin, 50 solder fillet, 54 cavity, 55 lid,
100, 300, 500 circuit modules.

Claims (6)

電子部品を搭載するためのセラミックキャリア基板と、上記セラミックキャリア基板の表面に設けられたセラミック基板パッドと、キャビティを有し、且つ底面がはんだで上記セラミック基板パッドに接合されたリッドとを備えた回路モジュールであって、
上記リッドが、上記キャビティに隣接した突部と該突部を挟んで上記キャビティに隣接したへこみ部とからなる段差を設けた段差付リッドであり、上記突部が上記セラミック基板パッドと所定の間隔をあけて上記セラミックキャリア基板と接触しており、上記へこみ部が上記セラミック基板パッドとはんだで接合されるとともに上記突部の上記キャビティ空間側と対向する側に上記はんだの隙間が設けられていることを特徴とする回路モジュール。
A ceramic carrier substrate for mounting electronic components, a ceramic substrate pad provided on the surface of the ceramic carrier substrate, and a lid having a cavity and having a bottom surface joined to the ceramic substrate pad by solder A circuit module,
The lid is a stepped lid provided with a step including a protrusion adjacent to the cavity and a dent adjacent to the cavity across the protrusion, and the protrusion is spaced from the ceramic substrate pad by a predetermined distance. The recess is in contact with the ceramic carrier substrate, the indented portion is bonded to the ceramic substrate pad by solder, and the solder gap is provided on the side of the protrusion facing the cavity space side . A circuit module characterized by that.
電子部品を搭載するためのセラミックキャリア基板と、上記セラミックキャリア基板の表面に設けられたセラミック基板パッドと、キャビティを有し、且つ底面が導電性樹脂で上記セラミック基板パッドに接合されたリッドとを備えた回路モジュールであって、
上記リッドが、上記キャビティに隣接した突部と該突部を挟んで上記キャビティに隣接したへこみ部とからなる段差を設けた段差付リッドであり、上記突部が上記セラミック基板パッドと所定の間隔をあけて上記セラミックキャリア基板と接触しており、上記へこみ部が上記セラミック基板パッドと導電性樹脂で接合されるとともに上記突部の上記キャビティ空間側と対向する側に上記導電性樹脂の隙間が設けられていることを特徴とする回路モジュール。
A ceramic carrier substrate for mounting electronic components, a ceramic substrate pad provided on the surface of the ceramic carrier substrate, and a lid having a cavity and having a bottom surface bonded to the ceramic substrate pad with a conductive resin A circuit module comprising:
The lid is a stepped lid provided with a step including a protrusion adjacent to the cavity and a dent adjacent to the cavity across the protrusion, and the protrusion is spaced from the ceramic substrate pad by a predetermined distance. And the recess is bonded to the ceramic substrate pad with a conductive resin, and a gap between the conductive resin is formed on the side of the protrusion facing the cavity space side. A circuit module characterized by being provided .
請求項1記載の回路モジュールの製造方法であって、
上記セラミック基板パッドを設けた、上記電子部品を搭載するための上記セラミックキャリア基板を調製する工程と、上記セラミック基板パッド上に、はんだペースト層を形成する工程と、上記セラミック基板パッド上に上記はんだペースト層が形成された上記セラミックキャリア基板を加熱し、上記はんだペースト層を溶融後、冷却固化してプリコートはんだ層を形成する工程と、上記段差付リッドを上記セラミックキャリア基板の上記プリコートはんだ層に仮固定するとともに加圧固定治具から外力を加えることにより上記突部を上記セラミックキャリア基板の表面と接触させる工程と、上記段差付リッドを上記プリコートはんだ層に仮固定した上記セラミックキャリア基板をリフロー炉に投入して、上記段差付リッドと上記セラミックキャリア基板とをはんだ接合する工程との各工程を備え、上記各工程を順に行うことを特徴とする回路モジュールの製造方法。
A method of manufacturing a circuit module according to claim 1,
Said providing the ceramic substrate pads, a step of preparing the ceramic carrier substrate for mounting the electronic component, on the ceramic substrate pads, forming a solder paste layer, the solder on the ceramic substrate pads the ceramic carrier substrate which paste layer is formed is heated, after melting the solder paste layer to form a pre-coat the solder layer is cooled and solidified, a lid with the step in the pre-coat the solder layer of the ceramic carrier substrate Temporarily fixing and applying external force from a pressure fixing jig to bring the protrusion into contact with the surface of the ceramic carrier substrate; and reflowing the ceramic carrier substrate in which the stepped lid is temporarily fixed to the precoat solder layer Put into the furnace, the stepped lid and the ceramic Comprising the steps of a process of bonding solder and Yaria substrate, method of manufacturing a circuit module and performing the steps in order.
段差付リッドをプリコートはんだ層に接触させたセラミックキャリア基板を、はんだの融点よりも低く、且つ加重ではんだが軟化する温度に加熱し、上記プリコートはんだ層に上記段差付リッドを仮接合する工程を、上記段差付リッドを上記セラミックキャリア基板の上記プリコートはんだ層に仮固定する工程の直前に追加して設けたことを特徴とする請求項3に記載の回路モジュールの製造方法。 The step of temporarily bonding the stepped lid to the precoated solder layer by heating the ceramic carrier substrate with the stepped lid in contact with the precoated solder layer to a temperature lower than the melting point of the solder and a temperature at which the solder softens under load. 4. The method of manufacturing a circuit module according to claim 3, wherein the stepped lid is additionally provided immediately before the step of temporarily fixing the lid with the step to the precoat solder layer of the ceramic carrier substrate. 請求項2記載の回路モジュールの製造方法であって、
上記セラミック基板パッドを設けた、上記電子部品を搭載するための上記セラミックキャリア基板を調製する工程と、上記セラミック基板パッド上に、未硬化状態の上記導電性樹脂層を形成する工程と、上記導電性樹脂層が形成された上記セラミックキャリア基板を加熱し、上記導電性樹脂を半硬化状態にして、固形のプリコート導電性樹脂層を形成する工程と、上記段差付リッドと上記プリコート導電性樹脂層が設けられた上記セラミックキャリア基板とを加熱機構付きのマウンターに取り付け、上記加熱機構付きのマウンターで、上記段差付リッドを上記プリコート導電性樹脂層に接触させ、上記段差付リッドと上記プリコート導電性樹脂層が形成された上記セラミックキャリア基板とを加熱し、上記突部を上記セラミックキャリア基板に接触させた後に上記プリコート導電性樹脂層を加熱硬化させ、上記段差付リッドを上記セラミックキャリア基板に接着接合する工程との各工程を備え、上記各工程を順に行うことを特徴とする回路モジュールの製造方法。
A method of manufacturing a circuit module according to claim 2,
It said providing the ceramic substrate pads, a step of preparing the ceramic carrier substrate for mounting the electronic component, on the ceramic substrate pads, and forming the conductive resin layer in an uncured state, the conductive heating the ceramic carrier substrate sexual resin layer is formed, and the conductive resin to a semi-cured state, and forming a pre-coat the conductive resin layer of the solid, the lid and the pre-coating a conductive resin layer with the stepped The ceramic carrier substrate provided with a heating mechanism is attached to a mounter with a heating mechanism, the stepped lid is brought into contact with the precoat conductive resin layer with the mounter with a heating mechanism, and the stepped lid and the precoat conductive property are contacted . The ceramic carrier substrate on which the resin layer is formed is heated, and the protrusion is formed on the ceramic carrier substrate. The precoating conductive resin layer after contacting cured by heating, the lid with the step comprises the steps of a process of adhesively bonded to the ceramic carrier substrate, the circuit module and performing the steps in the order Production method.
上記段差付リッドと上記プリコート導電性樹脂層が設けられた上記セラミックキャリア基板とを上記加熱機構付きのマウンターに取り付け、上記加熱機構付きのマウンターで、上記段差付リッドを上記プリコート導電性樹脂層に接触させるとともに上記突部を上記セラミックキャリア基板に接触させた後の工程が、上記加熱機構付きマウンターにより、上記段差付リッドのみを加熱し、上記段差付リッドを上記セラミックキャリア基板に仮接着する工程と、上記セラミックキャリア基板に仮接着された上記段差付リッドを、上記セラミックキャリア基板に仮固定して、上記段差付リッドが仮固定された上記セラミックキャリア基板を加熱乾燥炉中で高温に保持し、上記プリコート導電性樹脂層を硬化させて、上記段差付リッドを上記セラミックキャリア基板に本接着する工程とであることを特徴とする請求項5に記載の回路モジュールの製造方法。 And the ceramic carrier board lid and the pre-coating a conductive resin layer with the step is provided attached to the mounter with the heating mechanism, with mounter with the heating mechanism, the lid with the step in the pre-coating a conductive resin layer step after the Rutotomoni the projection is contacted was brought into contact with the ceramic carrier substrate, by the heating mechanism with mounter, heating only the lid with the step, temporarily bonding the lid with the step on the ceramic carrier substrate The step and the stepped lid temporarily bonded to the ceramic carrier substrate are temporarily fixed to the ceramic carrier substrate, and the ceramic carrier substrate to which the stepped lid is temporarily fixed is held at a high temperature in a heating and drying furnace. Then, the precoat conductive resin layer is cured, and the stepped lid is bonded to the ceramic. Method of manufacturing a circuit module according to claim 5, characterized in that in the step of the bonding the carrier substrate.
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109132A (en) * 2008-10-30 2010-05-13 Yamaha Corp Thermoelectric module package and method of manufacturing the same
JP5368377B2 (en) * 2010-06-02 2013-12-18 三菱電機株式会社 Electronic component package and manufacturing method thereof
JP5568416B2 (en) * 2010-08-31 2014-08-06 京セラクリスタルデバイス株式会社 Manufacturing method of electronic device
US8822844B1 (en) * 2010-09-27 2014-09-02 Rockwell Collins, Inc. Shielding and potting for electrical circuits
WO2012093509A1 (en) * 2011-01-07 2012-07-12 富士電機株式会社 Semiconductor device and method of manufacturing thereof
US8637981B2 (en) 2011-03-30 2014-01-28 International Rectifier Corporation Dual compartment semiconductor package with temperature sensor
US9105500B2 (en) 2012-07-13 2015-08-11 International Business Machines Corporation Non-hermetic sealed multi-chip module package
EP3050157A4 (en) * 2013-09-27 2017-07-26 Nokia Technologies Oy Transmission line structure and method of attaching transmission line structure to conductive body
JP6314731B2 (en) * 2014-08-01 2018-04-25 株式会社ソシオネクスト Semiconductor device and manufacturing method of semiconductor device
JP6499886B2 (en) 2015-03-11 2019-04-10 田中貴金属工業株式会社 Cap for sealing electronic parts
WO2016199634A1 (en) * 2015-06-10 2016-12-15 三菱電機株式会社 Semiconductor device, and method for manufacturing same
JP6810335B2 (en) * 2016-06-24 2021-01-06 富士通株式会社 Electronic component modules, manufacturing methods for electronic component modules, terminals and signal processing systems
JP2019096797A (en) * 2017-11-27 2019-06-20 三菱電機株式会社 Semiconductor device and power conversion apparatus
WO2022061682A1 (en) * 2020-09-25 2022-03-31 华为技术有限公司 Packaging structure, packaging method, electronic device and manufacturing method therefor

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62149155A (en) * 1985-09-02 1987-07-03 Hitachi Ltd Sealed electronic device
US4868639A (en) 1986-08-11 1989-09-19 Fujitsu Limited Semiconductor device having waveguide-coaxial line transformation structure
JP3114403B2 (en) * 1992-12-22 2000-12-04 富士電機株式会社 Semiconductor pressure sensor
JP3227031B2 (en) 1993-06-14 2001-11-12 富士通株式会社 Email processing system
US5715144A (en) * 1994-12-30 1998-02-03 International Business Machines Corporation Multi-layer, multi-chip pyramid and circuit board structure
US5640746A (en) * 1995-08-15 1997-06-24 Motorola, Inc. Method of hermetically encapsulating a crystal oscillator using a thermoplastic shell
JP3652102B2 (en) * 1998-02-27 2005-05-25 京セラ株式会社 Electronic circuit module
JP2001068576A (en) 1999-08-30 2001-03-16 Sharp Corp Hermetically sealed semiconductor device
US6504723B1 (en) * 2001-11-15 2003-01-07 Intel Corporation Electronic assembly having solder thermal interface between a die substrate and a heat spreader
US6953985B2 (en) 2002-06-12 2005-10-11 Freescale Semiconductor, Inc. Wafer level MEMS packaging
JP2004031787A (en) * 2002-06-27 2004-01-29 Toyo Commun Equip Co Ltd Surface mount type electronic device
JP2004064013A (en) * 2002-07-31 2004-02-26 Kinseki Ltd Cap sealing method of package for electronic component
US6747350B1 (en) * 2003-06-06 2004-06-08 Silicon Integrated Systems Corp. Flip chip package structure
US6953891B2 (en) * 2003-09-16 2005-10-11 Micron Technology, Inc. Moisture-resistant electronic device package and methods of assembly
JP2005223641A (en) * 2004-02-05 2005-08-18 Toyo Commun Equip Co Ltd Surface mounting saw device
US7576427B2 (en) * 2004-05-28 2009-08-18 Stellar Micro Devices Cold weld hermetic MEMS package and method of manufacture
CN100477513C (en) * 2004-06-28 2009-04-08 京瓷株式会社 Method for manufacturing surface acoustic wave device, and wireless communication equipment

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