JP4838976B2 - Mosfet半導体装置の形成方法 - Google Patents
Mosfet半導体装置の形成方法 Download PDFInfo
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- JP4838976B2 JP4838976B2 JP2003334487A JP2003334487A JP4838976B2 JP 4838976 B2 JP4838976 B2 JP 4838976B2 JP 2003334487 A JP2003334487 A JP 2003334487A JP 2003334487 A JP2003334487 A JP 2003334487A JP 4838976 B2 JP4838976 B2 JP 4838976B2
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- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000000034 method Methods 0.000 title claims description 10
- 239000000463 material Substances 0.000 claims description 29
- 230000000873 masking effect Effects 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Claims (1)
- MOSFET半導体装置の形成方法であって、
n+基板を設けるステップと、
ドーピングされていない第1エピタキシャル層を蒸着し、ゲート領域の下方の領域がn−となるようにマスキングしてn型材料が注入され、ソース領域の下方の領域がp−となるようにマスキングしてp型材料が注入され、n−及びp−ドーピングされた第1ウエルを前記基板上に形成するステップと、
ドーピングされていない第2エピタキシャル層を蒸着し、ゲート領域の下方の領域がn−となるようにマスキングしてn型材料が注入され、ソース領域の下方の領域がp−となるようにマスキングしてp型材料が注入され、n−及びp−ドーピングされた第2ウエルを前記第1ウエル上に形成するステップと、
n型にドーピングされた第3エピタキシャル層を蒸着し、ソース領域の下方の領域がp−となるようにマスキングしてp型材料が注入され、n−及びp−ドーピングされた第3ウエルを前記第2ウエル上に形成するステップと、
前記第3ウエルのうちp型材料が注入された領域の上方であり、ソース領域の周囲の領域がp+となるようにマスキングしてp型材料が注入され、p+ドーピングされたp+領域を形成するステップと、
前記p+領域によって囲まれる領域がn+となるようにマスキングしてn型材料が注入され、n+ドーピングされたソース領域を形成するステップと、
ゲート領域の下方の前記第3ウエルの上方にゲート酸化膜を形成するステップと、
前記ゲート酸化膜上にゲート電極を形成し、ソース領域にソース電極を形成し、前記n+基板にドレイン電極を形成して、該MOSFET半導体装置の形成を完了するステップと、
を含むことを特徴とするMOSFET半導体装置の形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/260,611 | 2002-09-27 | ||
US10/260,611 US6825513B2 (en) | 2002-09-27 | 2002-09-27 | High power mosfet semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004119982A JP2004119982A (ja) | 2004-04-15 |
JP4838976B2 true JP4838976B2 (ja) | 2011-12-14 |
Family
ID=32029729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003334487A Expired - Fee Related JP4838976B2 (ja) | 2002-09-27 | 2003-09-26 | Mosfet半導体装置の形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6825513B2 (ja) |
JP (1) | JP4838976B2 (ja) |
BR (1) | BR0304243A (ja) |
CA (1) | CA2441912C (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10346838A1 (de) * | 2002-10-08 | 2004-05-13 | International Rectifier Corp., El Segundo | Superjunction-Bauteil |
US7126186B2 (en) * | 2002-12-20 | 2006-10-24 | Infineon Technolgies Ag | Compensation component and process for producing the component |
CN100518435C (zh) * | 2005-04-23 | 2009-07-22 | 鸿富锦精密工业(深圳)有限公司 | 具有改良焊盘的印刷电路板 |
US20060255401A1 (en) * | 2005-05-11 | 2006-11-16 | Yang Robert K | Increasing breakdown voltage in semiconductor devices with vertical series capacitive structures |
US20070012983A1 (en) * | 2005-07-15 | 2007-01-18 | Yang Robert K | Terminations for semiconductor devices with floating vertical series capacitive structures |
DE102006061994B4 (de) * | 2006-12-21 | 2011-05-05 | Infineon Technologies Austria Ag | Ladungskompensationsbauelement mit einer Driftstrecke zwischen zwei Elektroden und Verfahren zur Herstellung desselben |
US20090057713A1 (en) * | 2007-08-31 | 2009-03-05 | Infineon Technologies Austria Ag | Semiconductor device with a semiconductor body |
US20120126341A1 (en) * | 2010-11-23 | 2012-05-24 | Microchip Technology Incorporated | Using low pressure epi to enable low rdson fet |
US9583578B2 (en) * | 2013-01-31 | 2017-02-28 | Infineon Technologies Ag | Semiconductor device including an edge area and method of manufacturing a semiconductor device |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2089119A (en) * | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
CN1019720B (zh) * | 1991-03-19 | 1992-12-30 | 电子科技大学 | 半导体功率器件 |
DE4309764C2 (de) * | 1993-03-25 | 1997-01-30 | Siemens Ag | Leistungs-MOSFET |
JP3988262B2 (ja) * | 1998-07-24 | 2007-10-10 | 富士電機デバイステクノロジー株式会社 | 縦型超接合半導体素子およびその製造方法 |
JP3799888B2 (ja) * | 1998-11-12 | 2006-07-19 | 富士電機デバイステクノロジー株式会社 | 超接合半導体素子およびその製造方法 |
JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
US6475864B1 (en) * | 1999-10-21 | 2002-11-05 | Fuji Electric Co., Ltd. | Method of manufacturing a super-junction semiconductor device with an conductivity type layer |
JP3636345B2 (ja) * | 2000-03-17 | 2005-04-06 | 富士電機デバイステクノロジー株式会社 | 半導体素子および半導体素子の製造方法 |
JP2002170955A (ja) * | 2000-09-25 | 2002-06-14 | Toshiba Corp | 半導体装置およびその製造方法 |
-
2002
- 2002-09-27 US US10/260,611 patent/US6825513B2/en not_active Expired - Fee Related
-
2003
- 2003-09-19 CA CA002441912A patent/CA2441912C/en not_active Expired - Fee Related
- 2003-09-25 BR BR0304243-0A patent/BR0304243A/pt not_active Application Discontinuation
- 2003-09-26 JP JP2003334487A patent/JP4838976B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6825513B2 (en) | 2004-11-30 |
BR0304243A (pt) | 2004-09-08 |
US20040061182A1 (en) | 2004-04-01 |
CA2441912A1 (en) | 2004-03-27 |
CA2441912C (en) | 2008-11-18 |
JP2004119982A (ja) | 2004-04-15 |
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