JP4829792B2 - 電子デバイス及びこれを製造する方法 - Google Patents
電子デバイス及びこれを製造する方法 Download PDFInfo
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- JP4829792B2 JP4829792B2 JP2006534156A JP2006534156A JP4829792B2 JP 4829792 B2 JP4829792 B2 JP 4829792B2 JP 2006534156 A JP2006534156 A JP 2006534156A JP 2006534156 A JP2006534156 A JP 2006534156A JP 4829792 B2 JP4829792 B2 JP 4829792B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 40
- 238000000034 method Methods 0.000 title claims description 34
- 239000010410 layer Substances 0.000 claims description 115
- 238000009792 diffusion process Methods 0.000 claims description 99
- 230000004888 barrier function Effects 0.000 claims description 97
- 239000004020 conductor Substances 0.000 claims description 92
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 34
- 239000011229 interlayer Substances 0.000 claims description 29
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 16
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 235000021419 vinegar Nutrition 0.000 claims 1
- 239000000052 vinegar Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 57
- 238000001020 plasma etching Methods 0.000 description 36
- 239000000463 material Substances 0.000 description 26
- 238000000206 photolithography Methods 0.000 description 11
- 230000009977 dual effect Effects 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 238000001035 drying Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000000075 oxide glass Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
- H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (14)
- 半導体基板上に形成された層間誘電体層と、
前記層間誘電体層内に形成され、該層間誘電体層の上面より下方に凹まされた上面を有する銅製下部電極と、
前記銅製下部電極の上面と直接接し、上面が前記層間誘電体層の前記上面と同一平面にある第1導電性拡散障壁と、
前記第1導電性拡散障壁の上面と直接接触する第2導電性拡散障壁と、
前記第2導電性拡散障壁の上面と直接接するMIM誘電体と、
前記MIM誘電体の上面と直接接する上部電極と
を備える電子デバイス。 - 前記第2導電性拡散障壁が、前記下部電極の少なくとも2つの側部を超えて前記層間誘電体層の前記上面の一部にまで延び、前記MIM誘電体が、前記下部電極の少なくとも2つの側部を超えて延びる、請求項1に記載の電子デバイス。
- 前記上部電極が、前記下部電極の少なくとも2つの側部を超えて延びる、請求項1又は請求項2に記載の電子デバイス。
- 前記第1及び第2導電性拡散障壁は、5nmから200nmまでの厚さのW、Ta、TaN、WN、TaSiN、Pt、IrO2、又はRuO2、或いはそれらの組み合わせを含む、請求項1に記載の電子デバイス。
- 前記MIM誘電体は、2nmから20nmまでの厚さのSiO2、Si3N4又はSiC、Ta2O5、BaTiO3、HfO2、ZrO2又はAl2O3、或いはこれらの組み合わせ含む、請求項1に記載の電子デバイス。
- 前記上部電極は、前記MIM誘電体に直接接する下部導体、該下部導体に直接接するコア導体及び該コア導体に直接接する上部導体を有する、請求項1に記載の電子デバイス。
- 前記下部導体及び前記上部導体は、TiN又はTaNを含み、前記コア導体は、Al又はWを含む、請求項6に記載の電子デバイス。
- 電子デバイスを製造する方法であって、
(a)半導体基板を準備するステップと、
(b)前記半導体基板上に第1層間誘電体層を形成するステップと、
(c)前記第1層間誘電体層内に、該第1層間誘電体層の上面より下方に凹まされた上面を有する銅製下部電極を形成するステップと、
(d)前記銅製下部電極の上面と直接接し、上面が前記第1層間誘電体層の前記上面と同一平面にある第1導電性拡散障壁を前記第1層間誘電体層に形成するステップと、
(e)前記第1導電性拡散障壁の上面と直接接触する第2導電性拡散障壁を形成するステップと、
(f)前記第2導電性拡散障壁の前記上面と直接接するようにMIM誘電体を形成するステップと、
(g)前記MIM誘電体の上面と直接接するように上部電極を形成するステップとを含む方法。 - ステップ(g)の後に、
(h)少なくとも前記上部電極及び前記第1層間誘電体層の全ての露出された面の上に、反応性イオン・エッチング停止層を付着させるステップと、
(i)前記反応性イオン・エッチング停止層に直接接するように、第2層間誘電体層を形成するステップと、
(j)前記上部電極を露出するビアを前記第2層間誘電体層に形成するステップと、
(k)前記ビア内に導体を形成するステップとをさらに含む、請求項8に記載の方法。 - 前記第2導電性拡散障壁が、前記下部電極の少なくとも2つの側部を超えて前記層間誘電体層の前記上面の一部にまで延び、前記MIM誘電体が、前記下部電極の少なくとも2つの側部を超えて延びる、請求項8に記載の方法。
- 前記上部電極が、前記下部電極の少なくとも2つの側部を超えて延びる、請求項10に記載の方法。
- 前記第1及び第2導電性拡散障壁は、5nmから200nmまでの厚さのW、Ta、TaN、WN、TaSiN、Pt、IrO 2 、又はRuO 2 、或いはそれらの組み合わせを含む、請求項8に記載の方法。
- 前記MIM誘電体は、2nmから20nmまでの厚さのSiO 2 、Si 3 N 4 又はSiC、Ta 2 O 5 、BaTiO 3 、HfO 2 、ZrO 2 又はAl 2 O 3 、或いはこれらの組み合わせ含む、請求項8に記載の方法。
- 前記上部電極は、前記MIM誘電体に直接接する下部導体、該下部導体に直接接するコア導体及び該コア導体に直接接する上部導体を有する、請求項8に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/605,444 | 2003-09-30 | ||
US10/605,444 US6876028B1 (en) | 2003-09-30 | 2003-09-30 | Metal-insulator-metal capacitor and method of fabrication |
PCT/US2004/032405 WO2005034201A2 (en) | 2003-09-30 | 2004-09-30 | Metal-insulator-metal capacitor and method of fabrication |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007521661A JP2007521661A (ja) | 2007-08-02 |
JP2007521661A5 JP2007521661A5 (ja) | 2007-11-08 |
JP4829792B2 true JP4829792B2 (ja) | 2011-12-07 |
Family
ID=34375679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006534156A Expired - Fee Related JP4829792B2 (ja) | 2003-09-30 | 2004-09-30 | 電子デバイス及びこれを製造する方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US6876028B1 (ja) |
EP (1) | EP1671358A4 (ja) |
JP (1) | JP4829792B2 (ja) |
KR (1) | KR100861855B1 (ja) |
CN (1) | CN100568507C (ja) |
WO (1) | WO2005034201A2 (ja) |
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2004
- 2004-09-30 WO PCT/US2004/032405 patent/WO2005034201A2/en active Application Filing
- 2004-09-30 KR KR1020067005670A patent/KR100861855B1/ko not_active IP Right Cessation
- 2004-09-30 EP EP04789450A patent/EP1671358A4/en not_active Withdrawn
- 2004-09-30 CN CNB2004800282572A patent/CN100568507C/zh active Active
- 2004-09-30 JP JP2006534156A patent/JP4829792B2/ja not_active Expired - Fee Related
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2005
- 2005-01-03 US US11/028,425 patent/US20050156278A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
WO2005034201A2 (en) | 2005-04-14 |
CN100568507C (zh) | 2009-12-09 |
EP1671358A2 (en) | 2006-06-21 |
JP2007521661A (ja) | 2007-08-02 |
EP1671358A4 (en) | 2009-10-21 |
US20050067701A1 (en) | 2005-03-31 |
WO2005034201A3 (en) | 2007-12-06 |
US20050156278A1 (en) | 2005-07-21 |
CN101160661A (zh) | 2008-04-09 |
KR20060093698A (ko) | 2006-08-25 |
US6876028B1 (en) | 2005-04-05 |
KR100861855B1 (ko) | 2008-10-07 |
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