JP4818342B2 - Frequency error estimation device - Google Patents

Frequency error estimation device Download PDF

Info

Publication number
JP4818342B2
JP4818342B2 JP2008273947A JP2008273947A JP4818342B2 JP 4818342 B2 JP4818342 B2 JP 4818342B2 JP 2008273947 A JP2008273947 A JP 2008273947A JP 2008273947 A JP2008273947 A JP 2008273947A JP 4818342 B2 JP4818342 B2 JP 4818342B2
Authority
JP
Japan
Prior art keywords
frequency error
circuit
error detection
value
smoothing filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008273947A
Other languages
Japanese (ja)
Other versions
JP2010103800A (en
Inventor
阿部　　順一
史洋 山下
聖 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2008273947A priority Critical patent/JP4818342B2/en
Publication of JP2010103800A publication Critical patent/JP2010103800A/en
Application granted granted Critical
Publication of JP4818342B2 publication Critical patent/JP4818342B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

本発明は、無線通信などのディジタル通信システムにおいて、受信信号に含まれる周波数誤差による受信信号特性の劣化を防ぐため、周波数誤差補償に用いる周波数誤差値を高精度に推定する周波数誤差推定装置に関するものである。   The present invention relates to a frequency error estimation apparatus for accurately estimating a frequency error value used for frequency error compensation in a digital communication system such as radio communication in order to prevent deterioration of received signal characteristics due to a frequency error included in the received signal. It is.

図４は、受信信号に含まれる周波数誤差を推定する従来の周波数誤差推定装置の構成である（非特許文献１参照）。図４によると、周波数誤差推定装置は、Ｎシンボル遅延回路３１と、位相回転量検出回路３２と、平滑化フィルタ３３を備える。   FIG. 4 shows a configuration of a conventional frequency error estimation apparatus that estimates a frequency error included in a received signal (see Non-Patent Document 1). According to FIG. 4, the frequency error estimation apparatus includes an N symbol delay circuit 31, a phase rotation amount detection circuit 32, and a smoothing filter 33.

続いて、上記周波数誤差推定装置における信号の流れについて説明する。該周波数誤差推定装置には、受信信号からＱＰＳＫなどの変調成分を除去した無変調信号を入力する。位相回転量検出回路３２は、該周波数誤差推定装置の入力信号と、前記入力信号をＮシンボル遅延回路３１でＮシンボル遅延させた信号に基づき、Ｎシンボルあたりの位相回転量を出力する。平滑化フィルタ３３は、位相回転量検出回路３２の出力であるＮシンボルあたりの位相回転量に基づき、１シンボルあたりの位相回転量、すなわち周波数誤差推定値を出力する。   Next, a signal flow in the frequency error estimation apparatus will be described. The frequency error estimation apparatus receives an unmodulated signal obtained by removing a modulation component such as QPSK from the received signal. The phase rotation amount detection circuit 32 outputs a phase rotation amount per N symbols based on the input signal of the frequency error estimation device and a signal obtained by delaying the input signal by N symbols by the N symbol delay circuit 31. The smoothing filter 33 outputs a phase rotation amount per symbol, that is, a frequency error estimated value, based on the phase rotation amount per N symbols that is the output of the phase rotation amount detection circuit 32.

図５は、図４の周波数誤差推定回路におけるＮシンボルあたりの位相回転量のベクトル表示である。受信信号にシンボルレートでの規格化周波数誤差Δｆが存在する場合、Ｎシンボル区間の位相回転量は２πＮΔｆである。このように、位相回転量はＮと周波数誤差に比例するので、位相回転量検出回路３２で位相回転量を検出し、平滑化フィルタ３３で雑音を平滑化して周波数誤差出力を得る。雑音の影響を考慮すると、周波数誤差出力は２π（ＮΔｆ）＋ｅと表せる（ただし、ｅは雑音成分）。Ｎを大きく設定すると周波数誤差に比例した成分のみ増加するので、相対的に雑音の影響が小さくなり、周波数誤差推定精度が向上する利点がある。しかしながら、Ｎを大きく設定すると推定できる周波数誤差の範囲が狭まる問題がある。   FIG. 5 is a vector representation of the amount of phase rotation per N symbols in the frequency error estimation circuit of FIG. When the normalized frequency error Δf at the symbol rate exists in the received signal, the amount of phase rotation in the N symbol period is 2πNΔf. Thus, since the phase rotation amount is proportional to N and the frequency error, the phase rotation amount detection circuit 32 detects the phase rotation amount, and the smoothing filter 33 smoothes the noise to obtain a frequency error output. Considering the influence of noise, the frequency error output can be expressed as 2π (NΔf) + e (where e is a noise component). If N is set to be large, only the component proportional to the frequency error increases, so that there is an advantage that the influence of noise is relatively reduced and the frequency error estimation accuracy is improved. However, there is a problem that the range of frequency error that can be estimated when N is set large is narrowed.

図６は、図４の周波数誤差推定回路において、Ｎを大きく設定し、推定できる周波数誤差の範囲が狭まり、正常に周波数誤差を検出出来ない場合を示している。２πＮΔｆ＞πのとき、実際に検出される位相回転量はマイナス方向に位相が回転した−２π（１−ＮΔｆ）と誤検出される。同様に２πＮΔｆ＜−πの場合も位相回転量を正確に検出できない。このため、検出可能な位相回転量は、−π≦２πＮΔｆ≦πとなり、推定可能な周波数誤差Δｆの範囲は、−１／（２Ｎ）≦Δｆ≦１／（２Ｎ）となる。すなわちＮに反比例して検出範囲は狭くなる。   FIG. 6 shows a case where N is set large in the frequency error estimation circuit of FIG. 4, the range of frequency errors that can be estimated is narrowed, and the frequency error cannot be detected normally. When 2πNΔf> π, the actually detected amount of phase rotation is erroneously detected as −2π (1-NΔf) with the phase rotated in the minus direction. Similarly, the phase rotation amount cannot be accurately detected when 2πNΔf <−π. Therefore, the detectable phase rotation amount is −π ≦ 2πNΔf ≦ π, and the range of the frequency error Δf that can be estimated is −1 / (2N) ≦ Δf ≦ 1 / (2N). That is, the detection range becomes narrower in inverse proportion to N.

図７は、図４のＮの値が異なる２つの周波数誤差推定回路を組み合わせ、周波数誤差推定範囲を狭めることなく、高精度な周波数誤差の推定を実現する周波数誤差推定装置である（特許文献１）。該周波数誤差推定装置は、Ｎ＝ｍ（ｍは自然数）である第１の周波数誤差推定回路と、Ｎ＝ｎ（ｎは自然数）かつｍ＜ｎである第２の周波数誤差推定回路、及び第１の周波数誤差推定回路の出力と第２の周波数誤差推定回路の出力に基づき、高精度な周波数誤差推定値を出力する、周波数誤差推定値補正回路を備える。   FIG. 7 shows a frequency error estimation device that combines two frequency error estimation circuits having different values of N in FIG. 4 to realize highly accurate frequency error estimation without narrowing the frequency error estimation range (Patent Document 1). ). The frequency error estimation device includes a first frequency error estimation circuit in which N = m (m is a natural number), a second frequency error estimation circuit in which N = n (n is a natural number) and m <n, and A frequency error estimated value correcting circuit is provided that outputs a highly accurate frequency error estimated value based on the output of the first frequency error estimating circuit and the output of the second frequency error estimating circuit.

第１の周波数誤差推定回路は、ｍシンボル遅延回路４１と、位相回転量検出回路４２と、平滑化フィルタ４３を備える。第２の周波数誤差推定回路は、ｎシンボル遅延回路４４と、位相回転量検出回路４５と、平滑化フィルタ４６を備える。周波数誤差推定値補正回路は、乗算回路４７、４９、及び５１と、加算回路４８、及び５２と、丸め回路５０を備える。   The first frequency error estimation circuit includes an m symbol delay circuit 41, a phase rotation amount detection circuit 42, and a smoothing filter 43. The second frequency error estimation circuit includes an n symbol delay circuit 44, a phase rotation amount detection circuit 45, and a smoothing filter 46. The frequency error estimated value correction circuit includes multiplier circuits 47, 49, and 51, adder circuits 48 and 52, and a rounding circuit 50.

続いて、上記周波数誤差推定装置における信号の流れについて説明する。該周波数誤差推定装置に、受信信号から変調成分を除去した無変調信号を入力する。位相回転量検出回路４２は、該周波数誤差推定装置の入力信号と、前記入力信号をｍシンボル遅延回路４１でｍシンボル遅延させた信号に基づき、ｍシンボルあたりの位相回転量を出力する。平滑化フィルタ４３は、位相回転量検出回路４２の出力の帯域制限をし、雑音の影響を低減する。位相回転量検出回路４５は、該周波数誤差推定装置の入力信号と、前記入力信号をｎシンボル遅延回路４４でｎシンボル遅延させた信号に基づき、ｎシンボルあたりの位相回転量を出力する。平滑化フィルタ４６は、位相回転量検出回路４５の出力の帯域制限をし、雑音の影響を低減する。乗算回路４７は、平滑化フィルタ４３の出力をｎ／ｍ倍しｎシンボル分の位相回転量に相当する値を出力する。加算回路４８は、乗算回路４７の出力と平滑化フィルタ４６の出力の差分をとり、平滑化フィルタ４６の出力における、本来のｍシンボル分の位相回転量からの不足分を出力する。乗算回路４９、丸め回路５０、及び乗算回路５１は、加算回路４８の出力が本来２πの整数倍であることを利用し、加算回路４８の出力に含まれる雑音等の影響を除去する。加算回路５２は、平滑化フィルタ４６の出力に乗算回路５１の出力を加えて、本来のｎシンボル分の位相回転量を出力する。乗算回路５３は、加算回路５２の出力を１／（２π×ｎ）で乗算し、１シンボルあたりの位相回転量、すなわち周波数誤差推定値を出力する。   Next, a signal flow in the frequency error estimation apparatus will be described. An unmodulated signal obtained by removing the modulation component from the received signal is input to the frequency error estimating apparatus. The phase rotation amount detection circuit 42 outputs a phase rotation amount per m symbols based on an input signal of the frequency error estimation device and a signal obtained by delaying the input signal by m symbols by the m symbol delay circuit 41. The smoothing filter 43 limits the band of the output of the phase rotation amount detection circuit 42 and reduces the influence of noise. The phase rotation amount detection circuit 45 outputs a phase rotation amount per n symbols based on an input signal of the frequency error estimation device and a signal obtained by delaying the input signal by n symbols delay circuit 44 by n symbols. The smoothing filter 46 limits the band of the output of the phase rotation amount detection circuit 45 to reduce the influence of noise. The multiplication circuit 47 multiplies the output of the smoothing filter 43 by n / m and outputs a value corresponding to the phase rotation amount for n symbols. The adder circuit 48 takes the difference between the output of the multiplier circuit 47 and the output of the smoothing filter 46 and outputs a deficiency from the original m-symbol phase rotation amount in the output of the smoothing filter 46. The multiplier circuit 49, the rounding circuit 50, and the multiplier circuit 51 use the fact that the output of the adder circuit 48 is originally an integer multiple of 2π to remove the influence of noise and the like included in the output of the adder circuit 48. The adder circuit 52 adds the output of the multiplier circuit 51 to the output of the smoothing filter 46, and outputs the original phase rotation amount for n symbols. The multiplier circuit 53 multiplies the output of the adder circuit 52 by 1 / (2π × n), and outputs a phase rotation amount per symbol, that is, a frequency error estimated value.

ｍ＜ｎなので、第２の周波数誤差推定回路は、第１の周波数誤差推定回路よりも高精度な周波数誤差推定が可能であるが、推定周波数範囲が狭い。受信信号に第２の周波数誤差推定回路の推定可能範囲外となる周波数誤差が存在する場合、第２の周波数誤差推定回路が検出するｎシンボル分の位相回転量ｙは、本来検出すべき位相回転量とは異なる。これは、本来の位相回転量は２πｋ＋ｙ（ｋは整数）であるが、第２の周波数誤差推定回路は、位相回転量２πｋを検出できないためである。   Since m <n, the second frequency error estimation circuit can estimate the frequency error with higher accuracy than the first frequency error estimation circuit, but the estimated frequency range is narrow. When the received signal contains a frequency error that is outside the estimable range of the second frequency error estimation circuit, the phase rotation amount y for n symbols detected by the second frequency error estimation circuit is the phase rotation that should be detected originally. It is different from the amount. This is because the original phase rotation amount is 2πk + y (k is an integer), but the second frequency error estimation circuit cannot detect the phase rotation amount 2πk.

以上を考慮すると１シンボル分の位相回転量は、（ｙ＋２πｋ）／ｎである。ｋは不明なので、１シンボル分の位相回転量が定まらず、周波数誤差が推定できない。そこで、周波数誤差推定値補正回路では、推定対象の周波数誤差が推定可能範囲内にある第１の周波数誤差推定回路が検出するｍシンボル分の位相回転量ｘに基づき、ｋを決定する。ｘをｎ／ｍ倍した値はｎシンボル分の位相回転量に相当する。そのため、下記の式が成立する。   Considering the above, the phase rotation amount for one symbol is (y + 2πk) / n. Since k is unknown, the amount of phase rotation for one symbol cannot be determined, and the frequency error cannot be estimated. Therefore, the frequency error estimated value correcting circuit determines k based on the phase rotation amount x for m symbols detected by the first frequency error estimating circuit whose frequency error to be estimated is within the estimable range. A value obtained by multiplying x by n / m corresponds to a phase rotation amount for n symbols. Therefore, the following formula is established.

ｘ×ｎ／ｍ＝ｙ＋２πｋ
よって、ｋ＝（ｘ×ｎ／ｍ−ｙ）／２πとなるが、（ｘ×ｎ／ｍ−ｙ）／２πは雑音の影響で整数にならないため、ｋは（ｘ×ｎ／ｍ−ｙ）／２πに最も近い整数値とする。周波数誤差推定値補正回路は、ｋに基づきｙを補正するため、高精度な周波数誤差推定値を得る（特許文献１参照）。 x × n / m = y + 2πk
Therefore, k = (x × n / my) / 2π, but (x × n / my) / 2π does not become an integer due to the influence of noise, so k is (x × n / my). ) / 2 is the integer value closest to 2π. Since the frequency error estimated value correction circuit corrects y based on k, a highly accurate frequency error estimated value is obtained (see Patent Document 1).

特開２００４−２００９３９号公報Japanese Patent Laid-Open No. 2004-200939 H. Furukawa, K. Matsuyama, T. Sato, T. Takenaka and Y. Takeda, “Aπ/4-Shifted DQPSK Demodulator for a Personal Mobile Communications System”,IEEE PIMRC 92,pp.618-622H. Furukawa, K. Matsuyama, T. Sato, T. Takenaka and Y. Takeda, “Aπ / 4-Shifted DQPSK Demodulator for a Personal Mobile Communications System”, IEEE PIMRC 92, pp.618-622

図７の周波数誤差推定装置において、第２の周波数誤差推定回路で推定可能な周波数を超える周波数を推定するため、推定可能範囲が広い第１の周波数誤差推定回路の推定値を用いて、第２の周波数誤差推定値を補償する。しかしながら、平滑化フィルタ４３の出力を乗算回路４７でｎ／ｍ倍するため、平滑化フィルタ４３の出力が受けている雑音の影響を増大させている。このため、受信信号に含まれる雑音が増大するにつれ、丸め回路５０の出力に誤りが生じ、乗算回路５１の出力である平滑化フィルタ４６の出力に対する補正値が劣化する。この結果、装置の周波数誤差推定値が劣化する問題がある。   In the frequency error estimation apparatus of FIG. 7, in order to estimate a frequency exceeding the frequency that can be estimated by the second frequency error estimation circuit, the second frequency error estimation circuit uses the estimated value of the first frequency error estimation circuit that has a wide estimable range. To compensate for the frequency error estimate of. However, since the output of the smoothing filter 43 is multiplied by n / m by the multiplication circuit 47, the influence of noise received by the output of the smoothing filter 43 is increased. For this reason, as the noise included in the received signal increases, an error occurs in the output of the rounding circuit 50, and the correction value for the output of the smoothing filter 46, which is the output of the multiplication circuit 51, deteriorates. As a result, there is a problem that the estimated frequency error value of the apparatus deteriorates.

従って、本発明は雑音の影響によらず高精度な周波数誤差を推定できる周波数誤差装置を提供することを目的とする。   Therefore, an object of the present invention is to provide a frequency error device that can estimate a frequency error with high accuracy regardless of the influence of noise.

上記目的を実現するため本発明による周波数誤差推定装置は、周波数誤差検出範囲の広さが可変である周波数誤差検出回路と、前記周波数誤差検出回路の検出値を入力とし、平滑化処理し、周波数誤差推定値として出力する第１の平滑化フィルタ回路と、前記周波数誤差検出回路の周波数誤差検出範囲の広さ及び前記第１の平滑化フィルタ回路のフィルタ帯域幅を調整する調整回路とを備え、前記調整回路は、前記周波数誤差検出範囲に含まれる有効領域を設定し、前記周波数誤差検出値が前記有効領域内であるか否かの判定を行い、前記周波数誤差検出値が前記有効領域を超えたとき、前記有効領域の中心周波数を前記周波数誤差検出値に再設定し、前記周波数誤差検出値が前記有効領域内であり、かつ前記有効領域の再設定が所定の時間内に起きない場合、前記第１の平滑化フィルタ回路のフィルタ帯域幅を狭めるとともに、前記有効領域の中心周波数を前記周波数誤差検出値に再設定し、前記第１の平滑化フィルタ回路のフィルタ帯域幅が予め設定した下限値に達したとき、前記周波数誤差検出範囲の広さと前記有効領域とを狭めるとともに、前記第１の平滑化フィルタ回路のフィルタ帯域幅を初期化し、再び、前記周波数誤差検出値が前記有効領域内であるか否かの判定を行い、以降の処理を繰り返す。 In order to achieve the above object, a frequency error estimation device according to the present invention has a frequency error detection circuit with a variable frequency error detection range and a detection value of the frequency error detection circuit as inputs, and performs a smoothing process. A first smoothing filter circuit that outputs an error estimation value; and an adjustment circuit that adjusts a frequency error detection range of the frequency error detection circuit and a filter bandwidth of the first smoothing filter circuit; The adjustment circuit sets an effective region included in the frequency error detection range, determines whether the frequency error detection value is within the effective region, and the frequency error detection value exceeds the effective region. when in the center frequency of the effective area is reset to the frequency error detection value, wherein a frequency error detection value is the effective area, and the time re-setting is given the effective area If the not occur, along with narrowing the filter bandwidth prior Symbol first smoothing filter circuit, re-setting the center frequency of the effective region in the frequency error detection value, the filter band of the first smoothing filter circuit When the width reaches a preset lower limit value, the width of the frequency error detection range and the effective area are narrowed, the filter bandwidth of the first smoothing filter circuit is initialized, and the frequency error detection is performed again. It is determined whether or not the value is within the effective area, and the subsequent processing is repeated .

また、前記調整回路は、前記周波数誤差検出範囲の広さが予め設定した下限値に達した場合、前記周波数誤差検出範囲の広さ及び前記第１の平滑化フィルタ回路のフィルタ帯域幅を狭めることを停止することも好ましい。 The adjustment circuit narrows the width of the frequency error detection range and the filter bandwidth of the first smoothing filter circuit when the width of the frequency error detection range reaches a preset lower limit value. It is also preferable to stop the operation.

また、前記周波数誤差検出回路が、受信信号の特定の推定区間における位相回転量から周波数誤差を推定し、前記推定区間の長さを変更することで前記周波数誤差検出範囲の広さを可変とすることも好ましい。 Further, the frequency error detection circuit estimates a frequency error from a phase rotation amount in a specific estimation section of the received signal, and changes a length of the estimation section, thereby making the width of the frequency error detection range variable. It is also preferable.

また、受信信号を無変調化する回路と、前記無変調化された信号を平滑化する第２の平滑化フィルタ回路をさらに備え、前記周波数誤差検出回路が前記第２の平滑化フィルタ回路の出力に基づき周波数誤差を検出することも好ましい。   The circuit further includes a circuit that demodulates the received signal and a second smoothing filter circuit that smoothes the non-modulated signal, and the frequency error detection circuit outputs an output of the second smoothing filter circuit. It is also preferable to detect the frequency error based on the above.

本発明の周波数誤差推定装置は、周波数誤差推定値の収束状況により、周波数誤差推定範囲を順次切り替えるので、高精度かつ高速な周波数誤差の推定を実現する。精度の低い推定値により補正する必要がないので、雑音を増大させることなく高精度に周波数誤差を推定できる。また周波数誤差推定値がある程度収束したとき、平滑化フィルタ回路の通過帯域幅もあわせて段階的に狭めることで周波数誤差推定値の変動を低減させ、雑音の影響を一層低減させる。さらに収束状況は乗算回路などを必要としない簡易な回路で推定できるので、従来技術と比べ回路規模を簡素化できる。   The frequency error estimation apparatus of the present invention sequentially switches the frequency error estimation range according to the convergence state of the frequency error estimation value, thereby realizing high-precision and high-speed frequency error estimation. Since it is not necessary to correct the estimated value with low accuracy, the frequency error can be estimated with high accuracy without increasing noise. Further, when the frequency error estimated value converges to some extent, the passband width of the smoothing filter circuit is also narrowed in steps, thereby reducing the fluctuation of the frequency error estimated value and further reducing the influence of noise. Furthermore, since the convergence state can be estimated with a simple circuit that does not require a multiplication circuit or the like, the circuit scale can be simplified as compared with the prior art.

本発明を実施するための最良の実施形態について、以下では図面を用いて詳細に説明する。   The best mode for carrying out the present invention will be described in detail below with reference to the drawings.

次に、本発明の実施形態に関わる周波数誤差推定装置の構成図を図１に示す。図１によると、周波数誤差推定装置は、乗算回路１、可変発振回路２、無変調化回路３、平滑化フィルタ回路４、ｍシンボル遅延回路５、位相回転量検出回路６、帯域幅可変平滑化フィルタ回路７、調整回路１０を備える。帯域幅可変平滑化フィルタ回路７は、可変ループゲイン８、および積分回路９を備える。なお、ｍシンボル遅延回路５におけるｍの値（ｍは自然数）、および帯域幅可変平滑化フィルタ回路７における可変ループゲイン８の値は、調整回路１０の出力により変更できる。   Next, FIG. 1 shows a configuration diagram of the frequency error estimation apparatus according to the embodiment of the present invention. According to FIG. 1, the frequency error estimation device includes a multiplier circuit 1, a variable oscillation circuit 2, a non-modulation circuit 3, a smoothing filter circuit 4, an m symbol delay circuit 5, a phase rotation amount detection circuit 6, and a bandwidth variable smoothing. A filter circuit 7 and an adjustment circuit 10 are provided. The bandwidth variable smoothing filter circuit 7 includes a variable loop gain 8 and an integration circuit 9. Note that the value of m in the m symbol delay circuit 5 (m is a natural number) and the value of the variable loop gain 8 in the variable bandwidth smoothing filter circuit 7 can be changed by the output of the adjustment circuit 10.

続いて、上記周波数誤差推定装置における信号の流れについて説明する。該周波数誤差推定装置には、ベースバンドの受信信号を入力する。可変発振回路２は、積分回路９の出力である周波数誤差推定値に基づき、周波数誤差補償信号を出力する。乗算回路１は、ベースバンドの受信信号に含まれる周波数誤差を補償する。   Next, a signal flow in the frequency error estimation apparatus will be described. The frequency error estimation apparatus receives a baseband received signal. The variable oscillation circuit 2 outputs a frequency error compensation signal based on the estimated frequency error value output from the integration circuit 9. The multiplier circuit 1 compensates for a frequency error contained in the baseband received signal.

しかしながら、周波数誤差推定値が受信信号の周波数誤差値と一致しない場合、乗算回路１の出力には残留周波数誤差が含まれる。そこで当該装置は、残留周波数誤差を検出し、残留周波数誤差が０になるように周波数誤差推定値を更新する。   However, if the estimated frequency error value does not match the frequency error value of the received signal, the output of the multiplier circuit 1 includes a residual frequency error. Therefore, the apparatus detects the residual frequency error and updates the frequency error estimated value so that the residual frequency error becomes zero.

無変調化回路３は、乗算回路１の出力に含まれる既知パターンを検出し、受信回路１の出力に含まれる既知パターンと、無変調化回路内で生成された既知パターンを逆変調したものとを乗算することで、受信回路１の出力からＱＰＳＫなどの変調成分を除去し、無変調化する。平滑化フィルタ回路４は、調整回路１０の出力に基づき無変調化回路３の出力を平滑化した値を出力する。位相回転量検出回路６は、平滑化フィルタ回路４の出力と、同出力をｍシンボル遅延回路５でｍシンボル遅延させた信号に基づき、ｍシンボル間に残留周波数誤差により生じた位相回転量を算出する。積分回路９は、位相回転量検出回路６の出力を可変ループゲイン８で調整した値に基づき、逐次積分することで周波数誤差推定値を更新する。調整回路１０は、図２に示すフローチャートに基づき、ｍシンボル遅延回路５のｍの値を調整し、また可変ループゲイン８の値を調整する。   The non-modulation circuit 3 detects a known pattern included in the output of the multiplication circuit 1, and inversely modulates the known pattern included in the output of the reception circuit 1 and the known pattern generated in the non-modulation circuit. , The modulation component such as QPSK is removed from the output of the receiving circuit 1 to make no modulation. The smoothing filter circuit 4 outputs a value obtained by smoothing the output of the non-modulation circuit 3 based on the output of the adjustment circuit 10. The phase rotation amount detection circuit 6 calculates the amount of phase rotation caused by the residual frequency error between m symbols based on the output of the smoothing filter circuit 4 and a signal obtained by delaying the output by m symbol delay circuit 5 by m symbols. To do. The integrating circuit 9 updates the frequency error estimated value by successively integrating the output of the phase rotation amount detecting circuit 6 based on the value adjusted by the variable loop gain 8. The adjustment circuit 10 adjusts the value of m of the m symbol delay circuit 5 and adjusts the value of the variable loop gain 8 based on the flowchart shown in FIG.

調整回路１０は帯域幅可変平滑化フィルタ回路７の出力に基づき、ｍシンボル分の位相回転量検出回路１１のｍの値を逐次増大させることで、周波数誤差推定範囲と周波数誤差推定精度を変更できる。なお、回路の動作開始時はｍの値は最小とし、そのときの周波数誤差推定可能範囲に含まれる領域［−Ｂ，Ｂ］を有効領域とする。すなわち、Ｂは１／（２ｍ）より小さい値とする。   The adjustment circuit 10 can change the frequency error estimation range and the frequency error estimation accuracy by sequentially increasing the value of m of the phase rotation amount detection circuit 11 for m symbols based on the output of the variable bandwidth smoothing filter circuit 7. . Note that the value of m is minimized at the start of circuit operation, and the region [−B, B] included in the frequency error estimable range at that time is set as an effective region. That is, B is a value smaller than 1 / (2 m).

周波数誤差推定値が有効領域外の場合、有効領域の中心である中心周波数を当該周波数誤差推定値に設定する。よって、有効領域は［周波数誤差推定値−Ｂ，周波数誤差推定値＋Ｂ］となる。   When the frequency error estimated value is outside the effective region, the center frequency that is the center of the effective region is set as the frequency error estimated value. Therefore, the effective area is [frequency error estimated value−B, frequency error estimated value + B].

周波数誤差推定値が有効領域内であり、かつ予め設定された時間Ｔの間に有効領域の中心周波数が変更されなかった場合、可変ループゲイン８を減少させると共に、有効領域を［周波数誤差推定値−Ｂ，周波数誤差推定値＋Ｂ］に再設定する。可変ループゲイン８を減少させることは、閉ループのループ帯域が狭まるため、帯域幅可変平滑化フィルタ回路７の通過帯域幅が小さくなることと等価である。また、可変ループゲイン８の値が予め設定された下限値のとき、ｍを増加、Ｂを減少、可変ループゲイン８の値を初期化する。   When the frequency error estimated value is within the effective region and the center frequency of the effective region is not changed during the preset time T, the variable loop gain 8 is decreased and the effective region is set to [frequency error estimated value. -B, frequency error estimate + B]. Decreasing the variable loop gain 8 is equivalent to reducing the pass bandwidth of the variable bandwidth smoothing filter circuit 7 because the loop bandwidth of the closed loop is narrowed. Further, when the value of the variable loop gain 8 is a preset lower limit value, m is increased, B is decreased, and the value of the variable loop gain 8 is initialized.

ｍを増加することにより、周波数誤差推定範囲は狭まり、結果として周波数誤差推定精度が高まる。上記動作を繰り返し、ｍが予め設定された上限値に達した場合、調整回路１０はｍの値、および可変ループゲイン８の値の更新を停止する。   By increasing m, the frequency error estimation range is narrowed, and as a result, the frequency error estimation accuracy is increased. When the above operation is repeated and m reaches a preset upper limit value, the adjustment circuit 10 stops updating the value of m and the value of the variable loop gain 8.

図１の回路は、有効領域の変更頻度によって周波数誤差推定値の収束状況を判断している。すなわち、収束に近づくほど周波数誤差推定値の変化が小さくなるため、周波数誤差推定値が設定された有効領域内に留まる時間が長くなる。図２のフローチャートは、前記有効領域内に留まる時間を測定することで収束状況を判断し、周波数誤差推定値がある程度収束したとき、可変ループゲイン８の値を段階的に引き下げて周波数誤差推定値の変動を低減させ、雑音の影響を低減させる。このようにして得られた周波数誤差推定値は、雑音の影響が相当低減されているので、入力信号の周波数誤差の真値に近づく。従って図１の回路は、ｍの値を切り替えても、推定対象の周波数誤差が推定可能範囲外になることが防がれ、かつ図７のように複数の乗算回路が不要であるので、従来技術と比べ回路規模を簡素化することが可能である。   The circuit in FIG. 1 determines the convergence state of the frequency error estimated value based on the change frequency of the effective region. In other words, since the change in the frequency error estimated value becomes smaller as the convergence is approached, the time for staying in the effective region in which the frequency error estimated value is set becomes longer. The flow chart of FIG. 2 determines the convergence state by measuring the time remaining in the effective region, and when the frequency error estimated value has converged to some extent, the value of the variable loop gain 8 is lowered stepwise to estimate the frequency error estimated value. To reduce the influence of noise. The estimated frequency error value thus obtained approaches the true value of the frequency error of the input signal because the influence of noise is considerably reduced. Therefore, even if the value of m is switched, the circuit of FIG. 1 can prevent the estimation target frequency error from being outside the estimable range, and does not require a plurality of multiplication circuits as shown in FIG. Compared to technology, the circuit scale can be simplified.

図１のｍシンボル分の位相回転量検出回路１１は、図３に示すａシンボル分の位相回転量検出回路１２、ｂシンボル分の位相回転量検出回路１５、セレクタ１８を用いても良い。ａシンボル分の位相回転量検出回路１２はａシンボル遅延回路１３と位相回転量検出回路１４とから構成され、ｂシンボル分の位相回転量検出回路１５はｂシンボル遅延回路１６と位相回転量検出回路１７とから構成される。図３の構成は、図１におけるｍシンボル遅延回路５のｍの値を１回のみ切り替える場合に相当する。セレクタ１８は調整回路１０の出力に基づき、ａシンボル分の位相回転量検出回路１２とｂシンボル分の位相回転量検出回路１５のいずれかを選択し、出力する。   The phase rotation amount detection circuit 11 for m symbols in FIG. 1 may use the phase rotation amount detection circuit 12 for a symbols, the phase rotation amount detection circuit 15 for b symbols, and the selector 18 shown in FIG. The phase rotation amount detection circuit 12 for a symbol is composed of an a symbol delay circuit 13 and a phase rotation amount detection circuit 14, and the phase rotation amount detection circuit 15 for b symbols is a b symbol delay circuit 16 and a phase rotation amount detection circuit. 17. The configuration of FIG. 3 corresponds to a case where the value of m of the m symbol delay circuit 5 in FIG. 1 is switched only once. The selector 18 selects and outputs either the phase rotation amount detection circuit 12 for a symbols or the phase rotation amount detection circuit 15 for b symbols based on the output of the adjustment circuit 10.

以上のアルゴリズムにより、高速な初期引き込みと収束状態における雑音の低減が可能になる。   The above algorithm enables high-speed initial pull-in and noise reduction in the convergence state.

また、以上述べた実施形態は全て本発明を例示的に示すものであって限定的に示すものではなく、本発明は他の種々の変形態様および変更態様で実施することができる。従って本発明の範囲は特許請求の範囲およびその均等範囲によってのみ規定されるものである。   Moreover, all the embodiments described above are illustrative of the present invention and are not intended to limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

本発明による周波数誤差推定装置の構成図である。It is a block diagram of the frequency error estimation apparatus by this invention. 図１で示す調整回路１０における処理を示すフローチャートである。It is a flowchart which shows the process in the adjustment circuit 10 shown in FIG. 図１で示すｍシンボル分の位相回転量検出回路１１の別の形態である。It is another form of the phase rotation amount detection circuit 11 for m symbols shown in FIG. 従来の周波数誤差推定装置を示す図である。It is a figure which shows the conventional frequency error estimation apparatus. 図４で示す周波数誤差推定装置において検出できる位相回転量の範囲を示す図である。It is a figure which shows the range of the phase rotation amount which can be detected in the frequency error estimation apparatus shown in FIG. 図４で示す周波数誤差推定回路が位相回転量を誤検出する場合を示す図である。FIG. 5 is a diagram showing a case where the frequency error estimation circuit shown in FIG. 4 erroneously detects a phase rotation amount. 図４の誤検出を防いで高精度な周波数誤差の推定を行う従来の周波数誤差推定装置を示す図である。It is a figure which shows the conventional frequency error estimation apparatus which prevents the misdetection of FIG. 4 and estimates a frequency error with high precision.

符号の説明Explanation of symbols

１ 乗算回路
２ 可変発振回路
３ 無変調化回路
４ 平滑化フィルタ回路
５ ｍシンボル遅延回路
６ 位相回転量検出回路
７ 帯域幅可変平滑化フィルタ回路
８ 可変ループゲイン
９ 積分回路
１０ 調整回路
１１ ｍシンボル分の位相回転量検出回路
１２ ａシンボル分の位相回転量検出回路
１３ ａシンボル遅延回路
１４ 位相回転量検出回路
１５ ｂシンボル分の位相回転量検出回路
１６ ｂシンボル遅延回路
１７ 位相回転量検出回路
１８ セレクタ
３１ Ｎシンボル遅延回路
３２、４２、４５ 位相回転量検出回路
３３、４３、４６ 平滑化フィルタ
４１ ｍシンボル遅延回路
４４ ｎシンボル遅延回路
４７、４９、５１、５３ 乗算回路
４８、５２ 加算回路
５０ 丸め回路 DESCRIPTION OF SYMBOLS 1 Multiplication circuit 2 Variable oscillation circuit 3 Unmodulation circuit 4 Smoothing filter circuit 5 m symbol delay circuit 6 Phase rotation amount detection circuit 7 Bandwidth variable smoothing filter circuit 8 Variable loop gain 9 Integration circuit 10 Adjustment circuit 11 m symbols worth Phase rotation amount detection circuit 12 a symbol phase rotation amount detection circuit 13 a symbol delay circuit 14 phase rotation amount detection circuit 15 b symbol phase rotation amount detection circuit 16 b symbol delay circuit 17 phase rotation amount detection circuit 18 selector 31 N symbol delay circuit 32, 42, 45 Phase rotation amount detection circuit 33, 43, 46 Smoothing filter 41 m symbol delay circuit 44 n symbol delay circuit 47, 49, 51, 53 Multiplication circuit 48, 52 Addition circuit 50 Rounding circuit

Claims (4)

周波数誤差検出範囲の広さが可変である周波数誤差検出回路と、
前記周波数誤差検出回路の検出値を入力とし、平滑化処理し、周波数誤差推定値として出力する第１の平滑化フィルタ回路と、
前記周波数誤差検出回路の周波数誤差検出範囲の広さ及び前記第１の平滑化フィルタ回路のフィルタ帯域幅を調整する調整回路と、
を備え、
前記調整回路は、
前記周波数誤差検出範囲に含まれる有効領域を設定し、
前記周波数誤差検出値が前記有効領域内であるか否かの判定を行い、
前記周波数誤差検出値が前記有効領域を超えたとき、前記有効領域の中心周波数を前記周波数誤差検出値に再設定し、
前記周波数誤差検出値が前記有効領域内であり、かつ前記有効領域の再設定が所定の時間内に起きない場合、前記第１の平滑化フィルタ回路のフィルタ帯域幅を狭めるとともに、前記有効領域の中心周波数を前記周波数誤差検出値に再設定し、
前記第１の平滑化フィルタ回路のフィルタ帯域幅が予め設定した下限値に達したとき、前記周波数誤差検出範囲の広さと前記有効領域とを狭めるとともに、前記第１の平滑化フィルタ回路のフィルタ帯域幅を初期化し、
再び、前記周波数誤差検出値が前記有効領域内であるか否かの判定を行い、以降の処理を繰り返す
ことを特徴とする周波数誤差推定装置。 A frequency error detection circuit having a variable frequency error detection range;
A first smoothing filter circuit which receives a detection value of the frequency error detection circuit as input, performs a smoothing process, and outputs it as a frequency error estimation value;
An adjustment circuit for adjusting a frequency error detection range of the frequency error detection circuit and a filter bandwidth of the first smoothing filter circuit;
With
The adjustment circuit includes:
Set an effective area included in the frequency error detection range,
Determining whether the frequency error detection value is within the effective region;
When the frequency error detection value exceeds the effective area, the center frequency of the effective area is reset to the frequency error detection value,
Wherein a frequency error detection value is the effective area, and if the re-setting of the effective area does not occur within a predetermined time, with narrow the filter bandwidth prior Symbol first smoothing filter circuit, the effective area Reset the center frequency of the above to the frequency error detection value,
When the filter bandwidth of the first smoothing filter circuit reaches a preset lower limit value, the width of the frequency error detection range and the effective region are narrowed, and the filter band of the first smoothing filter circuit Initialize the width,
The frequency error estimation apparatus again determines whether or not the frequency error detection value is within the effective region, and repeats the subsequent processing . 前記調整回路は、
前記周波数誤差検出範囲の広さが予め設定した下限値に達した場合、前記周波数誤差検出範囲の広さ及び前記第１の平滑化フィルタ回路のフィルタ帯域幅を狭めることを停止することを特徴とする請求項１に記載の周波数誤差推定装置。 The adjustment circuit includes:
When the width of the frequency error detection range reaches a preset lower limit value, the narrowing of the width of the frequency error detection range and the filter bandwidth of the first smoothing filter circuit is stopped. The frequency error estimation apparatus according to claim 1. 前記周波数誤差検出回路が、
受信信号の特定の推定区間における位相回転量から周波数誤差を推定し、
前記推定区間の長さを変更することで前記周波数誤差検出範囲の広さを可変とすることを特徴とする請求項１または２に記載の周波数誤差推定装置。 The frequency error detection circuit is
Estimate the frequency error from the amount of phase rotation in a specific estimation section of the received signal,
The frequency error estimation apparatus according to claim 1 or 2, wherein a width of the frequency error detection range is made variable by changing a length of the estimation section. 受信信号を無変調化する回路と、前記無変調化された信号を平滑化する第２の平滑化フィルタ回路をさらに備え、前記周波数誤差検出回路が前記第２の平滑化フィルタ回路の出力に基づき周波数誤差を検出することを特徴とする請求項１から３のいずれか１項に記載の周波数誤差推定装置。   A circuit for demodulating the received signal; and a second smoothing filter circuit for smoothing the unmodulated signal, wherein the frequency error detection circuit is based on the output of the second smoothing filter circuit. The frequency error estimation device according to any one of claims 1 to 3, wherein a frequency error is detected.
JP2008273947A 2008-10-24 2008-10-24 Frequency error estimation device Expired - Fee Related JP4818342B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008273947A JP4818342B2 (en) 2008-10-24 2008-10-24 Frequency error estimation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008273947A JP4818342B2 (en) 2008-10-24 2008-10-24 Frequency error estimation device

Publications (2)

Publication Number Publication Date
JP2010103800A JP2010103800A (en) 2010-05-06
JP4818342B2 true JP4818342B2 (en) 2011-11-16

Family

ID=42294023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008273947A Expired - Fee Related JP4818342B2 (en) 2008-10-24 2008-10-24 Frequency error estimation device

Country Status (1)

Country Link
JP (1) JP4818342B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE519309T1 (en) * 2008-11-03 2011-08-15 Ericsson Telefon Ab L M ESTIMATION OF A FREQUENCY CONVERSION
JP6191416B2 (en) * 2013-11-28 2017-09-06 富士通株式会社 Frequency offset estimation circuit and frequency offset estimation method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3327152B2 (en) * 1996-12-25 2002-09-24 三菱電機株式会社 Automatic frequency control circuit
JP3488657B2 (en) * 1999-06-02 2004-01-19 日本無線株式会社 Frequency error detection device and automatic frequency control device
WO2000076165A1 (en) * 1999-06-09 2000-12-14 Mitsubishi Denki Kabushiki Kaisha Automatic frequency controller
JP3743629B2 (en) * 1999-11-12 2006-02-08 三菱電機株式会社 Wireless communication terminal that can accurately locate burst and has small frequency error of regenerated carrier wave
JP3888966B2 (en) * 2002-12-17 2007-03-07 日本電信電話株式会社 Automatic frequency control circuit
JP4681637B2 (en) * 2008-08-21 2011-05-11 日本電信電話株式会社 Frequency error estimation device

Also Published As

Publication number Publication date
JP2010103800A (en) 2010-05-06

Similar Documents

Publication Publication Date Title
RU2511719C2 (en) Carrier recovery circuit and demodulation circuit based on quasi-coherent detection method
JP4740905B2 (en) ADPLL frequency synthesizer
JP5213469B2 (en) Modulator and demodulator
US8509360B2 (en) Pulse radio receiver
US7620125B1 (en) Frequency estimation apparatus and related method
JP4279027B2 (en) OFDM demodulation method and semiconductor integrated circuit
JP5655251B2 (en) Phase error correction configuration and phase error correction method
WO2018034030A1 (en) Phase noise compensation device, demodulation device, communication device, communication system, and phase noise compensation method
WO2002019645A1 (en) Frequency offset estimator
JP4818342B2 (en) Frequency error estimation device
US20080170651A1 (en) Correction of mismatches between two I and Q channels
JP2008211760A (en) Modulation system estimation apparatus
JP2009147522A (en) Multilevel qam demodulator, multilevel qam demodulation method, and wireless communication system
US8761320B2 (en) Apparatus and method for automatic frequency prediction control
US7139343B2 (en) Digital radio receiver
JP4681637B2 (en) Frequency error estimation device
KR100709519B1 (en) System for the estimation of the complex gain of a transmission channel
JP5272893B2 (en) AFC circuit and AFC control method for digital radio
JP4435005B2 (en) Equalizer
JP2006295766A (en) Nonlinear distortion equalization system
JP3888966B2 (en) Automatic frequency control circuit
CN108353066B (en) Apparatus and method for carrier frequency offset correction and storage medium thereof
JP4326972B2 (en) Frequency offset compensation circuit and method
JPH09246917A (en) Frequency error estimation device
JP2000151732A (en) Carrier phase estimation device and demodulator using the estimation device

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20100831

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100929

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110318

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110329

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110525

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110621

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110801

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110823

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110830

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140909

Year of fee payment: 3

R151 Written notification of patent or utility model registration

Ref document number: 4818342

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140909

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees