JP4783906B2 - パッケージングされた積層型半導体装置及びその製造方法 - Google Patents
パッケージングされた積層型半導体装置及びその製造方法 Download PDFInfo
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Description
SiOxNy:[但し、SiOxNyにおいて、x及びyは、夫々0<X<2、0<y<1.4の範囲で、2x+3y=4を満たす数値を表す。]
SiOxCyNz:[但し、SiOxCyNzにおいて、x、y及びzは、夫々0<X<2、0<y<1、0<z<1.4の範囲で、2x+4y+3z=4を満たす数値を表す。]
SiNx:[但し、SiNxにおいて、xは、0<X<1.4を満たす数値を表す。]
窒素を含有する窒化珪素、即ちSiCxNyの炭窒化珪素膜は、硬い為、強いストレスが生じやすく、割れ易いという欠点を有するが、しかし、絶縁膜を炭窒化珪素膜にすると、ストレスを緩和できる効果が生じる。また比誘電率が低いという利点もあり、更に、バリア性が窒化珪素よりも優れているので、LSIのHigh-k絶縁膜のアンダーコートへの利用に最近では検討されている。
Claims (17)
- 外部電極端子として機能するバンプを、半導体装置のおもて面側及びその裏面側の両表面に備え、かつ、他の電極端子を有する他の半導体装置、基板、或いはボードに積層されて、その電極端子と直接に電気的に接続されて用いられるパッケージングされた積層型半導体装置において、
半導体基板を貫通する貫通電極を形成した半導体基板のおもて面側に、複数の回路素子を形成したLSI形成面、及び該LSI形成面の上に前記複数の回路素子に接続する多層配線部を有し、かつ、前記多層配線部の上面に塗布する第1の絶縁膜上において前記貫通電極を前記多層配線部に接続する再配線層、及び該再配線上において該再配線に接続するポスト電極を有し、該ポスト電極の頭部面を除いて半導体基板のおもて面を覆う第2の絶縁膜、及び前記ポスト電極の頭部面に接続される外部接続用のバンプを備え、前記第2の絶縁膜は半導体基板より厚くして、半導体装置の剛性を実質的に第2の絶縁膜で確保し、
前記半導体基板の裏面側において、前記貫通電極の頭部面が露出するように塗布した第3の絶縁膜の上で、前記貫通電極の頭部面に配線により接続されるバンプ形成部を備え、該バンプ形成部を、それを覆う第4の絶縁膜に開けた開口を通して外部接続用のバンプに接続したことを特徴とするパッケージングされた積層型半導体装置。 - 他の半導体装置を上面に位置するようアライメントを行って両者の接続部分が重なるようにして、外部接続用のバンプを接合させ、さらに、多層配線基板からなるドウターボードの上面に搭載して、接合した請求項1に記載のパッケージングされた積層型半導体装置。
- 前記他の半導体装置の周囲を前記ドウターボードによって支持するスペーサーを用いた請求項2に記載のパッケージングされた積層型半導体装置。
- さらに別の1つ又は複数の半導体装置を、途中に基板や放熱板を挿入して、立体的に接続した請求項2に記載のパッケージングされた積層型半導体装置。
- 前記第2の絶縁膜厚は40〜200μm、半導体基板厚は10〜50μm、第4の絶縁膜厚は30μm以下にした請求項1に記載のパッケージングされた積層型半導体装置。
- 前記半導体基板の裏面側において、前記貫通電極の頭部面に配線により接続されるバンプ形成部は、貫通電極位置より再配線層により任意の位置に再配置された請求項1に記載のパッケージングされた積層型半導体装置。
- 外部電極端子として機能するバンプを、半導体装置のおもて面側及びその裏面側の両表面に備え、かつ、他の電極端子を有する他の半導体装置、基板、或いはボードに積層されて、その電極端子と直接に電気的に接続されて用いられるパッケージングされた積層型半導体装置の製造方法において、
スクライブラインを介して格子状に複数配置された半導体ウエハ状の半導体基板のおもて面に、複数の回路素子を形成したLSI形成面、及び該LSI形成面の上に前記複数の回路素子に接続する多層配線部を形成すると共に、該半導体基板に貫通電極を設け、
前記多層配線部上に形成した第1の絶縁膜の上において、前記貫通電極を前記多層配線部に接続する再配線層を形成し、
前記再配線上において該再配線に接続するポスト電極を形成し、
さらにポスト電極を形成した後、該おもて面に第2の絶縁膜を塗布し、前記ポスト電極の先端を露出させた後、
半導体基板の裏面を研削して、貫通電極の先端を露出させた後、半導体基板の裏面上に第3の絶縁膜を、貫通電極頭部面が露出するように塗布し、
次に、半導体基板の裏面側の第3の絶縁膜の上に、該露出した貫通電極頭部面とバンプ形成部との配線を実施し、該配線の上に塗布された第4の絶縁膜に開けられた開口を通して、該バンプ形成部にバンプを形成し、前記第2の絶縁膜は半導体基板より厚く、第4の絶縁膜は半導体基板より薄くして、半導体装置の剛性を実質的に第2の絶縁膜で確保し、
半導体基板のおもて面側においては、ポスト電極の先端にバンプを形成する、
ことを特徴とするパッケージングされた積層型半導体装置の製造方法。 - 半導体基板の裏面側の前記第3の絶縁膜の上の配線はナノ金属粒子を用いてスクリーン印刷又はインクジェットにより実施した請求項7に記載のパッケージングされた積層型半導体装置の製造方法。
- 前記配線の上を窒化膜で被覆し、かつ、該窒化膜は、ヘキサメチルジシラザン、テトラメチルジシラザン、オクタメチルトリシラザン、ヘキサメチルシクロトリシラザン、テトラエチルテトラメチルシクロテトラシラザン、テトラフェニルジメチルジシラザンの中から選ばれた1種又は2種以上のシラザン化合物を加熱された触媒体に接触させ、接触分解反応により生じた化学種のシリコンカーボナイトライド、シリコンオキシナイトライド、シリコンオキシカーボナイトライド又はシリコンナイトライドの何れかである請求項8に記載のパッケージングされた積層型半導体装置の製造方法。
- 半導体基板のおもて面側および裏面のバンプの形成は、半導体ウエハを切断して個々の半導体装置に個別化する前に実施するか、又は、半導体ウエハを切断して個別化した後に実施する請求項7に記載のパッケージングされた積層型半導体装置の製造方法。
- 半導体基板を貫通する貫通電極の形成は、該貫通電極用の孔を開けた後、この孔の側壁に多層配線に悪影響を与えない程度の低温で絶縁膜を形成し、次に、貫通電極の埋め込みをした後、該貫通電極を前記多層配線部内の所定の配線層に接続してなる請求項7に記載のパッケージングされた積層型半導体装置の製造方法。
- 前記半導体基板を貫通する貫通電極の形成は、該貫通電極用の孔を開けた後、この孔の側壁に多層配線に悪影響を与えない程度の低温で絶縁膜を形成し、次に、前記多層配線部内の所定の配線層との接続部を開口した後、貫通電極部と接続部を同時に形成してなる請求項7に記載のパッケージングされた積層型半導体装置の製造方法。
- 前記貫通電極のための孔を、多数の同一半導体素子を同時形成する半導体ウエハ状の半導体基板に対して開口すると同時に、個々の半導体素子に切断するためのスクライブラインを所定の幅を持って開口し、前記第2の絶縁膜を半導体基板のおもて面のみならずスクライブラインの開口にも充填することにより、スクライブラインで切断した半導体装置の端面が絶縁膜で覆われる請求項7に記載のパッケージングされた積層型半導体装置の製造方法。
- 前記第1の絶縁膜および前記第2の絶縁膜は何れも半導体ウエハ状の半導体基板に対して形成され、裏面側の配線は銅ナノ金属微粒子を用いてインクジェットにより半導体ウエハ状の半導体基板上で形成された請求項7に記載のパッケージングされた積層型半導体装置の製造方法。
- 前記貫通電極用の孔側壁の絶縁膜として窒化膜を使用し、前記窒化膜が、ヘキサメチルジシラザン、テトラメチルジシラザン、オクタメチルトリシラザン、ヘキサメチルシクロトリシラザン、テトラエチルテトラメチルシクロテトラシラザン、テトラフェニルジメチルジシラザンの中から選ばれた1種又は2種以上のシラザン化合物を加熱された触媒体に接触させ、接触分解反応により生じた化学種を、前記孔側壁に触れさせ、該孔側壁表面上に形成されたシリコンカーボナイトライド、シリコンオキシナイトライド、シリコンオキシカーボナイトライド又はシリコンナイトライドの何れかである請求項7に記載のパッケージングされた積層型半導体装置の製造方法。
- 前記貫通電極が、前記絶縁膜を形成した孔に金属ナノ粒子を充填することにより形成される請求項15に記載のパッケージングされた積層型半導体装置の製造方法。
- 前記貫通電極を、水素を含有する化合物の気体を加熱された触媒体に接触させた接触分解反応により生じた原子状水素で処理することにより、表面酸化膜の還元、及び又は、有機物の除去を行った請求項16に記載のパッケージングされた積層型半導体装置の製造方法。
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