JP4742824B2 - Storage device initialization method - Google Patents

Storage device initialization method Download PDF

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JP4742824B2
JP4742824B2 JP2005326380A JP2005326380A JP4742824B2 JP 4742824 B2 JP4742824 B2 JP 4742824B2 JP 2005326380 A JP2005326380 A JP 2005326380A JP 2005326380 A JP2005326380 A JP 2005326380A JP 4742824 B2 JP4742824 B2 JP 4742824B2
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variable resistance
resistance element
memory
resistance value
film
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JP2007134512A (en
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恒則 椎本
信道 岡崎
寛伸 森
朋人 対馬
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Sony Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning

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Description

本発明は、不揮発性の可変抵抗素子によりメモリセルを構成した記憶装置に対して、初期化を行う方法に係わる。   The present invention relates to a method for initializing a memory device in which a memory cell is configured by a nonvolatile variable resistance element.

従来の記憶装置、特にフラッシュメモリを用いた記憶装置は、記憶データを保持するための電力が不要であることから、近年、盛んに用いられるようになっている。
特に、携帯電話装置を含む、携帯用の端末装置には、メモリとしてフラッシュメモリが多く用いられている。 Conventional storage devices, particularly storage devices using a flash memory, have been actively used in recent years because they do not require power to hold stored data.
In particular, flash memory is often used as a memory in portable terminal devices including mobile phone devices.

このようなフラッシュメモリを用いた記憶装置においては、データの書き込み動作の速度が遅いという問題がある（例えば、非特許文献１参照。）。   In such a storage device using a flash memory, there is a problem that the speed of data writing operation is slow (see, for example, Non-Patent Document 1).

日経エレクトロニクス，２００２．１１．１８号，ｐ．１３０Nikkei Electronics, 2002.11.11, p. 130

ところで、本出願人は、先に、上述したフラッシュメモリよりも優れた特性を持ちうる、不揮発性の可変抵抗素子を提案している。
この可変抵抗素子の膜構成は、例えば、図４の断面図に示すように、２つの電極１０１，１０２の間に導体膜１０３と絶縁体膜１０４を持つ膜構成になっている。導体膜１０３から絶縁体膜１０４に向かって電流Ｉが流れるように電圧をかけると、可変抵抗素子１０５が低抵抗に変化してデータが書き込まれ、絶縁体膜１０４から導体膜１０３に向かって電流が流れるように電圧をかけると、可変抵抗素子１０５が高抵抗に変化してデータが消去される。 By the way, the present applicant has previously proposed a nonvolatile variable resistance element that can have characteristics superior to the above-described flash memory.
The film structure of the variable resistance element is, for example, a film structure having a conductor film 103 and an insulator film 104 between two electrodes 101 and 102 as shown in the cross-sectional view of FIG. When a voltage is applied so that the current I flows from the conductor film 103 toward the insulator film 104, the variable resistance element 105 changes to a low resistance and data is written, and the current flows from the insulator film 104 toward the conductor film 103. When a voltage is applied so as to flow, the variable resistance element 105 changes to a high resistance and data is erased.

この構成の可変抵抗素子１０５は、フラッシュメモリ等と比較して、単純な構造でメモリセルを構成することができるため、素子のサイズ依存性がなく、大きい信号を得ることができるため、スケーリングに強いという特長を有する。
また、抵抗変化によるデータ書き込み速度を例えば５ナノ秒程度と速くすることができ、また低電圧（例えば１Ｖ程度）かつ低電流（例えば２０μＡ程度）で動作させることができるという利点を有する。 Since the variable resistance element 105 having this configuration can form a memory cell with a simple structure as compared with a flash memory or the like, there is no dependency on the size of the element and a large signal can be obtained. It has the feature of being strong.
Further, the data writing speed due to the resistance change can be increased to, for example, about 5 nanoseconds, and it can be operated at a low voltage (for example, about 1 V) and a low current (for example, about 20 μA).

この可変抵抗素子１０５では、絶縁体膜や導体膜の構成や製法によっては、データの書き換えの際に、書き込み後の抵抗値と消去後の抵抗値が変動することがある。
このように抵抗値が変動すると、データの読み出しを安定して行うことが難しくなり、また、データの書き換えを繰り返したときに書き込みエラーや消去エラーを発生する場合もある。 In this variable resistance element 105, the resistance value after writing and the resistance value after erasing may fluctuate when data is rewritten depending on the configuration and manufacturing method of the insulator film and the conductor film.
When the resistance value fluctuates in this way, it becomes difficult to read data stably, and a write error or an erase error may occur when data rewrite is repeated.

上述した問題の解決のために、本発明においては、情報の記録（書き込み、消去）後の抵抗値を安定にし、書き込みエラーや消去エラーの発生を防ぐことができる、記憶装置の初期化方法を提供するものである。   In order to solve the above-described problem, the present invention provides a method for initializing a storage device that can stabilize the resistance value after information recording (writing, erasing) and prevent the occurrence of a writing error or an erasing error. It is to provide.

本発明の記憶装置の初期化方法は、２つの電極の間に、異なる極性の電圧を印加することにより、抵抗値が高抵抗状態と低抵抗状態との間を可逆的に変化する可変抵抗素子を備え、この可変抵抗素子から成るメモリセルを複数有する記憶装置に対して、メモリセルに初めて情報を記録する前に初期化を行う際に、可変抵抗素子に異なる極性の電圧パルスを１回ずつ交互に印加する過程を複数回繰り返すものである。 An initialization method for a memory device according to the present invention is a variable resistance element in which a resistance value reversibly changes between a high resistance state and a low resistance state by applying voltages of different polarities between two electrodes. When a memory device having a plurality of memory cells composed of variable resistance elements is initialized before information is recorded in the memory cells for the first time, a voltage pulse of a different polarity is applied to the variable resistance elements once. The process of alternately applying is repeated a plurality of times .

上述の本発明の記憶装置の初期化方法によれば、可変抵抗素子に、異なる極性の電圧パルスを１回ずつ交互に印加する過程を複数回繰り返すことにより、可変抵抗素子の内部に伝導路を安定して形成する等の作用により、可変抵抗素子の高抵抗状態の抵抗値及び低抵抗状態の抵抗値を安定化させていくことができ、最終的に高抵抗状態の抵抗値及び低抵抗状態の抵抗値の変動が非常に小さい安定した状態へ遷移させることができる。
これにより、初期化を行った後には、メモリセルの可変抵抗素子に対して、書き込みエラーや消去エラーがなく、安定にデータの書き込み・消去を行うことが可能になる。 According to the above-described initialization method of the memory device of the present invention, the process of alternately applying voltage pulses of different polarities to the variable resistance element once is repeated a plurality of times, so that the conduction path is formed inside the variable resistance element. The resistance value in the high resistance state and the resistance value in the low resistance state of the variable resistance element can be stabilized by an action such as stable formation, and finally the resistance value in the high resistance state and the low resistance state It is possible to make a transition to a stable state in which the fluctuation in resistance value of
Thereby, after initialization, there is no writing error or erasing error with respect to the variable resistance element of the memory cell, and data can be stably written / erased.

上述の本発明によれば、メモリセルの可変抵抗素子に対して、書き込みエラーや消去エラーがなく、安定にデータの書き込み・消去を行うことが可能になるため、安定して動作する記憶装置を実現することができる。   According to the above-described present invention, since there is no writing error or erasing error with respect to the variable resistance element of the memory cell, it is possible to stably write and erase data, and thus a storage device that operates stably can be provided. Can be realized.

本発明に係る可変抵抗素子の一形態の概略断面図を、図１に示す。
この可変抵抗素子５は、２つの電極１，２の間に導体膜３と絶縁体膜４を持つ膜構成になっている。即ち、図４に示した可変抵抗素子１０５と同様の膜構成である。 FIG. 1 shows a schematic cross-sectional view of one embodiment of the variable resistance element according to the present invention.
This variable resistance element 5 has a film configuration having a conductor film 3 and an insulator film 4 between two electrodes 1 and 2. That is, the film configuration is the same as that of the variable resistance element 105 shown in FIG.

導体膜３の材料としては、例えば、Ｃｕ，Ａｇ，Ｚｎから選ばれる１つ以上の金属元素を含有する金属膜、合金膜（例えばＣｕＴｅ合金膜）、金属化合物膜等が挙げられる。
また、絶縁体膜４の材料としては、例えば、アモルファスＧｄ２Ｏ３や、ＳｉＯ２等の絶縁体が挙げられる。 Examples of the material of the conductor film 3 include a metal film containing one or more metal elements selected from Cu, Ag, and Zn, an alloy film (for example, a CuTe alloy film), a metal compound film, and the like.
Examples of the material for the insulator film 4 include insulators such as amorphous Gd 2 O 3 and SiO 2 .

このような材料を用いた場合、導体膜３に含まれるＣｕ，Ａｇ，Ｚｎが、イオン化して陰極側に引き寄せられる性質を有する。なお、同様にイオン化しやすい性質を有する、Ｃｕ，Ａｇ，Ｚｎ以外の金属元素を用いてもよい。
従って、電極１，２間に、絶縁体膜４側の電極２が低電位になるように電圧を加えると、金属元素のイオンが電極２に引き寄せられて、絶縁体膜４内に入っていく。そして、イオンが電極２まで到達すると、上下の電極１，２間が導通して抵抗値が下がることになる。このようにして、可変抵抗素子５へのデータ（情報）の書き込みが行われる。
一方、電極１，２間に、導体膜３側の電極１が低電位になるように電圧を加えると、金属元素がイオン化して電極１に引き寄せられて、絶縁体膜４から抜けていくため、上下の電極１，２間の絶縁性が増して、抵抗値が上がることになる。このようにして、可変抵抗素子５に対してデータ（情報）の消去が行われる。 When such a material is used, Cu, Ag, and Zn contained in the conductor film 3 are ionized and attracted to the cathode side. Similarly, metal elements other than Cu, Ag, and Zn that have the property of being easily ionized may be used.
Therefore, when a voltage is applied between the electrodes 1 and 2 so that the electrode 2 on the insulator film 4 side has a low potential, ions of the metal element are attracted to the electrode 2 and enter the insulator film 4. . And when ion reaches | attains to the electrode 2, between the upper and lower electrodes 1 and 2 will conduct | electrically_connect and a resistance value will fall. In this way, data (information) is written to the variable resistance element 5.
On the other hand, when a voltage is applied between the electrodes 1 and 2 so that the electrode 1 on the conductor film 3 side is at a low potential, the metal element is ionized and attracted to the electrode 1 and escapes from the insulator film 4. The insulation between the upper and lower electrodes 1 and 2 increases, and the resistance value increases. In this way, data (information) is erased from the variable resistance element 5.

上述した変化を繰り返すことにより、可変抵抗素子５の抵抗値を、高抵抗状態と低抵抗状態との間で可逆的に変化させることができる。
実際には、絶縁体膜４中の金属元素のイオンの量によって、絶縁体膜４の抵抗値が変化しているので、絶縁体膜４を情報が記憶・保持される記憶層とみなすことができる。 By repeating the above-described change, the resistance value of the variable resistance element 5 can be reversibly changed between the high resistance state and the low resistance state.
Actually, since the resistance value of the insulator film 4 varies depending on the amount of metal element ions in the insulator film 4, the insulator film 4 can be regarded as a memory layer in which information is stored and held. it can.

可変抵抗素子５の具体的な膜構成としては、例えば、導体膜３としてＣｕＴｅ膜を膜厚２０ｎｍで形成し、その上に絶縁体膜４としてアモルファスＧｄ２Ｏ３膜を膜厚５ｎｍで形成する。 As a specific film configuration of the variable resistance element 5, for example, a CuTe film is formed as a conductor film 3 with a film thickness of 20 nm, and an amorphous Gd 2 O 3 film is formed as an insulator film 4 with a film thickness of 5 nm. .

この可変抵抗素子５を用いてメモリセルを構成し、メモリセルを多数設けることにより、メモリ（記憶装置）を構成することができる。   A memory (storage device) can be configured by configuring a memory cell using the variable resistance element 5 and providing a large number of memory cells.

ところで、導体膜３又は絶縁体膜４の構成や材料を変えた可変抵抗素子５の３つの形態について、それぞれの可変抵抗素子５に対して、書き込み及び消去を繰り返す、即ち書き換えを繰り返した場合の特性を、図２Ａ〜図２Ｃに示す。各図において、横軸を書き換え回数、縦軸を抵抗値として、書き込み後の抵抗値（書き込み抵抗）ＲＷ及び消去後の抵抗値（消去抵抗）ＲＥをそれぞれプロットしている。   By the way, with respect to the three forms of the variable resistance element 5 in which the configuration and material of the conductor film 3 or the insulator film 4 are changed, writing and erasing are repeated for each variable resistance element 5, that is, when rewriting is repeated. The characteristics are shown in FIGS. 2A-2C. In each figure, the resistance value after writing (writing resistance) RW and the resistance value after erasing (erasing resistance) RE are plotted with the horizontal axis representing the number of rewrites and the vertical axis representing the resistance value.

図２Ａに示す形態では、書き換え回数４０回程度までは、書き込み後の抵抗値ＲＷが徐々に低下し、消去後の抵抗値ＲＥが不安定な推移を示している。
一方、書き換え回数４０回以後は、書き込み後の抵抗値ＲＷ及び消去後の抵抗値ＲＥが、共にエラーもなく安定に推移している。 In the form shown in FIG. 2A, the resistance value RW after writing gradually decreases and the resistance value RE after erasing shows an unstable transition up to about 40 rewrites.
On the other hand, after 40 rewrites, both the resistance value RW after writing and the resistance value RE after erasing are stable without error.

図２Ｂに示す形態では、書き換え回数１００回程度までは、書き込み後の抵抗値ＲＷが徐々に低下し、消去後の抵抗値ＲＥが不安定な推移を示している。また、書き込みエラーが発生している。
一方、書き換え回数１００回以後は、書き込み後の抵抗値ＲＷ及び消去後の抵抗値ＲＥが、共にエラーもなく安定に推移している。 In the form shown in FIG. 2B, the resistance value RW after writing gradually decreases and the resistance value RE after erasing shows an unstable transition up to about 100 rewrites. A write error has occurred.
On the other hand, after 100 rewrites, both the resistance value RW after writing and the resistance value RE after erasing are stable without error.

図２Ｃに示す形態では、書き換え回数１００回以前では、書き込みエラー、消去エラーが共に発生している。特に、書き込みは成功しておらず、書き込み後の抵抗値ＲＷが高抵抗状態のままとなっている。
一方、書き換え回数１００回以後は、書き込み後の抵抗値ＲＷ及び消去後の抵抗値ＲＥが、共にエラーもなく安定に推移している。 In the form shown in FIG. 2C, both a writing error and an erasing error have occurred before the number of rewrites 100 times. In particular, writing is not successful, and the resistance value RW after writing remains in a high resistance state.
On the other hand, after 100 rewrites, the resistance value RW after writing and the resistance value RE after erasing both are stable without error.

これらの形態に示したように抵抗値が推移するメカニズムは、次のように考えられる。
書き換え回数の少ない初期においては、金属元素のイオンのコンダクションパス（伝導路）の形成の再現性が少なく不安定であると推測される。
これに対して、何回かの書き換えを繰り返すことによって、金属元素のイオンのコンダクションパスが再現性良く安定に形成されるようになると推測される。 The mechanism by which the resistance value changes as shown in these forms is considered as follows.
In the initial stage where the number of rewrites is small, it is presumed that the formation of a conduction path (conduction path) of ions of metal elements is less reproducible and unstable.
On the other hand, it is presumed that by repeating rewriting several times, a conduction path of ions of metal elements can be stably formed with good reproducibility.

従って、可変抵抗素子５に対して、複数回の書き換えを行うことにより、金属元素のイオンのコンダクションパスを再現性良く安定に形成することができると考えられる。
そこで、初回のデータの書き込みに先立ち、初期化過程として、このように書き換えを複数回行うようにすれば、可変抵抗素子５を安定化させることができる。 Therefore, it is considered that the ion element conduction path can be stably formed with good reproducibility by rewriting the variable resistance element 5 a plurality of times.
Therefore, if the rewriting is performed a plurality of times as an initialization process prior to the first data writing, the variable resistance element 5 can be stabilized.

続いて、本発明の一実施の形態として、図１に示した可変抵抗素子５を用いてメモリセルを構成した記憶装置（メモリ）に対して、初期化を行う方法を説明する。
本実施の形態の初期化パルス波形を図３に示す。
本実施の形態では、図３に示すように、異なる極性の電圧パルス（書き込みパルスＰＷと消去パルスＰＥ）を交互に印加する書き込みと消去を交互に複数回繰り返す。繰返し回数は、通常、例えば１０回から１０００回程度である。
図３では、書き込み電圧及び消去電圧と、書き込みパルス幅ＴＷ及び消去パルス幅ＴＥを、いずれもほぼ同一とした電圧パルスＰＷ，ＰＥを複数回繰り返している。
なお、初期化の際の電圧パルスを、通常のデータの書き込みや消去の際のパルス電圧に対して、同じ電圧や同じパルス幅としてもよいし、異なる電圧や異なるパルス幅としてもよい。 Next, as an embodiment of the present invention, a method for initializing a memory device (memory) in which a memory cell is configured using the variable resistance element 5 shown in FIG. 1 will be described.
The initialization pulse waveform of this embodiment is shown in FIG.
In the present embodiment, as shown in FIG. 3, writing and erasing in which voltage pulses (writing pulse PW and erasing pulse PE) having different polarities are applied alternately are repeated a plurality of times. The number of repetitions is usually about 10 to 1000 times, for example.
In FIG. 3, voltage pulses PW and PE in which the write voltage and erase voltage, and the write pulse width TW and erase pulse width TE are both substantially the same are repeated a plurality of times.
Note that the voltage pulse at the time of initialization may be the same voltage or the same pulse width as the pulse voltage at the time of writing or erasing normal data, or may be a different voltage or a different pulse width.

この初期化パルスを印加する、初期化過程は、初回のデータの書き込みに先立って、１回行えばよい。
また、記憶装置の工場出荷時に行っても良いし、出荷後にユーザーが行っても良い。 The initialization process for applying the initialization pulse may be performed once prior to the first data writing.
Further, it may be performed when the storage device is shipped from the factory, or may be performed by the user after shipment.

異なる極性の電圧パルスを交互に印加する回数は、可変抵抗素子５の絶縁体膜４や導体膜３の構成や製法によって異なる。
ちなみに、図２Ａに示した形態では４０回以上に、図２Ｂに示した形態及び図２Ｃに示した形態では１００回以上に、それぞれ電圧パルスの回数を設定することが望ましい。 The number of times the voltage pulses having different polarities are alternately applied depends on the configuration of the insulator film 4 and the conductor film 3 of the variable resistance element 5 and the manufacturing method.
Incidentally, it is desirable to set the number of voltage pulses to 40 times or more in the form shown in FIG. 2A, and to 100 times or more in the form shown in FIG. 2B and 100% in the form shown in FIG. 2C.

上述の本実施の形態によれば、異なる極性の電圧パルスＰＷ，ＰＥを交互に印加することによって、書き込みと消去を交互に複数回繰り返すことにより、金属元素のイオンのコンダクションパスが再現性よく安定に形成されるようになる。
これにより、書き込み後の抵抗値ＲＷと消去後の抵抗値ＲＥを安定にし、書き込みエラーや消去エラーの発生を防ぐことができる。 According to the above-described embodiment, by alternately applying voltage pulses PW and PE having different polarities, writing and erasing are alternately repeated a plurality of times, so that the conduction path of the metal element ions is highly reproducible. It will be formed stably.
As a result, the resistance value RW after writing and the resistance value RE after erasing can be stabilized, and the occurrence of writing errors and erasing errors can be prevented.

上述の実施の形態では、書き込み電圧及び消去電圧と、書き込みパルス幅及び消去パルス幅を、いずれもほぼ同一とした電圧パルスＰＷ，ＰＥを複数回繰り返して初期化を行ったが、電圧パルスの電圧（振幅）やパルス幅（時間）を、ほぼ一定ではなく、変化させることも可能である。また、書き込み側の一方の極性と消去側の他方の極性とで、電圧やパルス幅を異ならせることも可能である。   In the above-described embodiment, the voltage pulse PW and PE in which the write voltage and the erase voltage, and the write pulse width and the erase pulse width are both substantially the same are initialized a plurality of times. (Amplitude) and pulse width (time) are not substantially constant and can be changed. It is also possible to make the voltage and pulse width different between one polarity on the writing side and the other polarity on the erasing side.

さらに、本発明において、可変抵抗素子は、図１に示した可変抵抗素子５の構成に限定されるものではなく、その他の構成も可能である。   Furthermore, in the present invention, the variable resistance element is not limited to the configuration of the variable resistance element 5 shown in FIG. 1, and other configurations are possible.

例えば、（１）図１とは積層順序を逆にして、絶縁体膜の上に導体膜を積層した構成、（２）導体膜が電極を兼ねる構成、（３）導体膜を設ける代わりに、導体膜に用いられる金属元素を絶縁体膜に含有させた構成等が考えられる。   For example, (1) a structure in which the order of lamination is reversed from that in FIG. 1 and a conductor film is laminated on an insulator film, (2) a structure in which the conductor film also serves as an electrode, and (3) instead of providing a conductor film The structure etc. which contained the metal element used for a conductor film in the insulator film | membrane etc. can be considered.

また、可変抵抗素子としては、イオン化しやすい金属元素と絶縁体膜とを有する可変抵抗素子以外にも、様々な構成がある。
その他の構成の可変抵抗素子であっても、本発明を適用することが可能である。
特に、書き換え回数を増やしていくことによって、例えば伝導路が安定して形成される等のメカニズムで、書き換え（書き込み、消去）後の抵抗値が安定化していく可変抵抗素子であれば、前述した実施の形態と同様に、書き換え後の抵抗値を安定化させて、エラーの発生を防ぐ効果を得ることができる。 The variable resistance element has various configurations other than the variable resistance element having a metal element that is easily ionized and an insulator film.
The present invention can be applied to variable resistance elements having other configurations.
In particular, if the variable resistance element is such that the resistance value after rewriting (writing, erasing) is stabilized by increasing the number of times of rewriting, for example, by a mechanism in which the conduction path is stably formed or the like, it is described above. As in the embodiment, the resistance value after rewriting can be stabilized and an effect of preventing the occurrence of errors can be obtained.

本発明は、上述の実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲でその他様々な構成が取り得る。   The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

本発明に係る可変抵抗素子の一形態の膜構成を示す断面図である。It is sectional drawing which shows the film | membrane structure of one form of the variable resistance element which concerns on this invention. Ａ〜Ｃ 可変抵抗素子の３つの形態における書き換え回数と抵抗値との関係を示す図である。It is a figure which shows the relationship between the frequency | count of rewriting and resistance value in three forms of AC variable resistance element. 初期化の際に印加する電圧パルスの波形を示す図である。It is a figure which shows the waveform of the voltage pulse applied in the case of initialization. 可変抵抗素子の膜構成を示す断面図である。It is sectional drawing which shows the film | membrane structure of a variable resistance element.

符号の説明Explanation of symbols

１，２ 電極、３ 導体膜、４ 絶縁体膜、５ 可変抵抗素子 1, 2 electrodes, 3 conductor films, 4 insulator films, 5 variable resistance elements

Claims (4)

２つの電極の間に、異なる極性の電圧を印加することにより、抵抗値が高抵抗状態と低抵抗状態との間を可逆的に変化する可変抵抗素子を備え、
前記可変抵抗素子から成るメモリセルを複数有する記憶装置に対して、
前記メモリセルに初めて情報を記録する前に、初期化を行う方法であって、
前記可変抵抗素子に、異なる極性の電圧パルスを１回ずつ交互に印加する過程を複数回繰り返す
記憶装置の初期化方法。 A variable resistance element having a resistance value reversibly changed between a high resistance state and a low resistance state by applying voltages of different polarities between the two electrodes,
For a memory device having a plurality of memory cells made of the variable resistance element,
A method for performing initialization before recording information in the memory cell for the first time,
A method for initializing a storage device, wherein a process of alternately applying voltage pulses of different polarities to the variable resistance element one by one is repeated a plurality of times . 電圧パルスの振幅及び時間をほぼ一定にして、前記異なる極性の電圧パルスを印加する請求項１に記載の記憶装置の初期化方法。 The method for initializing a memory device according to claim 1, wherein the voltage pulses having different polarities are applied with the amplitude and time of the voltage pulse being substantially constant. 前記可変抵抗素子が、前記２つの電極の間に、絶縁体から成る記憶層を有し、前記記憶層に接する層内に、或いは、前記記憶層内に、イオン化が容易な金属元素が含有されている構成である請求項１に記載の記憶装置の初期化方法。 The variable resistance element has a memory layer made of an insulator between the two electrodes, and a metal element that is easily ionized is contained in a layer in contact with the memory layer or in the memory layer. The method for initializing a storage device according to claim 1, wherein: 前記金属元素が、Ｃｕ，Ａｇ，Ｚｎから選ばれる１つ以上の元素である請求項３に記載の記憶装置の初期化方法。 4. The method for initializing a memory device according to claim 3, wherein the metal element is one or more elements selected from Cu, Ag, and Zn.
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