JP4714480B2 - Liquid crystal display element - Google Patents
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- JP4714480B2 JP4714480B2 JP2005047119A JP2005047119A JP4714480B2 JP 4714480 B2 JP4714480 B2 JP 4714480B2 JP 2005047119 A JP2005047119 A JP 2005047119A JP 2005047119 A JP2005047119 A JP 2005047119A JP 4714480 B2 JP4714480 B2 JP 4714480B2
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本発明は、一対の基板にそれぞれ設けた各電極の端子を一方の基板にまとめた片側基板端子型の液晶表示素子に関する。 The present invention relates to a one-side substrate terminal type liquid crystal display element in which terminals of respective electrodes provided on a pair of substrates are combined on one substrate.
従来の液晶表示素子に、一対の基板にそれぞれ複数の電極を設け、これら電極に電圧を供給するための配線の各端子を一方の基板にまとめて設置した、片側基板端子型の液晶表示素子がある。この片側基板端子型の液晶表示素子は、外部電気回路との接続が容易で実装構造が簡素化されるという利点を備えている。 In a conventional liquid crystal display element, a single-side substrate terminal type liquid crystal display element in which a plurality of electrodes are provided on a pair of substrates and wiring terminals for supplying voltage to these electrodes are collectively installed on one substrate is provided. is there. This one-side substrate terminal type liquid crystal display element has the advantage that the connection structure with an external electric circuit is easy and the mounting structure is simplified.
しかし、この片側基板端子型液晶表示素子においては、一方の基板に設けられた電極と、他方の基板に設けられた前記電極に電圧を供給するための引き回し配線とを導電接続する必要があり、そのための構造や工程がコストアップを引き起こす。すなわち、一方の基板に前記電極から配線を引き出して接続パッドを形成し、他方の基板の引き回し配線に設けられた被接続パッドとを導通部材により導通接続(以下、基板間導通という)するから、導通部材の材料費とこれを配置し基板間導通するための工数が増加する。 However, in this one-side substrate terminal type liquid crystal display element, it is necessary to conductively connect an electrode provided on one substrate and a lead wiring for supplying a voltage to the electrode provided on the other substrate, The structure and process for that cause cost increase. That is, since a wiring is drawn out from the electrode on one substrate to form a connection pad, and a connected pad provided on the routing wiring on the other substrate is conductively connected by a conductive member (hereinafter referred to as inter-substrate conduction), The material cost of the conductive member and the number of steps for arranging the conductive member and connecting between the substrates increase.
特に、一方の基板に複数の表示電極を設け、他方の基板にそれらの表示電極に直交させて複数の走査電極を配設する単純マトリクス型液晶表示素子においては、片側基板端子化することにより構造や製造工程がより複雑化してしまう。 In particular, in a simple matrix type liquid crystal display element in which a plurality of display electrodes are provided on one substrate and a plurality of scanning electrodes are disposed on the other substrate so as to be orthogonal to the display electrodes, the structure is obtained by forming a single-side substrate terminal. And the manufacturing process becomes more complicated.
上述のような片側基板端子構造の単純マトリクス型液晶表示素子であっても、基板間導通を作業性良く実施できる従来の方法として、一対の基板を接合するために設けられるシール材中に導電性粒子を含有させ、その導電性粒子を介して対応する接続パッドと被接続パッドを導電接続する方法が知られている。（例えば特許文献１参照）
しかるに、近年はユーザーのディスプレイに対する高精細化の要望が強く、これに対応すべく液晶表示素子も高精細化が求められている。高精細化液晶表示素子においては、画素密度が高くなるのに応じて各画素に信号電圧を供給する配線も高密度化する。従って、片側基板端子構造の単純マトリクス型液晶表示素子においては、高密度化した配線に対応して接続パッドと被接続パッドも高密度化して個々のパッド面積が小さくなり、基板間導通における信頼性が低下すると共に電気抵抗値がばらつく。配線の電気抵抗値のバラツキは、表示ムラを引き起こす原因となる。
Even in a simple matrix type liquid crystal display element having a single-sided substrate terminal structure as described above, as a conventional method capable of conducting conduction between substrates with good workability, the conductive material is contained in a sealing material provided to join a pair of substrates. A method is known in which particles are contained, and corresponding connection pads and connection pads are conductively connected through the conductive particles. (For example, see Patent Document 1)
However, in recent years, there has been a strong demand for higher definition for the display of the user, and in order to meet this demand, higher definition is also required for the liquid crystal display element. In a high-definition liquid crystal display element, the wiring for supplying a signal voltage to each pixel is also densified as the pixel density increases. Therefore, in a simple matrix type liquid crystal display element with a single-sided substrate terminal structure, the connection pads and the pads to be connected are also densified in accordance with the densified wiring, and the individual pad area is reduced, and the reliability in inter-substrate conduction is reduced. As the value decreases, the electrical resistance varies. Variation in the electric resistance value of the wiring causes display unevenness.
また、配線の高密度化に対応するために、個々の配線が最低限必要な線幅を確保できるように引き回しパターンが最適化され、その結果、配線の引き回しエリアが増大する。この場合、液晶表示素子の小型化を促進するには額縁部の幅を可及的に小さくする必要があるため、配線の引き回しエリアは、特許文献２に示されるように両基板を接合するシール材の外側に沿った広い範囲に設定される。
しかし、特許文献２に示した液晶表示素子では、シール材の外側に沿った配線の引き回しエリアは、両基板の縁部が対向する隙間になっているために、液晶注入時における余剰液晶や種々の狭雑物が入り込みやすく且つ除去し難いため、これらにより配線が電食される虞がある。配線の電食を防止するために保護膜をオーバーコートする場合、そのための材料費や工数がアップする。 However, in the liquid crystal display element disclosed in Patent Document 2, the wiring routing area along the outside of the sealing material is a gap where the edges of both substrates face each other. Since these narrow objects are easy to enter and difficult to remove, there is a risk that the wiring may be eroded. In the case of overcoating a protective film to prevent electrical corrosion of the wiring, the material cost and man-hours for that purpose increase.
本発明の目的は、高精細化により配線密度が高くなっても電気抵抗値のバラツキが少なく信頼性に優れた基板間導通が得られると共に配線の電食等による劣化が顕著に抑えられ、高度な表示品質を長期にわたり安定して得ることができる片側基板端子型液晶表示素子を提供することである。 The object of the present invention is to achieve highly reliable inter-substrate conduction with little variation in electrical resistance value even when the wiring density is increased due to high definition, and the deterioration due to electrolytic corrosion of wiring is remarkably suppressed. An object of the present invention is to provide a single-sided substrate terminal type liquid crystal display element capable of stably obtaining a good display quality over a long period of time.
本発明の液晶表示素子は、複数の第1の電極、これらの第１の電極にそれぞれ接続され、前記複数の第１の電極に電圧を供給するための複数の前側第１配線、及びこれらの前側第１配線にそれぞれ設けられた第１接続パッドが形成された第１の基板と、複数の第２の電極、これらの第２の電極にそれぞれ接続され、前記複数の第２の電極に電圧を供給するための複数の第２配線、前記第１接続パッドにそれぞれ対応させて設けられた複数の第１被接続パッド、及びこれらの第１被接続パッドにそれぞれ電圧を供給する複数の後側第１配線が形成された第２の基板と、絶縁樹脂基材中に導電性粒子を含有させてなり、前記第１の基板及び前記第２の基板をそれぞれの電極形成面を対向させて所定の間隙を保ち接合する接合部材と、前記第１の基板及び前記第２の基板の対向する各内面と前記接合部材とで囲まれる空間に封入された液晶とからなる液晶表示素子であって、前記接合部材は、前記第１の電極と前記第２の電極とが前記液晶を介して対向する領域毎に形成された複数の画素からなる表示領域を内側に囲む枠状の第１シール部と、該第１シール部の外側の所定の領域を囲む第２シール部とを備え、前記第１接続パッドとこれに対応する前記第１被接続パッドとは、前記第１シール部と前記第２シール部のうちの少なくとも一方のシール部に対応させて配設され、前記導電性粒子を介し導通接続されていることを特徴とするものである。 The liquid crystal display element of the present invention includes a plurality of first electrodes, a plurality of front first wirings connected to the first electrodes and supplying a voltage to the plurality of first electrodes, and these A first substrate on which a first connection pad provided on each of the front first wirings is formed, a plurality of second electrodes, and a voltage applied to the plurality of second electrodes. A plurality of second wirings for supplying power, a plurality of first connected pads provided corresponding to the first connection pads, and a plurality of rear sides for supplying voltages to the first connected pads, respectively. The second substrate on which the first wiring is formed and the insulating resin base material contain conductive particles, and the first substrate and the second substrate are arranged with their respective electrode formation surfaces facing each other. A bonding member for bonding while maintaining a gap between the first substrate and the first substrate And a liquid crystal display element comprising a liquid crystal sealed in a space surrounded by each of the opposing inner surfaces of the second substrate and the bonding member, wherein the bonding member includes the first electrode and the second electrode. A frame-shaped first seal portion that encloses a display region composed of a plurality of pixels formed in each region where the electrodes face each other through the liquid crystal, and a first region that surrounds a predetermined region outside the first seal portion. The first connection pad and the corresponding first connected pad corresponding to the first connection pad are arranged corresponding to at least one of the first seal portion and the second seal portion. It is provided and is electrically connected through the conductive particles.
本発明の液晶表示素子によれば、高精細化により配線密度が増加しても、基板間導通部における接続パッドと被接続パッドの面積を大きく確保できるから、電気抵抗値のバラツキの少ない信頼性に富む基板間導通が得られると共に、引き回し配線の電食等による劣化が顕著に抑制され、良好な表示品質を長期にわたり安定して得ることができる。 According to the liquid crystal display element of the present invention, even when the wiring density increases due to high definition, a large area of the connection pad and the connection pad in the inter-substrate conductive portion can be ensured. In addition to being able to obtain a rich inter-substrate conduction, deterioration due to electrolytic corrosion or the like of the routing wiring is remarkably suppressed, and good display quality can be stably obtained over a long period of time.
本発明の液晶表示素子においては、第１接続パッドと第１被接続パッドとがそれぞれ前側第１配線と後側第１配線に一対づつ形成され、第１シール部と第２シール部の双方でそれぞれ導通接続されていることが好ましく、これにより、第１接続パッドと第１被接続パッドのそれぞれの総面積が大きく確保されると共に並列配線回路が形成され、基板間導通部における電気抵抗値の絶対値を低下させ且つそのバラツキを抑えることができ、より信頼性に優れると共に表示品質が良好な高精細化が促進された片側基板端子型の液晶表示素子が得られる。 In the liquid crystal display element of the present invention, the first connection pad and the first connected pad are formed in pairs on the front first wiring and the rear first wiring, respectively, and both in the first seal part and the second seal part. It is preferable that each of the first connection pads and the first connected pads is large, and a parallel wiring circuit is formed, and the electric resistance value of the inter-substrate conductive portion is increased. An absolute value can be reduced and variations thereof can be suppressed, and a one-side substrate terminal type liquid crystal display element that is more reliable and promotes high definition with good display quality can be obtained.
また、本発明の液晶表示素子においては、第１接続パッドと第１被接続パッドとはそれぞれ前側第１配線と後側第１配線に１個づつ形成され、隣り合う第１接続パッドと第１被接続パッドとの導通接続部は互いに第１シール部と第２シール部のうちの異なるシール部に形成されていることが好ましく、これにより、第１接続パッドと第１被接続パッドの面積を大きく確保でき、第１の基板と第２の基板との接合時における第１接続パッドと第２被接続パッドとの位置合わせが容易となる。 In the liquid crystal display element of the present invention, the first connection pad and the first connected pad are formed one by one for the front first wiring and the rear first wiring, respectively. The conductive connection portion with the connected pad is preferably formed in a different seal portion of the first seal portion and the second seal portion, thereby reducing the area of the first connection pad and the first connected pad. A large amount can be secured, and the first connection pad and the second connection pad can be easily aligned at the time of joining the first substrate and the second substrate.
さらに、本発明の液晶表示素子においては、第２配線にそれぞれ対応させて第１の基板に複数の補助第２配線が配設され、これら第２配線と補助第２配線にそれぞれ第２接続パッドとこれに対応する第２被接続パッドが一対づつ形成され、一対の第２接続パッドと一対の第２被接続パッドは第１シール部と第２シール部の双方でそれぞれ導通接続されている構成とすることが好ましく、これにより、第１配線だけでなく第２配線においても並列回路が形成されて電気抵抗値を低減することができる。 Furthermore, in the liquid crystal display element of the present invention, a plurality of auxiliary second wirings are disposed on the first substrate so as to correspond to the second wirings, and the second connection pads are respectively provided on the second wirings and the auxiliary second wirings. And a pair of second connected pads corresponding to each other, and the pair of second connected pads and the pair of second connected pads are electrically connected to each other by both the first seal portion and the second seal portion. In this way, a parallel circuit is formed not only in the first wiring but also in the second wiring, and the electric resistance value can be reduced.
（第１実施形態）
図１は本発明の実施形態としての液晶表示素子を示す平面図で、図２はその要部Ｑを拡大して示す部分平面図、図３(ａ)、(ｂ)はそれぞれ図２におけるＡ−Ａ線の模式的部分断面図と、これと同様に切断した他の部分の模式的部分断面図である。
(First embodiment)
FIG. 1 is a plan view showing a liquid crystal display device as an embodiment of the present invention, FIG. 2 is a partial plan view showing an enlarged main part Q, and FIGS. 3 (a) and 3 (b) are respectively A in FIG. It is the typical partial sectional view of the -A line, and the typical partial sectional view of the other part cut | disconnected similarly to this.
本実施形態の液晶表示素子は、単純マトリクス型液晶表示素子であり、図１に示されるように、平面外形が細長い長方形をなす一対のガラス基板１、２が、シール材３により所定の間隙を保ち接合されている。これら一対のガラス基板１、２は大きさが異なっており、一方の大ガラス基板１の隣り合う２辺の端部１ａ、１ｂを他方の小ガラス基板２の対応する各端面よりもそれぞれ適長突出させて、接合されている。 The liquid crystal display element of the present embodiment is a simple matrix type liquid crystal display element. As shown in FIG. 1, a pair of glass substrates 1 and 2 having a rectangular outer shape in plan view have a predetermined gap by a sealing material 3. Keep joined. The pair of glass substrates 1 and 2 are different in size, and the end portions 1a and 1b on the two adjacent sides of the one large glass substrate 1 are more suitable than the corresponding end surfaces of the other small glass substrate 2, respectively. Protrusions are joined.
接合された一対のガラス基板１、２の各対向面(内面)には、それぞれ、複数のストライプ電極４、５が互いに直交する方向に平行に延在させて配設されている。本実施形態においては、ガラス基板２の内面に複数の走査電極４が基板長手方向へ平行に延在させて配設され、ガラス基板１の内面には複数の表示電極５が基板短手方向へ平行に延在させて配設されている。 A plurality of stripe electrodes 4 and 5 are arranged on each facing surface (inner surface) of the pair of bonded glass substrates 1 and 2 so as to extend in parallel in directions orthogonal to each other. In the present embodiment, a plurality of scanning electrodes 4 are disposed on the inner surface of the glass substrate 2 so as to extend in parallel to the longitudinal direction of the substrate, and a plurality of display electrodes 5 are disposed on the inner surface of the glass substrate 1 in the lateral direction of the substrate. It is arranged to extend in parallel.
上述の走査電極４と表示電極５が対向する領域が画素ｐとなり、従って、それら複数の画素ｐがドットマトリックス配置された表示領域Ｄdが形成されている。
本実施形態の液晶表示素子は、液晶を駆動するためのドライバチップがガラス基板１に直接搭載されたＣＯＧ(Chip On Glass)実装方式の液晶表示素子である。すなわち、走査電極４に走査駆動電圧を供給する走査ドライバチップ６が突出部１ａに、表示電極５に表示駆動電圧を供給する表示ドライバチップ７が突出部１ｂに、それぞれＣＯＧ方式により搭載されている。
The region where the scanning electrode 4 and the display electrode 5 are opposed to each other is a pixel p, and thus a display region Dd in which the plurality of pixels p are arranged in a dot matrix is formed.
The liquid crystal display element of the present embodiment is a COG (Chip On Glass) mounting type liquid crystal display element in which a driver chip for driving a liquid crystal is directly mounted on the glass substrate 1. That is, the scanning driver chip 6 that supplies the scanning drive voltage to the scanning electrode 4 is mounted on the protruding portion 1a, and the display driver chip 7 that supplies the display driving voltage to the display electrode 5 is mounted on the protruding portion 1b by the COG method. .
そして、上記表示領域Ｄdを囲む略枠形状をなすシール材３が両ガラス基板１、２間に配置され、両基板１、２が接合されている。シール材３は、図３に示されるように絶縁樹脂基材３ａ中に導電性粒子３ｂが分散混合されてなる。本例の導電性粒子３ｂは樹脂粒子の表面に金をメッキ処理により被着して形成されている。基板接合時においては、この絶縁樹脂基材３ａ中に導電性粒子３ｂが分散混合された材料が、例えばガラス基板１の内面に図１に示されるパターンに印刷法により塗布される。 And the sealing material 3 which makes the substantially frame shape surrounding the said display area Dd is arrange | positioned between the both glass substrates 1 and 2, and both the substrates 1 and 2 are joined. As shown in FIG. 3, the sealing material 3 is formed by dispersing and mixing conductive particles 3b in an insulating resin base material 3a. The conductive particles 3b of this example are formed by depositing gold on the surface of the resin particles by plating. At the time of substrate bonding, a material in which conductive particles 3b are dispersed and mixed in this insulating resin base material 3a is applied to the pattern shown in FIG.
ここで、シール材３は、図１に示されるように、表示領域Ｄdを内側に囲む矩形枠状をなす第１シール部３Ａと、この第１シール部３Ａの外側で、基板突出部１ａ、１ｂに対応するガラス基板２の隣り合う２辺に沿った、外縁領域Ｄfを囲む第２シール部３Ｂとからなる。第１シール部３Ａには、液晶を注入するための液晶注入穴３ｃが形成されている。なお、本実施形態では、第２シール部３Ｂにより囲まれる外縁領域Ｄfに液晶が封入されないため、第２シール部３Ｂには液晶注入穴が設けられていないが、液晶注入側とは反対側の適所に内部気圧を安定させるための微小な空気逃がし穴(不図示)が設けられている。 Here, as shown in FIG. 1, the sealing material 3 includes a first seal portion 3A having a rectangular frame shape that surrounds the display region Dd inside, and a substrate protruding portion 1a on the outside of the first seal portion 3A, It consists of the 2nd seal | sticker part 3B surrounding the outer edge area | region Df along two adjacent sides of the glass substrate 2 corresponding to 1b. A liquid crystal injection hole 3c for injecting liquid crystal is formed in the first seal portion 3A. In the present embodiment, since the liquid crystal is not sealed in the outer edge region Df surrounded by the second seal portion 3B, the second seal portion 3B is not provided with a liquid crystal injection hole, but on the side opposite to the liquid crystal injection side. A minute air escape hole (not shown) for stabilizing the internal air pressure is provided at an appropriate position.
ガラス基板２の内面に配設された各走査電極４の一方の端部を延出させて前側走査配線８が形成されている。これら前側走査配線８は、ガラス基板２の突出部１ａに対応する端部の中央に向けて収斂するパターンに引き回されている。そして、それら各前側走査配線８には、図２に示されるように、第１シール部３Ａと第２シール部３Ｂの配設部に対応させて一対の基板間導通用接続パッド８ａ、８ａがそれぞれ形成されている。これら接続パッド８ａは、対応する各シール部３Ａ、３Ｂの延在方向に沿って所定の狭ピッチで並設されている。 A front scanning wiring 8 is formed by extending one end of each scanning electrode 4 disposed on the inner surface of the glass substrate 2. These front scanning wires 8 are routed in a pattern that converges toward the center of the end corresponding to the protruding portion 1a of the glass substrate 2. As shown in FIG. 2, each of the front scanning wirings 8 includes a pair of inter-substrate connection pads 8a and 8a corresponding to the arrangement portions of the first seal portion 3A and the second seal portion 3B. Each is formed. These connection pads 8a are arranged in parallel at a predetermined narrow pitch along the extending direction of the corresponding seal portions 3A, 3B.
一方、ガラス基板１側には、上述の前側走査配線８に対応させて後側走査配線９が配設されている。これら後側走査配線９には、それぞれ、前側走査配線８の一対の接続パッド８ａに対応させて一対の被接続パッド９ａ、９ａが対向する位置に同じ大きさで形成されている。各後側走査配線９は、走査ドライバチップ６の配設エリアに向けて収斂するパターンに形成され、そのうちの一対の被接続パッド９ａ、９ａ間のパターンは、前側走査配線８の対応する部分と略同じパターンに形成されている。 On the other hand, on the glass substrate 1 side, rear scanning wirings 9 are arranged corresponding to the above-mentioned front scanning wirings 8. In these rear scanning lines 9, a pair of connected pads 9a and 9a are formed in the same size at positions facing each other so as to correspond to the pair of connection pads 8a of the front scanning line 8. Each rear scanning wiring 9 is formed in a pattern that converges toward the area where the scanning driver chip 6 is arranged, and the pattern between the pair of connected pads 9a, 9a is a portion corresponding to the corresponding part of the front scanning wiring 8. They are formed in substantially the same pattern.
上述のように配設された前側走査配線８と後側走査配線９は、ガラス基板１、２をシール材３によって接合することにより、シール材３中の導電性粒子を介して導通接続される。この場合、図３(ａ)に示すように、前側走査配線８とこれに対応する後側走査配線９とは、一対の接続パッド８ａ、８ａと被接続パッド９ａ、９ａが第１シール部３Ａの導電性粒子３ｂと第２シール部３Ｂ中の導電性粒子３ｂを介してそれぞれ導通接続され、並列回路を形成する。従って、各接続パッド８ａ及び各被接続パッド９ａの面積は、１箇所で導通接続する従来の場合に比べてその略半分程度に小さくできると共に、一対の接続パッド８ａ、８ａと被接続パッド９ａ、９ａ間の各走査配線８、９もより幅狭に形成できる。その結果、液晶表示素子の高精細化による配線の狭ピッチ化にも容易に対応することができる。 The front scanning wiring 8 and the rear scanning wiring 9 arranged as described above are conductively connected via the conductive particles in the sealing material 3 by joining the glass substrates 1 and 2 with the sealing material 3. . In this case, as shown in FIG. 3 (a), the front scanning wiring 8 and the rear scanning wiring 9 corresponding thereto have a pair of connection pads 8a and 8a and connected pads 9a and 9a as the first seal portion 3A. The conductive particles 3b and the conductive particles 3b in the second seal portion 3B are connected to each other to form a parallel circuit. Accordingly, the area of each connection pad 8a and each connected pad 9a can be reduced to about half that of the conventional case where conductive connection is made at one place, and a pair of connection pads 8a, 8a and connected pads 9a, The scanning wirings 8 and 9 between 9a can also be formed narrower. As a result, it is possible to easily cope with narrowing of the wiring pitch due to high definition of the liquid crystal display element.
また、第１シール部３Ａの外側の第２シール部３Ｂで囲まれた外縁領域Ｄfに配設されている前側走査配線８と後側走査配線９は、幅狭に形成できるためにその分引き回し自由度が増してパターン設計が容易になると共に、第１、第２シール３Ａ、３Ｂで囲まれた略閉空間内に配設されるから、保護膜等で被覆しなくても電食等による劣化が有効に防止される。 In addition, since the front scanning wiring 8 and the rear scanning wiring 9 disposed in the outer edge region Df surrounded by the second seal portion 3B outside the first seal portion 3A can be formed narrow, they are routed accordingly. The degree of freedom is increased and pattern design is facilitated, and since it is disposed in a substantially closed space surrounded by the first and second seals 3A and 3B, it can be caused by electrolytic corrosion without being covered with a protective film or the like. Degradation is effectively prevented.
後側走査配線９の走査ドライバチップ６の配設エリアに向けて延出された各先端部には接続端子９ｂが形成され、これら接続端子９ｂは走査ドライバチップ６の出力端子電極６ａ(図３(ａ)参照)に対応する位置に所定のピッチで並設されている。 Connection terminals 9b are formed at the tip portions of the rear scanning wiring 9 extending toward the area where the scanning driver chip 6 is disposed, and these connection terminals 9b are connected to the output terminal electrodes 6a (FIG. 3) of the scanning driver chip 6. are arranged in parallel at a predetermined pitch at a position corresponding to (a).
一方、図１に示されるように、各表示電極５に表示信号電圧を供給するための表示配線１０は、各表示電極５の端部から引き出された複数の表示配線１０が表示ドライバチップ７の配設エリアに向けて収斂するパターンでガラス基板１の内面上を引き回し配設されている。この場合、各表示配線１０は、各表示電極５の端部から第１シール部３Ａ外側の第２シール部３Ｂで囲まれた外縁領域Ｄfを通過させた後、表示ドライバチップ７の配設エリアに向けて引き回し配設されている。各表示配線１０の第１シール部３Ａと第２シール部３Ｂとの各交差位置には、図３(ｂ)に示すように、接続パッド１０ａがそれぞれ形成されている。各表示配線１０に一対づつ形成された接続パッド１０ａ、１０ａは、各シール部３Ａ、３Ｂの延在方向に沿って所定の狭ピッチで並設されている。 On the other hand, as shown in FIG. 1, the display wiring 10 for supplying the display signal voltage to each display electrode 5 has a plurality of display wirings 10 drawn from the end of each display electrode 5. It is arranged by being drawn around the inner surface of the glass substrate 1 in a pattern that converges toward the arrangement area. In this case, each display wiring 10 passes through the outer edge region Df surrounded by the second seal portion 3B outside the first seal portion 3A from the end portion of each display electrode 5, and then the arrangement area of the display driver chip 7 It is routed toward the head. As shown in FIG. 3B, a connection pad 10a is formed at each intersection position of the first seal portion 3A and the second seal portion 3B of each display wiring 10. A pair of connection pads 10a and 10a formed on each display wiring 10 are arranged in parallel at a predetermined narrow pitch along the extending direction of the seal portions 3A and 3B.
そして、上記外縁領域Ｄfにおけるガラス基板２の内面には、複数の表示配線１０に対応させて複数の迂回配線１１が配設されている。これら各迂回配線１１は、対応する表示配線１０における一対の接続パッド１０ａ、１０ａ間の配線部に重なるように略同じ線幅で略同じパターンにそれぞれ形成されている。各迂回配線１１の両端には、表示配線１０の接続パッド１０ａ、１０ａに対向させて被接続パッド１１ａ、１１ａがそれぞれ形成されている。 A plurality of bypass wirings 11 are arranged on the inner surface of the glass substrate 2 in the outer edge region Df so as to correspond to the plurality of display wirings 10. Each of the bypass wirings 11 is formed in substantially the same pattern with substantially the same line width so as to overlap the wiring portion between the pair of connection pads 10a and 10a in the corresponding display wiring 10. Connected pads 11 a and 11 a are formed at both ends of each bypass wiring 11 so as to face the connection pads 10 a and 10 a of the display wiring 10.
上述のように配設された表示配線１０と迂回配線１１は、ガラス基板１、２をシール材３によって接合することにより、シール材３中の導電性粒子を介して導通接続される。この場合、図３(ｂ)に示すように、表示配線１０とこれに対応する迂回配線１１とは、一対の接続パッド１０ａ、１０ａと被接続パッド１１ａ、１１ａが第１シール部３Ａの導電性粒子３ｂと第２シール部３Ｂ中の導電性粒子３ｂを介してそれぞれ導通接続され、並列回路を形成する。従って、並列回路部の表示配線１０と迂回配線１１の各線幅をより幅狭に形成できる。その結果、液晶表示素子の高精細化による配線の狭ピッチ化にも容易に対応することができる。 The display wiring 10 and the bypass wiring 11 arranged as described above are electrically connected through the conductive particles in the sealing material 3 by joining the glass substrates 1 and 2 with the sealing material 3. In this case, as shown in FIG. 3B, the display wiring 10 and the detour wiring 11 corresponding to the display wiring 10 include a pair of connection pads 10a and 10a and connected pads 11a and 11a that are electrically conductive to the first seal portion 3A. The particles 3b and the conductive particles 3b in the second seal portion 3B are electrically connected to each other to form a parallel circuit. Therefore, each line width of the display wiring 10 and the bypass wiring 11 in the parallel circuit portion can be formed narrower. As a result, it is possible to easily cope with narrowing of the wiring pitch due to high definition of the liquid crystal display element.
また、上記外縁領域Ｄfの表示配線１０と迂回配線１１は、第１、第２シール３Ａ、３Ｂで囲まれた閉空間内に配設されるから、保護膜等で被覆しなくても電食等による劣化が有効に防止される。 Further, since the display wiring 10 and the bypass wiring 11 in the outer edge region Df are disposed in a closed space surrounded by the first and second seals 3A and 3B, even if they are not covered with a protective film or the like. It is possible to effectively prevent the deterioration due to the
ガラス基板１、２間の第１シール部３Ａで囲まれた空間には、図３(ａ)、(ｂ)で示されるように、液晶１２が封入されている。液晶１２は、周知の真空注入法により図１に示される液晶注入穴３ｃから注入される。液晶注入穴３ｃは、液晶注入後に封止材１３が充填され封止されている。 As shown in FIGS. 3A and 3B, a liquid crystal 12 is sealed in a space surrounded by the first seal portion 3A between the glass substrates 1 and 2. The liquid crystal 12 is injected from the liquid crystal injection hole 3c shown in FIG. 1 by a known vacuum injection method. The liquid crystal injection hole 3c is filled and sealed with the sealing material 13 after the liquid crystal is injected.
走査ドライバチップ６は、図３(ａ)に示されるように、異方性導電接着材１４を介して、後側走査配線９の接続端子９ｂと走査信号電圧を入力するための入力配線端子１５が並設された配設エリアに導通設置されている。異方性導電接着材１４は、シール材３と同様に熱硬化性の絶縁樹脂基材１４ａ中に導電性粒子１４ｂが分散混合されてなる。走査ドライバチップ６をＣＯＧ搭載する際は、まず、走査ドライバチップ６を異方性導電接着材１４を介してその出力端子電極６ａ及び入力端子電極６ｂが対応する接続端子９ｂ及び入力配線端子１５上に重なる位置に正確に位置決めして載置し、次に、走査ドライバチップ６に熱圧着ツールを圧接させて異方性導電接着材１４を加熱しつつ押圧し、導電性粒子１４ｂを出力端子電極６ａ及び入力端子電極６ｂと対応する接続端子９ｂ及び入力配線端子１５とで挟持した状態で絶縁樹脂基材１４ａを硬化させる。これにより、走査ドライバチップ６が的確に所定の配設エリアへ導通設置される。 As shown in FIG. 3A, the scanning driver chip 6 is connected to the connection terminal 9b of the rear scanning wiring 9 and the input wiring terminal 15 for inputting the scanning signal voltage via the anisotropic conductive adhesive material 14. Are conductively installed in the arrangement area arranged side by side. The anisotropic conductive adhesive 14 is formed by dispersing and mixing conductive particles 14b in a thermosetting insulating resin base material 14a in the same manner as the sealing material 3. When the scanning driver chip 6 is mounted on the COG, first, the scanning driver chip 6 is placed on the connection terminal 9 b and the input wiring terminal 15 corresponding to the output terminal electrode 6 a and the input terminal electrode 6 b through the anisotropic conductive adhesive 14. Then, the anisotropic conductive adhesive 14 is heated and pressed while the thermal bonding tool is pressed against the scanning driver chip 6 to heat the conductive particle 14b to the output terminal electrode. The insulating resin base material 14a is cured while being sandwiched between the connection terminals 9b and the input wiring terminals 15 corresponding to the input terminals 6a and the input terminal electrodes 6b. As a result, the scanning driver chip 6 is accurately placed in a predetermined arrangement area.
表示ドライバチップ７も、図３(ｂ)に示されるように、走査ドライバチップ６と同様に、異方性導電接着材１４を介して、表示配線１０の接続端子１０ｂと表示信号電圧を入力するための入力配線端子１６が並設された配設エリアにＣＯＧ方式で導通設置されている。 As shown in FIG. 3B, the display driver chip 7 also inputs the display signal voltage to the connection terminal 10 b of the display wiring 10 through the anisotropic conductive adhesive 14, similarly to the scanning driver chip 6. For this purpose, the input wiring terminals 16 are installed in a conductive area by the COG method.
以上のように、本実施形態の液晶表示素子においては、走査電極４と対向基板側に設置された走査ドライバチップ６とを電気接続するための基板間導通回路を、両ガラス基板１、２の前側走査配線８と後側走査配線９にそれぞれ形成された各一対の接続パッド８ａ、８ａと被接続パッド９ａ、９ａとを第１シール部３Ａと第２シール部３Ｂを介して導通接続する並列回路に構成したから、従来の１箇所での基板間導通構造に比べて接続パッド８ａ及び被接続パッド９ａの各々の面積を小さくできるとともに並列回路をなす基板間導通部の各配線８、９を幅狭に形成でき、液晶表示素子の高精細化に伴う配線の狭ピッチ化に充分に対応可能となる。 As described above, in the liquid crystal display element of the present embodiment, the inter-substrate conduction circuit for electrically connecting the scan electrode 4 and the scan driver chip 6 installed on the counter substrate side is provided on both the glass substrates 1 and 2. A pair of connection pads 8a, 8a and connected pads 9a, 9a respectively formed on the front scanning wiring 8 and the rear scanning wiring 9 are connected in parallel via the first seal portion 3A and the second seal portion 3B. Since the circuit is configured, the respective areas of the connection pads 8a and the pads 9a to be connected can be reduced as compared with the conventional inter-substrate conduction structure in one place, and the wirings 8 and 9 of the inter-substrate conduction part forming a parallel circuit are provided. It can be formed with a narrow width, and can sufficiently cope with a narrow pitch of wiring due to high definition of the liquid crystal display element.
また、並列回路を構成する基板間導通部の配線８、９がシール材３の第１シール部３Ａと第２シール部３Ｂで囲まれた外縁領域Ｄf内に配設されるから、それら配線８、９は保護膜が被覆されなくても電食等による劣化が有効に防止され、その結果、液晶表示素子の信頼性が向上する。
（第２実施形態）
次に、本発明の第２実施形態について、図４に基づき説明する。なお、上記第１実施形態と同一の構成要素については同一の符号を付して、その説明を省略する。
In addition, since the wirings 8 and 9 of the inter-substrate conducting portion constituting the parallel circuit are disposed in the outer edge region Df surrounded by the first seal portion 3A and the second seal portion 3B of the sealing material 3, the wiring 8 , 9 can be effectively prevented from being deteriorated by electrolytic corrosion or the like without being covered with a protective film, and as a result, the reliability of the liquid crystal display element is improved.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected about the component same as the said 1st Embodiment, and the description is abbreviate | omitted.
本実施形態では、前側走査配線２１と後側走査配線２２にそれぞれ接続パッド２１ａと被接続パッド２２ａが１個づつ形成され、接続パッド２１ａと被接続パッド２２ａによる基板間導通部が隣接する配線同士で互いに異なるシール部に形成されている。 In the present embodiment, one connection pad 21a and one connection pad 22a are formed on the front scanning wiring 21 and the rear scanning wiring 22, respectively, and wirings adjacent to each other by the connection pad 21a and the connection pad 22a are adjacent to each other. The seal portions are different from each other.
すなわち、ガラス基板２における隣り合う一対の前側走査配線２１、２１のうちの、一方の前側走査配線２１には接続パッド２１ａが第１シール部３Ａと交差する部分に形成され、他方の前側走査配線２１には接続パッド２１ａが第２シール部３Ｂと交差する部分(先端部)に形成され、この構成が繰り返されて複数の接続パッド２１ａが千鳥配置で形成されている。対向側のガラス基板１においても、各後側走査配線２２に被接続パッド２２ａが上述の接続パッド２１ａに対応して同様に千鳥配置で形成されている。 That is, of the pair of adjacent front scanning lines 21, 21 on the glass substrate 2, one front scanning line 21 has a connection pad 21 a formed at a portion intersecting the first seal portion 3 </ b> A, and the other front scanning line 21. The connection pad 21a is formed in the part (tip part) which cross | intersects the 2nd seal | sticker part 3B in 21, and this structure is repeated and the several connection pad 21a is formed in zigzag arrangement. Also in the glass substrate 1 on the opposite side, the connection pads 22a are similarly formed in a staggered arrangement corresponding to the above-described connection pads 21a on each rear scanning wiring 22.
そして、千鳥配置で形成されたこれら接続パッド２１ａと被接続パッド２２ａとは、第１シール部３Ａ或いは第２シール部３Ｂ中の導電性粒子(不図示)を介して導通接続される。その他の構成は、上記第１実施形態と同様である。 The connection pads 21a and the connection pads 22a formed in a staggered arrangement are conductively connected via conductive particles (not shown) in the first seal portion 3A or the second seal portion 3B. Other configurations are the same as those in the first embodiment.
上述のように構成された本実施形態の液晶表示素子によれば、各走査配線に設けられる基板間導通部が１箇所であるから、接続パッド２１ａと被接続パッド２２ａの各面積を上記第１実施形態のように小さくすることは難しいが、基板間導通部が千鳥に配設されているから、配線ピッチが上記第１実施形態と同様に狭ピッチである高精細液晶表示素子の場合も、接続パッド２１ａと被接続パッド２２ａの個々の面積を上記第１実施形態の場合よりも大きく確保することができる。その結果、狭ピッチ配線であっても接続パッド２１ａと被接続パッド２２ａを容易に位置合わせして確実に導通接続でき、基板間導通部での接続不良の発生が顕著に抑制されて製品歩留りが向上する。 According to the liquid crystal display element of the present embodiment configured as described above, since there is one inter-substrate conduction portion provided in each scanning wiring, each area of the connection pad 21a and the connection pad 22a is set to the first area. Although it is difficult to make it small as in the embodiment, since the inter-substrate conductive portions are arranged in a staggered manner, even in the case of a high-definition liquid crystal display element in which the wiring pitch is narrow as in the first embodiment, The individual areas of the connection pad 21a and the connection pad 22a can be secured larger than in the case of the first embodiment. As a result, even if it is a narrow pitch wiring, the connection pad 21a and the pad 22a to be connected can be easily aligned and reliably connected, and the occurrence of connection failure in the inter-substrate conductive portion is remarkably suppressed, and the product yield is increased. improves.
なお、本発明は、上記の実施形態に限定されるものではない。例えば、本発明は、上記実施形態のように走査電極の配線を基板間導通させる液晶表示素子に限らず、表示電極の配線を基板間導通させる液晶表示素子にも有効に適用される。 In addition, this invention is not limited to said embodiment. For example, the present invention is not limited to a liquid crystal display element that conducts scanning electrode wiring between substrates as in the above-described embodiment, but is also effectively applied to a liquid crystal display element that conducts display electrode wiring between substrates.
また、上記第１実施形態では表示電極の配線にも配線幅を狭くするために両ガラス基板に跨る並列回路部を設けたが、このように電極とそれにそれに電圧を供給するドライバチップが同一基板上に設けられている電極の配線は、敢えて両基板に跨る並列回路部を設けずに一方の基板だけでストレートに配設してもよい。 In the first embodiment, the display electrode wiring is also provided with a parallel circuit portion extending over both glass substrates in order to reduce the wiring width. In this way, the electrode and the driver chip for supplying voltage thereto are provided on the same substrate. The wiring of the electrodes provided on the upper side may be arranged straight on only one substrate without providing a parallel circuit section straddling both substrates.
さらに、上記実施形態では第２シール部で囲まれた第１シール部の外縁領域Ｄfは空洞としたが、この外縁領域Ｄfにも液晶を封入してもよい。これにより、外縁領域Ｄfに配設されている各配線の電食等による劣化がより確実に防止される。 Furthermore, in the above embodiment, the outer edge region Df of the first seal portion surrounded by the second seal portion is a cavity, but liquid crystal may be sealed in the outer edge region Df. Thereby, deterioration due to electrolytic corrosion or the like of each wiring arranged in the outer edge region Df is more reliably prevented.
１、２ ガラス基板
３ シール材
３Ａ 第１シール部
３Ｂ 第２シール部
４ 走査電極
５ 表示電極
６ 走査ドライバチップ
７ 表示ドライバチップ
８、２１ 前側走査配線
８ａ、１０ａ、２１ａ 接続パッド
９、２２ 後側走査配線
９ａ、１１ａ、２２ａ 被接続パッド
１０ 表示配線
１１ 迂回配線
１２ 液晶
１３ 封止材
１４ 異方性導電接着材
１５、１６ 入力配線端子
DESCRIPTION OF SYMBOLS 1, 2 Glass substrate 3 Sealing material 3A 1st seal | sticker part 3B 2nd seal | sticker part 4 Scan electrode 5 Display electrode 6 Scan driver chip 7 Display driver chip 8, 21 Front scan wiring 8a, 10a, 21a Connection pad 9, 22 Rear side Scanning wiring 9a, 11a, 22a Connected pad 10 Display wiring 11 Detour wiring 12 Liquid crystal 13 Sealing material 14 Anisotropic conductive adhesive 15, 16 Input wiring terminal
Claims (4)
複数の第２の電極、これらの第２の電極にそれぞれ接続され、前記複数の第２の電極に電圧を供給するための複数の第２配線、前記第１接続パッドにそれぞれ対応させて設けられた複数の第１被接続パッド、及びこれらの第１被接続パッドにそれぞれ電圧を供給する複数の後側第１配線が形成された第２の基板と、
絶縁樹脂基材中に導電性粒子を含有させてなり、前記第１の基板及び前記第２の基板をそれぞれの電極形成面を対向させて所定の間隙を保ち接合する接合部材と、
前記第１の基板及び前記第２の基板の対向する各内面と前記接合部材とで囲まれる空間に封入された液晶とからなる液晶表示素子であって、
前記接合部材は、前記第１の電極と前記第２の電極とが前記液晶を介して対向する領域毎に形成された複数の画素からなる表示領域を内側に囲む枠状の第１シール部と、該第１シール部の外側の所定の領域を囲む第２シール部とを備え、
前記第１接続パッドとこれに対応する前記第１被接続パッドとは、前記第１シール部と前記第２シール部のうちの少なくとも一方のシール部に対応させて配設され、前記導電性粒子を介し導通接続されていることを特徴とする液晶表示素子。 A plurality of first electrodes, a plurality of front first wirings connected to each of the first electrodes and supplying a voltage to the plurality of first electrodes, and a front first wiring of the plurality of first electrodes. A first substrate having a first connection pad formed thereon;
A plurality of second electrodes, respectively connected to these second electrodes, and provided corresponding to a plurality of second wirings for supplying a voltage to the plurality of second electrodes and the first connection pads, respectively. A plurality of first connected pads, and a second substrate on which a plurality of rear first wirings for supplying a voltage to each of the first connected pads are formed,
A bonding member containing conductive particles in an insulating resin base material, and bonding the first substrate and the second substrate with their electrode formation surfaces facing each other while maintaining a predetermined gap;
A liquid crystal display element comprising liquid crystal sealed in a space surrounded by each of the opposing inner surfaces of the first substrate and the second substrate and the bonding member,
The bonding member includes a frame-shaped first seal portion that encloses a display region including a plurality of pixels formed in each region where the first electrode and the second electrode are opposed to each other through the liquid crystal. A second seal portion surrounding a predetermined region outside the first seal portion,
The first connection pad and the first connected pad corresponding to the first connection pad are arranged corresponding to at least one of the first seal portion and the second seal portion, and the conductive particles A liquid crystal display element, wherein the liquid crystal display element is conductively connected through the substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2005047119A JP4714480B2 (en) | 2005-02-23 | 2005-02-23 | Liquid crystal display element |
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| JP2005047119A JP4714480B2 (en) | 2005-02-23 | 2005-02-23 | Liquid crystal display element |
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| JP4714480B2 true JP4714480B2 (en) | 2011-06-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8778183B2 (en) | 2010-01-26 | 2014-07-15 | Awa Paper Mfg. Co., Ltd. | Filtering apparatus |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4518199B2 (en) * | 2007-10-23 | 2010-08-04 | エプソンイメージングデバイス株式会社 | Electro-optic device |
| JP4916578B2 (en) * | 2008-10-07 | 2012-04-11 | シャープ株式会社 | Display device, manufacturing method thereof, and active matrix substrate |
| US8964159B2 (en) * | 2010-05-18 | 2015-02-24 | Sharp Kabushiki Kaisha | Display device and method for manufacturing the same |
| TWI472856B (en) * | 2012-07-12 | 2015-02-11 | Au Optronics Corp | Display apparatus |
| JP6502638B2 (en) * | 2014-09-10 | 2019-04-17 | 株式会社ジャパンディスプレイ | Liquid crystal display device and mother substrate |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS6039617A (en) * | 1983-08-12 | 1985-03-01 | Hitachi Ltd | Lead-out terminal structure of liquid-crystal display element |
| JPH01152425A (en) * | 1987-12-09 | 1989-06-14 | Oki Electric Ind Co Ltd | Structure of external fetching terminal |
| JPH01152426A (en) * | 1987-12-09 | 1989-06-14 | Oki Electric Ind Co Ltd | Structure of external fetching terminal for color liquid crystal display element |
| JPH1010551A (en) * | 1996-06-21 | 1998-01-16 | Casio Comput Co Ltd | Liquid crystal display element |
| JPH11284302A (en) * | 1998-03-27 | 1999-10-15 | Canon Inc | Connecting terminal structure of circuit board |
| JP2000321589A (en) * | 1999-05-12 | 2000-11-24 | Casio Comput Co Ltd | Display panel |
| JP2003215629A (en) * | 2002-01-25 | 2003-07-30 | Kyocera Corp | Liquid crystal display device and portable terminal or display equipment |
| JP2004086132A (en) * | 2002-06-28 | 2004-03-18 | Sharp Corp | Liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8778183B2 (en) | 2010-01-26 | 2014-07-15 | Awa Paper Mfg. Co., Ltd. | Filtering apparatus |
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