JP4658974B2 - キャビティの形成された基板製造方法 - Google Patents
キャビティの形成された基板製造方法 Download PDFInfo
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- JP4658974B2 JP4658974B2 JP2007007727A JP2007007727A JP4658974B2 JP 4658974 B2 JP4658974 B2 JP 4658974B2 JP 2007007727 A JP2007007727 A JP 2007007727A JP 2007007727 A JP2007007727 A JP 2007007727A JP 4658974 B2 JP4658974 B2 JP 4658974B2
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
320 内層回路
330 絶縁層
335 インタースティシャルビアホール(IVH:Interstitial Via Hole)
340 外層回路
350 フォトソルダレジスト
360 ボンディングパット
Claims (3)
- (a)上部シード層に上層回路を形成する段階と、
(b)前記上部シード層のキャビティの形成される領域にドライフィルムを積層する段階と、
(c)前記上部シード層の上面、前記上層回路の上面及び側面に絶縁層を形成して上部外層を製造する段階と、
(d)前記上部外層を内層回路が形成されたコア層の一面に積層する段階と、
(e)前記上部シード層を除去する段階と、
(f)前記ドライフィルムを除去して前記キャビティを形成する段階と、
を含むキャビティの形成された基板製造方法。 - (g)下部シード層に下層回路を形成する段階と、
(h)前記下部シード層の上面、前記下層回路の上面及び側面に絶縁層を積層して下部外層を形成する段階と、
(i)前記下部外層を前記内層回路が形成されたコア層の他面に積層する段階と、
(j)前記下部シード層を除去する段階と、
をさらに含むことを特徴とする請求項1に記載のキャビティの形成された基板製造方法。 - (m)前記キャビティの中に、半導体チップと電気的に結合するボンディングパットを形成する段階をさらに含むことを特徴とする請求項1または請求項2に記載のキャビティの形成された基板製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060014918A KR100659510B1 (ko) | 2006-02-16 | 2006-02-16 | 캐비티가 형성된 기판 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007221110A JP2007221110A (ja) | 2007-08-30 |
JP4658974B2 true JP4658974B2 (ja) | 2011-03-23 |
Family
ID=37814939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007007727A Expired - Fee Related JP4658974B2 (ja) | 2006-02-16 | 2007-01-17 | キャビティの形成された基板製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7858437B2 (ja) |
JP (1) | JP4658974B2 (ja) |
KR (1) | KR100659510B1 (ja) |
CN (1) | CN100481357C (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100898977B1 (ko) | 2007-11-07 | 2009-05-25 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
KR100974654B1 (ko) * | 2007-11-23 | 2010-08-09 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
KR101085436B1 (ko) * | 2010-03-10 | 2011-11-21 | 주식회사 심텍 | 릴리즈(Release) 필름을 이용하는 캐비티(Cavity) 피시비(PCB) 제조 방법 |
US9716193B2 (en) | 2012-05-02 | 2017-07-25 | Analog Devices, Inc. | Integrated optical sensor module |
US8946879B2 (en) | 2012-07-27 | 2015-02-03 | Analog Devices, Inc. | Packages and methods for 3D integration including two stacked dies with a portion of one die extending into a hole of the other die |
KR102011840B1 (ko) * | 2012-10-19 | 2019-08-19 | 해성디에스 주식회사 | 회로기판과 칩 패키지의 제조방법 및 그 방법으로 제조된 회로기판 |
US10884551B2 (en) | 2013-05-16 | 2021-01-05 | Analog Devices, Inc. | Integrated gesture sensor module |
CN105101680B (zh) * | 2014-05-22 | 2018-03-16 | 深南电路有限公司 | 一种电路板的加工方法 |
US9731959B2 (en) | 2014-09-25 | 2017-08-15 | Analog Devices, Inc. | Integrated device packages having a MEMS die sealed in a cavity by a processor die and method of manufacturing the same |
US9533878B2 (en) | 2014-12-11 | 2017-01-03 | Analog Devices, Inc. | Low stress compact device packages |
US10712197B2 (en) | 2018-01-11 | 2020-07-14 | Analog Devices Global Unlimited Company | Optical sensor package |
WO2019207884A1 (ja) * | 2018-04-26 | 2019-10-31 | 京セラ株式会社 | 電子素子実装用基板、電子装置、および電子モジュール |
US11296005B2 (en) | 2019-09-24 | 2022-04-05 | Analog Devices, Inc. | Integrated device package including thermally conductive element and method of manufacturing same |
CN112770495B (zh) * | 2019-10-21 | 2022-05-27 | 宏启胜精密电子(秦皇岛)有限公司 | 全向内埋模组及制作方法、封装结构及制作方法 |
CN110996510B (zh) * | 2019-12-31 | 2021-04-23 | 生益电子股份有限公司 | 一种阶梯槽制作方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01282892A (ja) * | 1988-05-09 | 1989-11-14 | Nec Corp | 多層印刷配線板の製造方法 |
JPH0936549A (ja) * | 1995-07-17 | 1997-02-07 | Nec Corp | ベアチップ実装用プリント基板 |
JP2003243837A (ja) * | 2002-02-20 | 2003-08-29 | Sumitomo Bakelite Co Ltd | 多層配線板 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07326865A (ja) * | 1994-05-31 | 1995-12-12 | Risho Kogyo Co Ltd | 電子部品搭載用の凹部を有する多層回路基板の製造方法 |
DE69626747T2 (de) * | 1995-11-16 | 2003-09-04 | Matsushita Electric Industrial Co., Ltd. | Gedruckte Leiterplatte und ihre Anordnung |
JP3382482B2 (ja) * | 1996-12-17 | 2003-03-04 | 新光電気工業株式会社 | 半導体パッケージ用回路基板の製造方法 |
US6242079B1 (en) * | 1997-07-08 | 2001-06-05 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
JP3547327B2 (ja) * | 1998-11-02 | 2004-07-28 | 松下電器産業株式会社 | セラミック多層基板の製造方法 |
EP2265101B1 (en) * | 1999-09-02 | 2012-08-29 | Ibiden Co., Ltd. | Printed circuit board and method of manufacturing printed circuit board |
JP3534405B1 (ja) * | 2002-11-28 | 2004-06-07 | 鐘淵化学工業株式会社 | 耐熱性フレキシブル積層板の製造方法およびこれにより製造される耐熱性フレキシブル積層板 |
US7440571B2 (en) * | 2002-12-03 | 2008-10-21 | Nagravision S.A. | Method for securing software updates |
JP4099057B2 (ja) * | 2002-12-27 | 2008-06-11 | 三井金属鉱業株式会社 | リチウムイオン電池内のコバルト回収方法およびコバルト回収システム |
EP1601017A4 (en) * | 2003-02-26 | 2009-04-29 | Ibiden Co Ltd | MULTILAYER PRINTED PCB |
KR100516762B1 (ko) * | 2003-06-11 | 2005-09-22 | 삼성전기주식회사 | 솔더 도금법을 이용한 c2bga 인쇄회로기판의 제조방법 |
JP2005129899A (ja) | 2003-08-28 | 2005-05-19 | Kyocera Corp | 配線基板および半導体装置 |
JP2005236194A (ja) | 2004-02-23 | 2005-09-02 | Cmk Corp | プリント配線板の製造方法 |
JP4361826B2 (ja) * | 2004-04-20 | 2009-11-11 | 新光電気工業株式会社 | 半導体装置 |
KR100633855B1 (ko) * | 2005-09-22 | 2006-10-16 | 삼성전기주식회사 | 캐비티가 형성된 기판 제조 방법 |
-
2006
- 2006-02-16 KR KR1020060014918A patent/KR100659510B1/ko not_active IP Right Cessation
-
2007
- 2007-01-17 JP JP2007007727A patent/JP4658974B2/ja not_active Expired - Fee Related
- 2007-02-15 CN CNB2007100793501A patent/CN100481357C/zh not_active Expired - Fee Related
- 2007-02-15 US US11/706,186 patent/US7858437B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01282892A (ja) * | 1988-05-09 | 1989-11-14 | Nec Corp | 多層印刷配線板の製造方法 |
JPH0936549A (ja) * | 1995-07-17 | 1997-02-07 | Nec Corp | ベアチップ実装用プリント基板 |
JP2003243837A (ja) * | 2002-02-20 | 2003-08-29 | Sumitomo Bakelite Co Ltd | 多層配線板 |
Also Published As
Publication number | Publication date |
---|---|
KR100659510B1 (ko) | 2006-12-20 |
JP2007221110A (ja) | 2007-08-30 |
CN100481357C (zh) | 2009-04-22 |
US20070190764A1 (en) | 2007-08-16 |
US7858437B2 (en) | 2010-12-28 |
CN101026099A (zh) | 2007-08-29 |
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