JP4653704B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4653704B2
JP4653704B2 JP2006211156A JP2006211156A JP4653704B2 JP 4653704 B2 JP4653704 B2 JP 4653704B2 JP 2006211156 A JP2006211156 A JP 2006211156A JP 2006211156 A JP2006211156 A JP 2006211156A JP 4653704 B2 JP4653704 B2 JP 4653704B2
Authority
JP
Japan
Prior art keywords
region
drift
conductivity type
drift region
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006211156A
Other languages
Japanese (ja)
Other versions
JP2006303543A (en
Inventor
良孝 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kansai Electric Power Co Inc
Original Assignee
Kansai Electric Power Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kansai Electric Power Co Inc filed Critical Kansai Electric Power Co Inc
Priority to JP2006211156A priority Critical patent/JP4653704B2/en
Publication of JP2006303543A publication Critical patent/JP2006303543A/en
Application granted granted Critical
Publication of JP4653704B2 publication Critical patent/JP4653704B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Thin Film Transistor (AREA)

Description

本発明は、半導体装置に関し、特に高耐圧のパワー半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a high breakdown voltage power semiconductor device.

炭化珪素（以下、ＳｉＣと記す）に代表されるワイドギャップ半導体材料は、珪素（以下、Ｓｉと記す）の半導体材料に比べて絶縁破壊電界強度が大きいためにＳｉの場合と同じ不純物濃度でより高い耐圧を実現できる。更に、低損失を保ちつつ高耐圧にでき、且つ２５０℃以上の高温でも動作し、熱伝導も良いという利点があり、次世代のパワー半導体の材料として期待されている。   A wide gap semiconductor material typified by silicon carbide (hereinafter referred to as SiC) has a higher dielectric breakdown field strength than a semiconductor material of silicon (hereinafter referred to as Si), and therefore has the same impurity concentration as that of Si. High breakdown voltage can be realized. Furthermore, it has the advantages of being able to have a high breakdown voltage while maintaining a low loss, operating at a high temperature of 250 ° C. or higher, and having good heat conduction, and is expected as a material for next-generation power semiconductors.

このＳｉＣを用いた、図１５に示すような構造のパワーＭＯＳＦＥＴが、１９９８年出版の論文集であるProceedings of the 10th International Symposium on Power Semiconductor Devices & ICs の１１９頁から１２２頁に示されている（非特許文献１）。このパワーＭＯＳＦＥＴはトレンチゲート型ＭＯＳＦＥＴと呼ばれており、ｎ型ＳｉＣ半導体基板１０１の上にエピタキシャル法でｎ型ドリフト層１０２が形成される。ｎ型ドリフト層１０２の上にｐ型ボディ領域１０３が形成され、更に、ｐ型ボディ層の所定領域にｎ型ソース領域１０４が形成されている。ｎ型ソース領域１０４とｐ型ボディ領域１０３からｎ型ドリフト領域１０２に達する凹部１１０が形成され、凹部１１０にゲート絶縁膜１０５を介してゲート電極１０６が形成されている。ｎ型ソース領域１０４の上にはソース電極１０７が形成されている。またｎ型ＳｉＣ半導体基板の下面にはドレイン電極１０８が形成されている。   A power MOSFET having such a structure as shown in FIG. 15 using SiC is shown on pages 119 to 122 of Proceedings of the 10th International Symposium on Power Semiconductor Devices & ICs published in 1998. Non-patent document 1). This power MOSFET is called a trench gate type MOSFET, and an n type drift layer 102 is formed on an n type SiC semiconductor substrate 101 by an epitaxial method. A p-type body region 103 is formed on the n-type drift layer 102, and an n-type source region 104 is formed in a predetermined region of the p-type body layer. A recess 110 reaching the n-type drift region 102 from the n-type source region 104 and the p-type body region 103 is formed, and a gate electrode 106 is formed in the recess 110 with a gate insulating film 105 interposed therebetween. A source electrode 107 is formed on the n-type source region 104. A drain electrode 108 is formed on the lower surface of the n-type SiC semiconductor substrate.

ソースＳとドレインＤ間にキャリアを流すチャネルは以下のようにして形成される。すなわちゲート電極１０６に電圧を印加し、ゲート電極１０６と凹部１１０の側壁部分のｐ型ボディ領域１０３とに挟まれたゲート絶縁膜１０５に電界を与える。これにより、ゲート絶縁膜１０５に接するｐ型ボディ領域１０３の表面付近の導電型がｎ型に反転しチャネルが形成される。この構造により、ＳｉのパワーＭＯＳＦＥＴの理論限界を超えた性能、すなわち、耐圧１４００Ｖで単位面積あたり３１１ｍΩｃｍ２の低いオン抵抗が得られる。 A channel for flowing carriers between the source S and the drain D is formed as follows. That is, a voltage is applied to the gate electrode 106 to apply an electric field to the gate insulating film 105 sandwiched between the gate electrode 106 and the p-type body region 103 on the side wall of the recess 110. As a result, the conductivity type in the vicinity of the surface of p-type body region 103 in contact with gate insulating film 105 is inverted to n-type to form a channel. With this structure, performance exceeding the theoretical limit of a Si power MOSFET, that is, a low on-resistance of 311 mΩcm 2 per unit area at a withstand voltage of 1400 V can be obtained.

近年、高耐圧パワー出力素子に制御回路や保護回路を組合せて一体化した高耐圧パワーＩＣの開発・実用化が進められ、高耐圧半導体装置の小型化・インテリジェント化に貢献している。高耐圧パワーＩＣの出力素子の種類としては低損失化の点からＩＧＢＴやサイリスタに代表されるバイポーラ半導体装置が注目されている。バイポーラ半導体装置は電導度変調の効果により、ＭＯＳＦＥＴやＳＩＴに代表されるモノポーラ半導体装置に比べて半導体装置の内部抵抗を大幅に低減でき、大幅な低損失化が図れるという利点がある。高耐圧パワー出力素子の構造としては縦型構造と横型構造があるが、制御回路などとの組合せや集積化が容易な点から主に横型構造が採用されている。図１６はＳｉを用いて構成された典型的な横型構造のＩＧＢＴであり、１９９６年に開催された国際学会の論文集Proceedings of the ８th International Symposium on Power Semiconductor Devices & ICs の１０１頁から１０４頁に渡って開示されている（非特許文献２）。   In recent years, development and practical use of high voltage power ICs in which a control circuit and a protection circuit are combined and integrated with a high voltage power output element have been promoted and contributed to miniaturization and intelligentization of high voltage semiconductor devices. As a type of output element of the high voltage power IC, a bipolar semiconductor device represented by an IGBT or a thyristor has attracted attention from the viewpoint of reducing the loss. Bipolar semiconductor devices have the advantage that due to the effect of conductivity modulation, the internal resistance of the semiconductor device can be greatly reduced compared to a monopolar semiconductor device represented by MOSFET or SIT, and the loss can be greatly reduced. The structure of the high withstand voltage power output element includes a vertical structure and a horizontal structure, but the horizontal structure is mainly adopted from the viewpoint of easy combination and integration with a control circuit. FIG. 16 shows a typical lateral structure IGBT composed of Si, which is shown in pages 101 to 104 of the Proceedings of the 8th International Symposium on Power Semiconductor Devices & ICs held in 1996. It has been disclosed (Non-Patent Document 2).

前記のＩＧＢＴは、Ｓｉ基板２０１の上にＳｉＯ２絶縁膜２１３を形成し、ついでｎ型ドリフト領域２０２を積層している。積層されたドリフト領域２０２の右端にｐ型ボディ領域２０４が形成され、その内部にｎ型エミッタ領域２０５とｐ型コンタクト領域２１４が形成されている。エミッタ領域２０５にエミッタ電極２１８が形成され、コンタクト領域２１４にベース電極２２０が形成されている。また、ゲート酸化膜２１０を介してｐ型ボディ領域２０４の上にゲート電極２１１が設けられている。ドリフト領域２０２の左端にはｎ型バッファー領域２０６、ｐ型コレクタ領域２０７及びアノード電極２１９が順次設けられている。 In the IGBT, a SiO 2 insulating film 213 is formed on a Si substrate 201 and then an n-type drift region 202 is laminated. A p-type body region 204 is formed at the right end of the stacked drift region 202, and an n-type emitter region 205 and a p-type contact region 214 are formed therein. An emitter electrode 218 is formed in the emitter region 205, and a base electrode 220 is formed in the contact region 214. A gate electrode 211 is provided on the p-type body region 204 via the gate oxide film 210. At the left end of the drift region 202, an n-type buffer region 206, a p-type collector region 207, and an anode electrode 219 are sequentially provided.

このＩＧＢＴのオフ時の動作は次のとおりである。アノード電極２１９の電位がエミッター電極２１８の電位より高い状態になるように高電圧を印加した時、ｐ型ボディ領域２０４とｎ型ドリフト領域２０２で形成する接合が逆バイアスされ空乏層が主にｎ型ドリフト領域２０２内に拡がる。空乏層内の電界は接合付近で最大となりｎ型バッファー領域２０６に向かって漸減している。印加電圧を更に高くすると空乏層は更にｎ型バッファー領域２０６に向かって拡がり上記の接合付近の最大電界も高くなってゆく。最大電界がＳｉＣの絶縁破壊電界である約０．３ＭＶ／ｃｍに達する印加電圧がこのＩＧＢＴの降伏耐圧である。   The operation of the IGBT when it is off is as follows. When a high voltage is applied so that the potential of the anode electrode 219 is higher than the potential of the emitter electrode 218, the junction formed by the p-type body region 204 and the n-type drift region 202 is reverse-biased so that the depletion layer is mainly n It extends into the mold drift region 202. The electric field in the depletion layer becomes maximum near the junction and gradually decreases toward the n-type buffer region 206. When the applied voltage is further increased, the depletion layer further expands toward the n-type buffer region 206, and the maximum electric field in the vicinity of the junction increases. The applied voltage at which the maximum electric field reaches about 0.3 MV / cm, which is a dielectric breakdown electric field of SiC, is the breakdown voltage of the IGBT.

一方、オン時の動作は次のとおりである。アノード電極２１９の電位がエミッタ電極２１８の電位より高くなるように電圧を印加した状態でゲート電極２１１にしきい値電圧以上の高い電圧を印加すると、ゲート電極２１１の下のｐ型ボディ領域２０４の表面に電子が集められ反転層が形成される。その結果、ｎ型エミッタ領域２０５から反転層を経て電子が流れる。この電子の一部はｎ型ドリフト領域２０２を通ってｎ型バッファー領域２０６に達し、ｐ型コレクタ領域２０７からの正孔の注入を促す。注入された正孔はｎ型ドリフト領域２０２を通ってｐ型ボディ領域２０４に達しエミッタ電極２１８から流出する。このとき、ｎ型ドリフト領域２０２内には電子と正孔の両方が存在することになり伝導度変調が生じる。これによりドリフト領域の抵抗を著しく低減させることができる。その結果、ＭＯＳＦＥＴに比べて高耐圧であるにもかかわらず低オン抵抗すなわち低損失の半導体装置が実現できる。   On the other hand, the operation when on is as follows. When a voltage higher than the threshold voltage is applied to the gate electrode 211 in a state where a voltage is applied so that the potential of the anode electrode 219 is higher than the potential of the emitter electrode 218, the surface of the p-type body region 204 below the gate electrode 211. Electrons are collected on the inversion layer. As a result, electrons flow from the n-type emitter region 205 through the inversion layer. Some of these electrons pass through the n-type drift region 202 and reach the n-type buffer region 206, prompting the injection of holes from the p-type collector region 207. The injected holes reach the p-type body region 204 through the n-type drift region 202 and flow out of the emitter electrode 218. At this time, both electrons and holes exist in the n-type drift region 202, and conductivity modulation occurs. Thereby, the resistance of the drift region can be significantly reduced. As a result, it is possible to realize a semiconductor device having a low on-resistance, that is, a low loss despite having a higher breakdown voltage than that of the MOSFET.

本従来例の降伏電圧は３４０Ｖ、電流容量は２Ａである。２００Ａ／ｃｍ２の電流密度でのオン電圧は２．０Ｖであり、ビルトイン電圧より高い電圧範囲でのオン抵抗は４６．６ｍΩｃｍ２である。
１９９８年出版の論文集であるProceedings of the 10th International Symposium on Power Semiconductor Devices & ICs の１１９頁から１２２頁 １９９６年に開催された国際学会の論文集Proceedings of the ８th International Symposium on Power Semiconductor Devices & ICs の１０１頁から１０４頁 The breakdown voltage of this conventional example is 340V, and the current capacity is 2A. The on-voltage at a current density of 200 A / cm 2 is 2.0 V, and the on-resistance in a voltage range higher than the built-in voltage is 46.6 mΩcm 2 .
Pp. 119-122 of the 1998 Proceedings of the 10th International Symposium on Power Semiconductor Devices & ICs Pages 101-104 of the Proceedings of the 8th International Symposium on Power Semiconductor Devices & ICs held in 1996

半導体装置を、産業用の大容量インバータや新幹線及び電車などの電鉄用途のインバータ、あるいは電力事業用電力変換装置等に用いるには、更に高耐圧で低損失のものが必要とされる。しかし、図１５のようなトレンチゲート型ＭＯＳＦＥＴで高耐圧化を図ろうとすると、ドレイン領域の不純物濃度を下げて空乏層を拡げ電界を低減させる必要がある。その結果、ドレイン領域の抵抗が大きくなり、半導体装置をオンさせて電流を流す際のオン抵抗が高くなり低損失化が困難になる。また、凹部１１０の底部に電界が集中しやすく、高耐圧化が難しい。ＳｉＣやＳｉを用いた半導体装置では、絶縁破壊電界が高いために通常ドリフト層１０２の不純物濃度を高くしてオン抵抗を低くするが、その場合は凹部１１０の底部のゲート絶縁膜１０５の電界が高くなり、高耐圧化が難しい。   In order to use a semiconductor device for an industrial high-capacity inverter, an inverter for electric railways such as a Shinkansen and a train, or a power conversion device for electric power business, a device with higher withstand voltage and lower loss is required. However, to increase the breakdown voltage with a trench gate type MOSFET as shown in FIG. 15, it is necessary to reduce the impurity concentration in the drain region to expand the depletion layer and reduce the electric field. As a result, the resistance of the drain region is increased, the on-resistance when the semiconductor device is turned on and current flows is increased, and it is difficult to reduce the loss. In addition, the electric field tends to concentrate on the bottom of the recess 110, and it is difficult to increase the breakdown voltage. In a semiconductor device using SiC or Si, since the breakdown electric field is high, the impurity concentration of the drift layer 102 is usually increased to lower the on-resistance. In this case, the electric field of the gate insulating film 105 at the bottom of the recess 110 is reduced. It becomes high and it is difficult to increase the pressure resistance.

図１６に示すＳｉ−ＩＧＢＴは、降伏電圧が低く、産業用の高圧インバータや新幹線の電車などの電鉄用途のインバータ、電力事業用の高圧電力変換装置等に用いるには耐圧が不足であり、更なる高耐圧が必要である。図１６の構造で高耐圧化を図ろうとすると、ドリフト領域２０２の不純物濃度を下げて空乏層を拡げ電界を低減する必要がある。しかしこのようにするとドリフト領域２０２の抵抗が大きくなり、半導体装置をオンさせて電流を流す際のオン抵抗が高くなり低損失化が困難になってしまう。例えば、１０００Ｖ以上の降伏電圧にするとビルトイン電圧より高い電圧範囲でのオン抵抗は４００ｍΩｃｍ２以上になり、２０００Ｖ以上の降伏電圧にすると２５００ｍΩｃｍ２以上になる。 The Si-IGBT shown in FIG. 16 has a low breakdown voltage, and it has insufficient withstand voltage for use in industrial high-voltage inverters, inverters for electric railways such as Shinkansen trains, and high-voltage power converters for power businesses. A high breakdown voltage is required. In order to achieve a high breakdown voltage with the structure of FIG. 16, it is necessary to reduce the impurity concentration of the drift region 202 to expand the depletion layer and reduce the electric field. However, if this is done, the resistance of the drift region 202 increases, and the on-resistance when the semiconductor device is turned on and current flows is increased, making it difficult to reduce the loss. For example, when the breakdown voltage is 1000 V or more, the on-resistance in a voltage range higher than the built-in voltage is 400 mΩcm 2 or more, and when the breakdown voltage is 2000 V or more, 2500 mΩcm 2 or more.

本発明は、ドレイン領域の不純物濃度を低減させずにドレイン領域の電界を緩和し、オン抵抗を低くする一方、耐圧が高く、また信頼性も高い高耐圧の半導体装置を提供することを目的としている。   SUMMARY OF THE INVENTION An object of the present invention is to provide a high breakdown voltage semiconductor device having high breakdown voltage and high reliability while relaxing the electric field of the drain region without reducing the impurity concentration of the drain region and reducing the on-resistance. Yes.

本発明のワイドギャップ半導体装置は、高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同様の厚さと同様の不純物濃度を有する第２の導電型の第２のドリフト領域、前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の少なくとも一方に接するように形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、及び前記第１のドリフト領域及び前記ボディ領域に形成した制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   A wide gap semiconductor device according to the present invention includes a first conductivity type first drift region formed on a substrate of a high resistance wide gap semiconductor, and the first drift formed on the first drift region. A second conductivity type second drift region having the same thickness and impurity concentration as the region, a first conductivity type buried region formed so as to be in contact with the first and second drift regions, A first electrode formed in a buried region; a body region of a second conductivity type formed so as to be at a predetermined distance from the buried region and in contact with at least one of the first and second drift regions; A first conductivity type region formed in a part of the body region, a second electrode provided in the body region and the first conductivity type region, and a first drift region and the body region; With control electrode When the first and second drift regions have a thickness lower than a rated voltage between the first electrode and the second electrode, the first and second drift regions are substantially completely It is selected to be a depletion layer.

本発明の他の観点のワイドギャップ半導体装置は、高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同様の厚さと同様の不純物濃度を有する第２の導電型の第２のドリフト領域、前記基板、及び前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の少なくとも一方に接するように形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、及び前記基板、第１のドリフト領域及びボディ領域に絶縁膜を介して形成した制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   A wide gap semiconductor device according to another aspect of the present invention is a first conductivity type first drift region formed on a substrate of a high resistance wide gap semiconductor, the first drift region formed on the first drift region, A first drift formed in contact with the second drift region of the second conductivity type having the same thickness and the same impurity concentration as the first drift region, the substrate, and the first and second drift regions. A conductive type buried region, a first electrode formed in the buried region, and a second electrode formed at a predetermined distance from the buried region and in contact with at least one of the first and second drift regions. Conductivity type body region, a first conductivity type region formed in a part of the body region, a second electrode provided in the body region and the first conductivity type region, and the substrate, first Drift region and body area A control electrode formed through an insulating film, and when applying a voltage lower than a rated voltage between the first electrode and the second electrode with a thickness of the first and second drift regions, The first and second drift regions are selected so as to be substantially complete depletion layers.

上記の両発明のワイドギャップ半導体装置では、第１の電極が高電位、第２の電極が低電位になるように電圧を印加すると、第１の導電型の領域と第２の導電型のボディ領域で形成される接合が順バイアスされるので、低電位領域が第２の導電型のドリフト領域に拡がる。また、埋込領域を介して高電位領域が第１の導電型のドリフト領域に拡がる。その結果、第１及び第２のドリフト領域で形成される第１の接合は逆バイアスされ第１及び第２の両ドリフト領域に空乏層が拡がる。埋込領域６と第２の導電型ドリフト領域３で構成される第２の接合も同時に逆バイアスされ、空乏層が第２の導電型の領域内に拡がる。また第２の導電型のボディ領域と第１の導電型のドリフト領域で形成される第３の接合も同時に逆バイアスされ、空乏層が第１の導電型のドリフト領域内に拡がる。このように、両ドリフト領域には四方から空乏層が拡がり、第２及び第３の接合が降伏する前に第１の導電型のドリフト領域と第２の導電型のドリフト領域がほぼ完全に空乏化するように薄くする。少なくとも、印加電圧が半導体装置の定格電圧に達する前にはドリフト領域は完全に空乏化する。その結果、少なくとも定格電圧付近の電圧が印加された際には、ドリフト領域と埋込領域６で構成される接合から、ドリフト領域２とボディ領域４で構成される接合までの電位の分布がほぼ等電位分布となり電界が両ドリフト領域全域に渡ってほぼ均一になる。この電界がワイドギャップ半導体の絶縁破壊電界Ｅｃに達するまで印加電圧を高くすることができるので高耐圧にできる。   In the wide gap semiconductor devices of both the above inventions, when a voltage is applied such that the first electrode is at a high potential and the second electrode is at a low potential, the first conductivity type region and the second conductivity type body are applied. Since the junction formed in the region is forward biased, the low potential region extends to the drift region of the second conductivity type. In addition, the high potential region extends to the drift region of the first conductivity type through the buried region. As a result, the first junction formed by the first and second drift regions is reverse-biased, and a depletion layer extends in both the first and second drift regions. The second junction composed of the buried region 6 and the second conductivity type drift region 3 is also reverse-biased at the same time, and the depletion layer extends into the region of the second conductivity type. Further, the third junction formed by the body region of the second conductivity type and the drift region of the first conductivity type is also reverse-biased at the same time, and the depletion layer extends into the drift region of the first conductivity type. As described above, the depletion layers spread from both sides in both drift regions, and the first conductivity type drift region and the second conductivity type drift region are almost completely depleted before the second and third junctions breakdown. Thinn so that At least before the applied voltage reaches the rated voltage of the semiconductor device, the drift region is completely depleted. As a result, when a voltage at least near the rated voltage is applied, the potential distribution from the junction constituted by the drift region and the buried region 6 to the junction constituted by the drift region 2 and the body region 4 is almost equal. It becomes equipotential distribution, and the electric field is almost uniform over the entire drift region. Since the applied voltage can be increased until the electric field reaches the dielectric breakdown electric field Ec of the wide gap semiconductor, a high breakdown voltage can be achieved.

更に、前記の構成では、耐圧は最大絶縁破壊電界と両ドリフト領域の長さできまり、両ドリフト領域の厚さには依存しない。両ドリフト領域の厚さを薄くするほど、不純物濃度を高くしても完全な空乏化ができ、高耐圧が得られる。一般に、空乏層の厚さと不純物濃度Ｎの間には、厚さが１／Ｎの０．５乗にほぼ比例するという関係がある。そこで両ドリフト領域の厚さを薄くし空乏層の厚さをこの範囲にすると、これによる不純物濃度の増大効果は著しい。すなわち、オン抵抗の低減効果が著しい。従来の構成の場合、ドリフト領域の厚さを薄くし不純物濃度を高くするとオン抵抗は低減できるが耐圧は非線形的に低下するため、単位面積あたりの抵抗ＲｏｎＳは耐圧の２．５乗に比例する関係となり、耐圧が大きくなるとＲｏｎＳは著しく大きくなる。本発明の構造では耐圧がドリフト領域の長さに比例するが厚さには依存しない。従って厚さを低減して耐圧を損ねることなく不純物濃度を低減させることによりオン抵抗の低減効果のみを享受でき、ＲｏｎＳは耐圧の１乗に比例する関係となる。従って、本発明の構造ではドリフト層の厚さを限界まで薄くした場合、耐圧１０００Ｖ以上の半導体装置では従来構造に比べて原理的にオン抵抗を２桁以上低減できるという大きな効果が生じる。このドリフト層の厚さの限界は、濃度を上げても第１の接合のビルトイン・ポテンシャルが存在するので、これによる空乏層が形成されるためにドリフト層の厚さをこの空乏層厚さ以下にしてもオン抵抗の低減効果はなくなるということから生じるものである。また、従来構造に比べて同じ電圧を印加した際には、本発明の構造の方が電界の局所集中が少なく最大電界が低いので信頼性が向上できる。   Further, in the above configuration, the breakdown voltage is determined by the maximum breakdown field and the length of both drift regions, and does not depend on the thickness of both drift regions. As the thickness of both drift regions is reduced, complete depletion can be achieved even when the impurity concentration is increased, and a high breakdown voltage can be obtained. In general, there is a relationship between the thickness of the depletion layer and the impurity concentration N that the thickness is approximately proportional to 1 / N to the 0.5th power. Therefore, if the thickness of both drift regions is reduced and the thickness of the depletion layer is within this range, the effect of increasing the impurity concentration due to this is remarkable. That is, the on-resistance reduction effect is remarkable. In the case of the conventional configuration, if the thickness of the drift region is reduced and the impurity concentration is increased, the on-resistance can be reduced, but the breakdown voltage decreases nonlinearly, so the resistance RonS per unit area is proportional to the 2.5th power of the breakdown voltage. In relation, as the breakdown voltage increases, RonS increases significantly. In the structure of the present invention, the breakdown voltage is proportional to the length of the drift region, but does not depend on the thickness. Therefore, by reducing the thickness and reducing the impurity concentration without impairing the breakdown voltage, only the on-resistance reduction effect can be enjoyed, and RonS is proportional to the first power of the breakdown voltage. Therefore, in the structure of the present invention, when the thickness of the drift layer is reduced to the limit, a semiconductor device having a withstand voltage of 1000 V or more has a great effect that in principle, the on-resistance can be reduced by two digits or more compared to the conventional structure. The limit of the thickness of the drift layer is that the built-in potential of the first junction exists even if the concentration is increased. Therefore, a depletion layer is formed by this, so that the thickness of the drift layer is less than the depletion layer thickness. However, this is because the effect of reducing the on-resistance is lost. Further, when the same voltage is applied as compared with the conventional structure, the structure of the present invention has less local concentration of the electric field and the maximum electric field is lower, so that the reliability can be improved.

本発明の他の観点のワイドギャップ半導体装置は、高抵抗のワイドギャップ半導体の基板の上に形成した、複数組の、第１の導電型の第１のドリフト領域と第２の導電型の第２のドリフト領域との組、前記複数組の、前記第１及び第２のドリフト領域の組を貫通して前記基板に達する第１のトレンチの内壁面に形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記複数組の第１及び第２のドリフト領域の最上層のドリフト領域内に形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記第１のトレンチから所定距離だけ離れた位置に設けた、前記複数組の前記第１及び第２のドリフト領域、前記ボディ領域及び第１の導電型の領域を貫通して前記基板に達する第２のトレンチの内壁面に形成した絶縁膜、前記第２のトレンチの内壁面に前記絶縁膜を介して設けた制御電極、及び前記領域及びボディ領域に設けた第２の電極を備えている。   A wide gap semiconductor device according to another aspect of the present invention includes a plurality of sets of a first drift region of a first conductivity type and a second conductivity type of a plurality of sets formed on a substrate of a high resistance wide gap semiconductor. Embedded in the first conductivity type formed on the inner wall surface of the first trench reaching the substrate through the set of two drift regions and the plurality of sets of the first and second drift regions Region, a first electrode formed in the buried region, a body region of a second conductivity type formed in a drift region of the uppermost layer of the plurality of sets of first and second drift regions, one of the body regions A plurality of sets of the first and second drift regions, the body region, and the first conductive region provided at a position away from the first trench by a predetermined distance. A second trench extending through the mold region to the substrate Insulating film formed on the inner wall surface, and a second control electrode is provided through the insulating film on the inner wall surface of the trench, and a second electrode provided on the region and the body region.

本発明の他の観点のワイドギャップ半導体装置は、高抵抗のワイドギャップ半導体の基板上に形成した第２の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と実質的に同じ厚さと同じ不純物濃度を有する第１の導電型の第２のドリフト領域、前記基板、及び前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記基板及び前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記領域及びボディ領域に設けた第２の電極、及び前記ボディ領域に絶縁膜を介して設けた制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   A wide gap semiconductor device according to another aspect of the present invention includes a first conductivity type first drift region formed on a substrate of a high resistance wide gap semiconductor, the first drift region formed on the first drift region, A first conductivity type second drift region having substantially the same thickness and the same impurity concentration as the first drift region, the substrate, and the first drift region and the first drift region formed in contact with the first drift region; A buried region of the conductive type, a first electrode formed in the buried region, and a first distance formed from the buried region so as to be in contact with the substrate and the first and second drift regions. A second conductivity type body region, a first conductivity type region formed in a part of the body region, a second electrode provided in the region and the body region, and an insulating film provided in the body region A control electrode; When the voltage lower than the rated voltage is applied between the first electrode and the second electrode, the first drift region and the second drift region are substantially completely depleted. It is selected so that it becomes.

本発明の他の観点のワイドギャップ半導体装置は、高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と実質的に同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように前記第１のドリフト領域内に形成した第２の導電型のボディ領域、前記ボディ領域の、１部分に形成した第１の導電型の領域、前記領域に設けた第２の電極、及び前記第１のドリフト領域の第２のボディ領域及び前記領域上に絶縁膜を介して設けた制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   A wide gap semiconductor device according to another aspect of the present invention is a first conductivity type first drift region formed on a substrate of a high resistance wide gap semiconductor, the first drift region formed on the first drift region, A second conductivity type second drift region having substantially the same thickness and the same impurity concentration as the first drift region, and a first conductivity type formed so as to be in contact with the first and second drift regions; A buried region, a first electrode formed in the buried region, and a predetermined distance away from the buried region and formed in the first drift region so as to contact the first and second drift regions A second conductivity type body region, a first conductivity type region formed in a part of the body region, a second electrode provided in the region, and a second body region of the first drift region; And an insulating film on the region Provided with a control electrode provided, and when the first and second drift regions have a thickness lower than a rated voltage applied between the first electrode and the second electrode, the first and second drift regions are provided. The drift region is selected so as to be a substantially complete depletion layer.

本発明の他の観点のワイドギャップ半導体装置は、高抵抗の第１の種類の材料を用いたワイドギャップ半導体の基板上に形成した、低抵抗の第２の種類の材料を用いた第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と実質的に同じ厚さと同じ不純物濃度を有する第２の種類の材料を用いた第２の導電型の第２のドリフト領域、前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記領域に設けた第２の電極、及び前記ボディ領域を貫通して、前記第１のドリフト領域に達するトレンチの内壁面に絶縁膜を介して設けた制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   According to another aspect of the present invention, there is provided a wide gap semiconductor device including a first low-resistance material using a low-resistance second type material formed on a wide-gap semiconductor substrate using a high-resistance first type material. A conductive first drift region, a second drift material formed on the first drift region, using a second type material having substantially the same thickness and the same impurity concentration as the first drift region. Conductivity type second drift region, first conductivity type buried region formed so as to be in contact with the first and second drift regions, first electrode formed in the buried region, and the buried region A body region of a second conductivity type formed so as to be in contact with the first and second drift regions at a predetermined distance from the region, a region of the first conductivity type formed in a part of the body region, A second electrode provided in the region, and the body region A control electrode provided on the inner wall surface of the trench reaching the first drift region through an insulating film, and the thicknesses of the first and second drift regions are set to be different from those of the first electrode and the second drift region. When a voltage lower than the rated voltage is applied between the electrodes, the first and second drift regions are selected so as to be substantially complete depletion layers.

本発明の半導体装置は、高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同様の厚さと同様の不純物濃度を有する第２の導電型の第２のドリフト領域、前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の少なくとも一方に接するように形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、及び前記第１のドリフト領域及び前記ボディ領域に形成した制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   The semiconductor device of the present invention includes a first drift region of a first conductivity type formed on a substrate of a high resistance wide gap semiconductor, the first drift region formed on the first drift region, A second conductivity type second drift region having a similar thickness and similar impurity concentration, a first conductivity type buried region formed so as to be in contact with the first and second drift regions, and the buried A first electrode formed in a region; a body region of a second conductivity type formed so as to be at a predetermined distance from the buried region and in contact with at least one of the first and second drift regions; A first conductivity type region formed in a part of the substrate, a second electrode provided in the body region and the first conductivity type region, and a control electrode formed in the first drift region and the body region Comprising the first and When the voltage lower than the rated voltage is applied between the first electrode and the second electrode, the first and second drift regions become substantially complete depletion layers. It was selected as follows.

本発明の他の観点の半導体装置は、高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同様の厚さと同様の不純物濃度を有する第２の導電型の第２のドリフト領域、前記基板、及び前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の少なくとも一方に接するように形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、及び前記基板、第１のドリフト領域及びボディ領域に絶縁膜を介して形成した制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   A semiconductor device according to another aspect of the present invention includes a first drift region of a first conductivity type formed on a substrate of a high resistance wide gap semiconductor, the first drift region formed on the first drift region. A first conductivity type formed in contact with the second drift region of the second conductivity type having the same thickness and the same impurity concentration as the first drift region, the substrate, and the first and second drift regions. Embedded region, a first electrode formed in the buried region, and a second conductive material formed so as to be at a predetermined distance from the buried region and in contact with at least one of the first and second drift regions. A body region of the mold, a region of a first conductivity type formed in a part of the body region, a second electrode provided in the body region and the region of the first conductivity type, the substrate, a first drift Insulating film in region and body region And when the first and second drift regions have a thickness lower than a rated voltage between the first electrode and the second electrode, the first and second drift regions are formed. The drift region is selected so as to be a substantially complete depletion layer.

上記の両発明の半導体装置では、第１の電極が高電位、第２の電極が低電位になるように電圧を印加すると、第１の導電型の領域と第２の導電型のボディ領域で形成される接合が順バイアスされるので、低電位領域が第２の導電型のドリフト領域に拡がる。また、埋込領域を介して高電位領域が第１の導電型のドリフト領域に拡がる。その結果、第１及び第２のドリフト領域で形成される第１の接合は逆バイアスされ第１及び第２の両ドリフト領域に空乏層が拡がる。埋込領域６と第２の導電型ドリフト領域３で構成される第２の接合も同時に逆バイアスされ、空乏層が第２の導電型の領域内に拡がる。また第２の導電型のボディ領域と第１の導電型のドリフト領域で形成される第３の接合も同時に逆バイアスされ、空乏層が第１の導電型のドリフト領域内に拡がる。このように、両ドリフト領域には四方から空乏層が拡がり、第２及び第３の接合が降伏する前に第１の導電型のドリフト領域と第２の導電型のドリフト領域がほぼ完全に空乏化するように薄くする。少なくとも、印加電圧が半導体装置の定格電圧に達する前にはドリフト領域は完全に空乏化する。その結果、少なくとも定格電圧付近の電圧が印加された際には、ドリフト領域と埋込領域６で構成される接合から、ドリフト領域２とボディ領域４で構成される接合までの電位の分布がほぼ等電位分布となり電界が両ドリフト領域全域に渡ってほぼ均一になる。この電界がワイドギャップ半導体の絶縁破壊電界Ｅｃに達するまで印加電圧を高くすることができるので高耐圧にできる。   In the semiconductor devices of both the above inventions, when a voltage is applied so that the first electrode is at a high potential and the second electrode is at a low potential, the first conductivity type region and the second conductivity type body region are applied. Since the formed junction is forward biased, the low potential region extends to the drift region of the second conductivity type. In addition, the high potential region extends to the drift region of the first conductivity type through the buried region. As a result, the first junction formed by the first and second drift regions is reverse-biased, and a depletion layer extends in both the first and second drift regions. The second junction composed of the buried region 6 and the second conductivity type drift region 3 is also reverse-biased at the same time, and the depletion layer extends into the region of the second conductivity type. Further, the third junction formed by the body region of the second conductivity type and the drift region of the first conductivity type is also reverse-biased at the same time, and the depletion layer extends into the drift region of the first conductivity type. As described above, the depletion layers spread from both sides in both drift regions, and the first conductivity type drift region and the second conductivity type drift region are almost completely depleted before the second and third junctions breakdown. Thinn so that At least before the applied voltage reaches the rated voltage of the semiconductor device, the drift region is completely depleted. As a result, when a voltage at least near the rated voltage is applied, the potential distribution from the junction constituted by the drift region and the buried region 6 to the junction constituted by the drift region 2 and the body region 4 is almost equal. It becomes equipotential distribution, and the electric field is almost uniform over the entire drift region. Since the applied voltage can be increased until the electric field reaches the dielectric breakdown electric field Ec of the wide gap semiconductor, a high breakdown voltage can be achieved.

更に、前記の構成では、耐圧は最大絶縁破壊電界と両ドリフト領域の長さできまり、両ドリフト領域の厚さには依存しない。両ドリフト領域の厚さを薄くするほど、不純物濃度を高くしても完全な空乏化ができ、高耐圧が得られる。一般に、空乏層の厚さと不純物濃度Ｎの間には、厚さが１／Ｎの０．５乗にほぼ比例するという関係がある。そこで両ドリフト領域の厚さを薄くし空乏層の厚さをこの範囲にすると、これによる不純物濃度の増大効果は著しい。すなわち、オン抵抗の低減効果が著しい。従来の構成の場合、ドリフト領域の厚さを薄くし不純物濃度を高くするとオン抵抗は低減できるが耐圧は非線形的に低下するため、単位面積あたりの抵抗ＲｏｎＳは耐圧の２．５乗に比例する関係となり、耐圧が大きくなるとＲｏｎＳは著しく大きくなる。本発明の構造では耐圧がドリフト領域の長さに比例するが厚さには依存しない。従って厚さを低減して耐圧を損ねることなく不純物濃度を低減させることによりオン抵抗の低減効果のみを享受でき、ＲｏｎＳは耐圧の１乗に比例する関係となる。従って、本発明の構造ではドリフト層の厚さを限界まで薄くした場合、耐圧１０００Ｖ以上の半導体装置では従来構造に比べて原理的にオン抵抗を２桁以上低減できるという大きな効果が生じる。このドリフト層の厚さの限界は、濃度を上げても第１の接合のビルトイン・ポテンシャルが存在するので、これによる空乏層が形成されるためにドリフト層の厚さをこの空乏層厚さ以下にしてもオン抵抗の低減効果はなくなるということから生じるものである。また、従来構造に比べて同じ電圧を印加した際には、本発明の構造の方が電界の局所集中が少なく最大電界が低いので信頼性が向上できる。   Further, in the above configuration, the breakdown voltage is determined by the maximum breakdown field and the length of both drift regions, and does not depend on the thickness of both drift regions. As the thickness of both drift regions is reduced, complete depletion can be achieved even when the impurity concentration is increased, and a high breakdown voltage can be obtained. In general, there is a relationship between the thickness of the depletion layer and the impurity concentration N that the thickness is approximately proportional to 1 / N to the 0.5th power. Therefore, if the thickness of both drift regions is reduced and the thickness of the depletion layer is within this range, the effect of increasing the impurity concentration due to this is remarkable. That is, the on-resistance reduction effect is remarkable. In the case of the conventional configuration, if the thickness of the drift region is reduced and the impurity concentration is increased, the on-resistance can be reduced, but the breakdown voltage decreases nonlinearly, so the resistance RonS per unit area is proportional to the 2.5th power of the breakdown voltage. In relation, as the breakdown voltage increases, RonS increases significantly. In the structure of the present invention, the breakdown voltage is proportional to the length of the drift region, but does not depend on the thickness. Therefore, by reducing the thickness and reducing the impurity concentration without impairing the breakdown voltage, only the on-resistance reduction effect can be enjoyed, and RonS is proportional to the first power of the breakdown voltage. Therefore, in the structure of the present invention, when the thickness of the drift layer is reduced to the limit, a semiconductor device having a withstand voltage of 1000 V or more has a great effect that in principle, the on-resistance can be reduced by two digits or more compared to the conventional structure. The limit of the thickness of the drift layer is that the built-in potential of the first junction exists even if the concentration is increased. Therefore, a depletion layer is formed by this, so that the thickness of the drift layer is less than the depletion layer thickness. However, this is because the effect of reducing the on-resistance is lost. Further, when the same voltage is applied as compared with the conventional structure, the structure of the present invention has less local concentration of the electric field and the maximum electric field is lower, so that the reliability can be improved.

本発明の他の観点の半導体装置は、高抵抗のワイドギャップ半導体の基板の上に形成した、複数組の、第１の導電型の第１のドリフト領域と第２の導電型の第２のドリフト領域との組、前記複数組の、前記第１及び第２のドリフト領域の組を貫通して前記基板に達する第１のトレンチの内壁面に形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記複数組の第１及び第２のドリフト領域の最上層のドリフト領域内に形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記第１のトレンチから所定距離だけ離れた位置に設けた、前記複数組の前記第１及び第２のドリフト領域、前記ボディ領域及び第１の導電型の領域を貫通して前記基板に達する第２のトレンチの内壁面に形成した絶縁膜、前記第２のトレンチの内壁面に前記絶縁膜を介して設けた制御電極、及び前記領域及びボディ領域に設けた第２の電極を備えている。   A semiconductor device according to another aspect of the present invention includes a plurality of sets of a first conductivity type first drift region and a second conductivity type second formed on a substrate of a high resistance wide gap semiconductor. A buried region of a first conductivity type formed on an inner wall surface of a first trench reaching the substrate through the set of the drift region, the plurality of sets of the first and second drift regions, A first electrode formed in the buried region; a body region of a second conductivity type formed in a drift region of an uppermost layer of the plurality of sets of first and second drift regions; and a part of the body region The formed first conductivity type region, the plurality of sets of the first and second drift regions, the body region, and the first conductivity type provided at a predetermined distance from the first trench. Formed on the inner wall of the second trench that penetrates the region and reaches the substrate Insulating film, and a second control electrode is provided through the insulating film on the inner wall surface of the trench, and a second electrode provided on the region and the body region.

本発明の他の観点の半導体装置は、高抵抗のワイドギャップ半導体の基板上に形成した第２の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と実質的に同じ厚さと同じ不純物濃度を有する第１の導電型の第２のドリフト領域、前記基板、及び前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記基板及び前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記領域及びボディ領域に設けた第２の電極、及び前記ボディ領域に絶縁膜を介して設けた制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   A semiconductor device according to another aspect of the present invention is a first drift region of a second conductivity type formed on a substrate of a high resistance wide gap semiconductor, the first drift region formed on the first drift region. A first conductivity type formed in contact with the second drift region of the first conductivity type having substantially the same thickness and the same impurity concentration as the first drift region, the substrate, and the first and second drift regions. A buried region of the mold, a first electrode formed in the buried region, and a second electrode formed to contact the substrate and the first and second drift regions at a predetermined distance from the buried region. Conductive body region, first conductive type region formed in part of the body region, second electrode provided in the region and body region, and control electrode provided in the body region via an insulating film Comprising the first and second doors. When the voltage lower than the rated voltage is applied between the first electrode and the second electrode, the first drift region and the second drift region become substantially complete depletion layers. It is selected.

本発明の他の観点の半導体装置は、高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と実質的に同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように前記第１のドリフト領域内に形成した第２の導電型のボディ領域、前記ボディ領域の、１部分に形成した第１の導電型の領域、前記領域に設けた第２の電極、及び前記第１のドリフト領域の第２のボディ領域及び前記領域上に絶縁膜を介して設けた制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   A semiconductor device according to another aspect of the present invention includes a first drift region of a first conductivity type formed on a substrate of a high resistance wide gap semiconductor, the first drift region formed on the first drift region. A second conductivity type second drift region having substantially the same thickness and the same impurity concentration as the first drift region, and an embedding of the first conductivity type formed in contact with the first and second drift regions Region, a first electrode formed in the buried region, a second electrode formed in the first drift region so as to be in contact with the first and second drift regions at a predetermined distance from the buried region. A conductive type body region, a first conductive type region formed in a portion of the body region, a second electrode provided in the region, a second body region of the first drift region, and the Control power provided on the region via an insulating film When the voltage lower than the rated voltage is applied between the first electrode and the second electrode, the first drift region and the second drift region are substantially It is characterized in that it is selected to be a completely depleted layer.

本発明の他の観点の半導体装置は、高抵抗の第１の種類の材料を用いたワイドギャップ半導体の基板上に形成した、低抵抗の第２の種類の材料を用いた第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と実質的に同じ厚さと同じ不純物濃度を有する第２の種類の材料を用いた第２の導電型の第２のドリフト領域、前記第１及び第２のドリフト領域に接するように形成した第１の導電型の埋込領域、前記埋込領域に形成した第１の電極、前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記領域に設けた第２の電極、及び前記ボディ領域を貫通して、前記第１のドリフト領域に達するトレンチの内壁面に絶縁膜を介して設けた制御電極を備え、前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧より低い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に完全な空乏層となるように選定したことを特徴とする。   A semiconductor device according to another aspect of the present invention is a first conductivity type using a low resistance second type material formed on a wide gap semiconductor substrate using a high resistance first type material. The first drift region, the second conductivity using the second type material formed on the first drift region and having substantially the same thickness and the same impurity concentration as the first drift region. A second drift region of the type, a first conductivity type buried region formed so as to be in contact with the first and second drift regions, a first electrode formed in the buried region, and the buried region A second conductivity type body region formed so as to be in contact with the first and second drift regions by a predetermined distance; a first conductivity type region formed in a part of the body region; and Penetrating the second electrode provided and the body region, A control electrode provided via an insulating film on the inner wall surface of the trench reaching the first drift region, and the thicknesses of the first and second drift regions are rated between the first electrode and the second electrode. The first and second drift regions are selected to be substantially complete depletion layers when a voltage lower than the voltage is applied.

本発明の他の観点の半導体装置は、絶縁基板上に形成した第１の導電型の第１のドリフト領域、前記第１のドリフト領域の上の一部分に形成した第２の導電型の第２のドリフト領域、前記第１のドリフト領域の上の一部分に形成した、第２の導電型の第２のドリフト領域の不純物濃度以上の不純物濃度を有する第２の導電型の第３のドリフト領域、前記第３のドリフト領域に形成した高不純物濃度を有する第１の導電型の第１の領域、前記第１のドリフト領域及び第２のドリフト領域に接して形成した、前記第１のドリフト領域及び第２のドリフト領域よりも高い不純物濃度を有する第１の導電型の第２の領域、前記第１の導電型の第２の領域に接して形成した、高不純物濃度を有する第２の導電型の第３の領域、前記第１の導電型の第１の領域に形成した第１の電極、前記第２の導電型の第３の領域に形成した第２の電極、及び前記第１のドリフト領域、第３のドリフト領域、第１の領域に絶縁膜を介して対向する制御電極、を備えたバイポーラ半導体装置であって、前記第１のドリフト領域と第２のドリフト領域の厚さが実質的に等しく、それぞれの厚さがそれぞれの長さより小さく、前記第１の電極と第２の電極間に定格電圧に近い電圧を印加したとき、前記第１及び第２のドリフト領域が実質的に空乏層となるように前記第１及び第２のドリフト領域の厚さを選択したことを特徴とする。   A semiconductor device according to another aspect of the present invention includes a first conductivity type first drift region formed on an insulating substrate, and a second conductivity type second formed on a part of the first drift region. A drift region of the second conductivity type formed in a part above the first drift region and having an impurity concentration equal to or higher than the impurity concentration of the second drift region of the second conductivity type, A first region of a first conductivity type having a high impurity concentration formed in the third drift region; the first drift region formed in contact with the first drift region and the second drift region; A second region of a first conductivity type having an impurity concentration higher than that of the second drift region; a second conductivity type having a high impurity concentration formed in contact with the second region of the first conductivity type; A third region of the first region of the first conductivity type A first electrode formed in a region, a second electrode formed in a third region of the second conductivity type, and an insulating film in the first drift region, the third drift region, and the first region A control electrode opposed thereto, wherein the first drift region and the second drift region have substantially the same thickness, each thickness being smaller than the respective length, When a voltage close to a rated voltage is applied between the first electrode and the second electrode, the first drift region and the second drift region are substantially depleted so that the first drift region and the second drift region become substantially depleted layers. The thickness is selected.

前記の半導体装置では、第２の電極が高電位、第１の電極が低電位になるように高電圧を印加すると、第１の導電型の第１の領域と第２の導電型の第２の領域で構成される接合は順方向電圧が印加されるので第２の導電型のドリフト領域は低電位になる。また第２の導電型の第３の領域と第１の導電型の第２の領域を介して第１の導電型の第１のドリフト領域は高電位になる。その結果、第１及び第２のドリフト領域で構成される第１の接合には逆方向の電圧が印加され第１及び第２の両ドリフト領域に空乏層が拡がる。第１の導電型の第２の領域と第２の導電型の第２のドリフト領域で構成される第２の接合も同時に逆バイアスされ空乏層が第２の導電型の第２のドリフト領域内に拡がる。第２の導電型の第３ドリフト領域と第１の導電型の第１のドリフト領域で構成される第３の接合も同時に逆方向の電圧が印加され空乏層が第１の導電型の第１のドリフト領域内に拡がる。   In the semiconductor device, when a high voltage is applied so that the second electrode is at a high potential and the first electrode is at a low potential, the first region of the first conductivity type and the second region of the second conductivity type are applied. Since a forward voltage is applied to the junction constituted by the regions, the drift region of the second conductivity type has a low potential. Further, the first conductivity type first drift region becomes a high potential through the second conductivity type third region and the first conductivity type second region. As a result, a reverse voltage is applied to the first junction composed of the first and second drift regions, and the depletion layer spreads in both the first and second drift regions. The second junction constituted by the second region of the first conductivity type and the second drift region of the second conductivity type is also simultaneously reverse-biased so that the depletion layer is in the second drift region of the second conductivity type. To spread. A voltage in the reverse direction is simultaneously applied to the third junction including the third drift region of the second conductivity type and the first drift region of the first conductivity type, so that the depletion layer is the first conductivity type first. Extends into the drift region.

このようにして、第１及び第２のドリフト領域には上下方向と左右方向から空乏層が拡がるので、第２及び第３の接合が降伏する前に第１の導電型の第１のドリフト領域と第２の導電型の第２のドリフト領域は印加電圧が半導体装置の定格電圧に達する前に容易に且つほぼ完全に空乏化される。その結果、少なくとも定格電圧付近の電圧が印加された際には、第２のドリフト領域と第２の領域で構成される接合から、第１のドリフト領域と第３のドリフト領域で構成される接合に至る部分の電位分布はほぼ等電位分布となり、電界は両ドリフト領域全域に渡ってほぼ均一になる。この電界が半導体材料の絶縁破壊電界に達するまで印加高電圧を高くすることができるので、高耐圧にすることができる。   In this way, since the depletion layer extends in the vertical direction and the horizontal direction in the first and second drift regions, the first drift region of the first conductivity type before the second and third junctions breakdown. The second drift region of the second conductivity type is easily and almost completely depleted before the applied voltage reaches the rated voltage of the semiconductor device. As a result, when at least a voltage in the vicinity of the rated voltage is applied, the junction composed of the first drift region and the third drift region is changed from the junction composed of the second drift region and the second region. The electric potential distribution in the portion extending to is substantially equipotential distribution, and the electric field is substantially uniform over the entire drift region. Since the applied high voltage can be increased until this electric field reaches the breakdown electric field of the semiconductor material, a high breakdown voltage can be achieved.

従来の構造では、一定の不純物濃度のドリフト領域を設けても空乏層内の電界は接合に近づくにつれて一定の勾配で増大し、接合部で最大となる。印加電圧が増大し、この接合部の電界が絶縁破壊電圧Ｅｃに達すると降伏する。これに対して本発明の構造では、耐圧は、電界が絶縁破壊電圧に達するときの空乏層内の電界の積分値となる。降伏時にドリフト領域内で電界が一定の絶縁破壊電圧になるので原理的に従来構造に比べて高耐圧にできる。   In the conventional structure, even if a drift region having a constant impurity concentration is provided, the electric field in the depletion layer increases with a constant gradient as it approaches the junction, and is maximized at the junction. The applied voltage increases, and breakdown occurs when the electric field at the junction reaches the dielectric breakdown voltage Ec. On the other hand, in the structure of the present invention, the breakdown voltage is an integral value of the electric field in the depletion layer when the electric field reaches the breakdown voltage. Since the electric field becomes a constant breakdown voltage in the drift region at the time of breakdown, in principle, a higher breakdown voltage can be achieved compared to the conventional structure.

更に、本発明の構造では耐圧は、最大絶縁破壊電界と第１及び第２のドリフト領域の長さで決まり、両ドリフト領域の厚さには依存しない。不純物濃度を高くしても、両ドリフト領域の厚さを薄くすれば、両ドリフト領域は容易且つ完全に空乏化し上記と同じように高耐圧化が実現できる。一般に、空乏層の厚さＷと不純物濃度Ｎの間には、厚さＷが１／Ｎの０．５乗にほぼ比例するという関係がある。両ドリフト領域の厚さを薄くするとその２乗に比例して不純物濃度を増やすことができるので、オン抵抗の低減効果が著しい。   Furthermore, in the structure of the present invention, the breakdown voltage is determined by the maximum breakdown electric field and the lengths of the first and second drift regions, and does not depend on the thicknesses of both drift regions. Even if the impurity concentration is increased, if the thicknesses of both drift regions are reduced, both drift regions are easily and completely depleted, and a high breakdown voltage can be achieved as described above. In general, there is a relationship between the thickness W of the depletion layer and the impurity concentration N that the thickness W is substantially proportional to 1 / N to the 0.5th power. If the thicknesses of both drift regions are reduced, the impurity concentration can be increased in proportion to the square thereof, so that the on-resistance reduction effect is significant.

従来の構造の場合、ドリフト領域の厚さを薄くし不純物濃度を高くするとオン抵抗は低減するが、耐圧も非線形的に低下する。このため、単位面積あたりの抵抗は耐圧の２．５乗に比例する関係となり、耐圧が大きくなると前記抵抗は著しく大きくなる。本発明の構造では、耐圧はドリフト領域の長さに比例し厚さには依存しないので、厚さを低減して不純物濃度を低減させることにより高い耐圧を保ちつつオン抵抗の低減が計れる。すなわち抵抗は耐圧の１乗に比例する関係となる。従って、本発明の構造ではドリフト層の厚さを限界まで薄くした場合、耐圧１０００Ｖ以上の半導体装置で従来の構造に比べて原理的にオン抵抗を２桁以上低減できるという大きな効果が生じる。このドリフト層の厚さの限界が、ドリフト層の不純物濃度を上げても第１の接合のビルトイン・ポテンシャルが存在するので、これによる空乏層が形成される。ドリフト層の厚さをこの空乏層の厚さ以下にするとオン抵抗の低減効果はなくなる、ということからこのドリフト層の厚さの限界が生じる。同じ電圧を印加した際には、従来の構造に比べて本発明の構造の方が電界の局所集中が少なく最大電界が低いので信頼性が向上できる。   In the case of the conventional structure, when the thickness of the drift region is reduced and the impurity concentration is increased, the on-resistance is reduced, but the breakdown voltage is also reduced nonlinearly. For this reason, the resistance per unit area is proportional to the 2.5th power of the breakdown voltage, and the resistance increases remarkably as the breakdown voltage increases. In the structure of the present invention, the breakdown voltage is proportional to the length of the drift region and does not depend on the thickness. Therefore, the ON resistance can be reduced while maintaining a high breakdown voltage by reducing the thickness and reducing the impurity concentration. That is, the resistance is proportional to the first power of the breakdown voltage. Therefore, in the structure of the present invention, when the thickness of the drift layer is reduced to the limit, a large effect is obtained that, in principle, the on-resistance can be reduced by two orders of magnitude or more in a semiconductor device having a withstand voltage of 1000 V or higher compared to the conventional structure. Even if the drift layer thickness limit increases the drift layer impurity concentration, the built-in potential of the first junction exists, so that a depletion layer is formed. If the thickness of the drift layer is set to be equal to or less than the thickness of the depletion layer, the effect of reducing the on-resistance is lost, so that the thickness of the drift layer is limited. When the same voltage is applied, the structure of the present invention has less local concentration of the electric field and the maximum electric field is lower than the conventional structure, so that the reliability can be improved.

本発明の他の観点の半導体装置は、絶縁基板の上に形成した、複数組の、第１の導電型の第１のドリフト領域と第２の導電型の第２のドリフト領域との組、前記複数組の、前記第１及び第２のドリフト領域を貫通して前記基板に達する第１のトレンチの内壁面に形成した第１の導電型の第１の埋込領域、前記第１の埋込領域に接して形成した第２の導電型の第２の埋込領域、前記第２の埋込領域に形成した第１の電極、前記複数組の第１及び第２のドリフト領域の最上層のドリフト領域に接して形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記第１のトレンチから所定距離だけ離れた位置に設けた、前記複数組の前記第１及び第２のドリフト領域、前記ボディ領域及び第１の導電型の領域を貫通して前記基板に達する第２のトレンチの内壁面に形成した絶縁膜、前記第２のトレンチの内壁面に前記絶縁膜を介して設けた制御電極、及び前記領域及びボディ領域に設けた第２の電極を備える。   A semiconductor device according to another aspect of the present invention includes a plurality of sets of a first conductivity type first drift region and a second conductivity type second drift region formed on an insulating substrate, A first buried region of the first conductivity type formed on an inner wall surface of a first trench penetrating the first and second drift regions and reaching the substrate; A second buried region of the second conductivity type formed in contact with the buried region, a first electrode formed in the second buried region, and an uppermost layer of the plurality of sets of first and second drift regions A second conductivity type body region formed in contact with the drift region, a first conductivity type region formed in a part of the body region, and a position away from the first trench by a predetermined distance; The plurality of sets of the first and second drift regions, the body region, and the first conductivity type region are penetrated. The insulating film formed on the inner wall surface of the second trench reaching the substrate, the control electrode provided on the inner wall surface of the second trench via the insulating film, and the second electrode provided in the region and the body region Electrode.

本発明の他の観点の半導体装置は、基板の上に絶縁膜を介して形成した、複数組の、第１の導電型の第１のドリフト領域と第２の導電型の第２のドリフト領域との組、前記複数組の、前記第１及び第２のドリフト領域を貫通して前記基板に達する第１のトレンチの内壁面に形成した第１の導電型の第１の埋込領域、前記第１の埋込領域に接して形成した第２の導電型の第２の埋込領域、前記第２の埋込領域に形成した第１の電極、前記複数組の第１及び第２のドリフト領域の最上層のドリフト領域に接して形成した第２の導電型のボディ領域、前記ボディ領域の一部に形成した第１の導電型の領域、前記第１のトレンチから所定距離だけ離れた位置に設けた、前記複数組の前記第１及び第２のドリフト領域、前記ボディ領域及び第１の導電型の領域を貫通して前記基板に達する第２のトレンチの内壁面に形成した絶縁膜、前記第２のトレンチの内壁面に前記絶縁膜を介して設けた制御電極、及び前記領域及びボディ領域に設けた第２の電極を備える。   A semiconductor device according to another aspect of the present invention includes a plurality of first conductivity type first drift regions and second conductivity type second drift regions formed on a substrate via an insulating film. The first conductivity type first buried region formed on the inner wall surface of the first trench that reaches the substrate through the first and second drift regions, A second buried region of the second conductivity type formed in contact with the first buried region; a first electrode formed in the second buried region; and the plurality of sets of first and second drifts. A body region of the second conductivity type formed in contact with the uppermost drift region of the region, a region of the first conductivity type formed in a part of the body region, and a position separated from the first trench by a predetermined distance The plurality of sets of the first and second drift regions, the body region, and the first conductivity type An insulating film formed on the inner wall surface of the second trench that reaches the substrate through the region, a control electrode provided on the inner wall surface of the second trench via the insulating film, and provided in the region and the body region A second electrode.

本発明の他の観点の半導体装置は、高抵抗のワイドギャップ半導体の基板の上に形成した、複数組の、第１の導電型の第１のドリフト領域と第２の導電型の第２のドリフト領域との組、前記複数組の、前記第１及び第２のドリフト領域を貫通して前記基板に達する第１のトレンチの内壁面に形成した第１の導電型の第１の埋込領域、前記第１の埋込領域に接して形成した第２の導電型の第２の埋込領域、前記第２の埋込領域に形成した第１の電極、前記複数組の第１及び第２のドリフト領域の最上層のドリフト領域に形成した第２の導電型コンタクト部、前記第１のトレンチから所定距離だけ離れた位置に形成され、前記複数組の前記第１及び第２のドリフト領域、前記コンタクト部を貫通して前記基板に達する第２のトレンチの内壁面に形成した第２の導電型のベース領域、前記第２のトレンチ内の前記ベース領域に設けた第２の電極、及び前記コンタクト部に設けた第３の電極を備える。   A semiconductor device according to another aspect of the present invention includes a plurality of sets of a first conductivity type first drift region and a second conductivity type second formed on a substrate of a high resistance wide gap semiconductor. A first buried region of the first conductivity type formed on an inner wall surface of a first trench that penetrates the first and second drift regions and reaches the substrate; , A second conductivity type second buried region formed in contact with the first buried region, a first electrode formed in the second buried region, the plurality of sets of first and second sets A second conductivity type contact portion formed in the drift region of the uppermost layer of the drift region, formed at a position away from the first trench by a predetermined distance, the plurality of sets of the first and second drift regions, Formed on the inner wall surface of the second trench that reaches the substrate through the contact portion Provided with second conductivity type base region, a second electrode provided on the base region in the second trench, and a third electrode provided on the contact portion.

本発明の他の観点の半導体装置は、高抵抗のワイドギャップ半導体の基板の上に形成した複数組の、第１の導電型の第１のドリフト領域と第２の導電型の第２のドリフト領域との組、前記複数組の、前記第１及び第２のドリフト領域を貫通して前記基板に達する第１のトレンチの内壁面に形成した第１の導電型の第１の埋込領域、前記第１の埋込領域に接して形成した第２の導電型の第２の埋込領域、前記第２の埋込領域に形成した第１の電極、前記第１のトレンチから所定距離だけ離れた位置に形成され、前記複数組の前記第１及び第２のドリフト領域を貫通して前記基板に達する第２のトレンチの内壁面に形成した第２の導電型のベース領域、前記第２のトレンチ内の前記ベース領域に設けた第２の電極、及び前記第１の埋込領域及び第２の埋込領域に絶縁膜を介して対向する第３の電極を備える。   A semiconductor device according to another aspect of the present invention includes a plurality of sets of a first conductivity type first drift region and a second conductivity type second drift formed on a substrate of a high resistance wide gap semiconductor. A first buried region of a first conductivity type formed on an inner wall surface of a first trench that penetrates the first and second drift regions and reaches the substrate, A second conductivity type second buried region formed in contact with the first buried region, a first electrode formed in the second buried region, and a predetermined distance from the first trench. A base region of a second conductivity type formed on an inner wall surface of a second trench reaching the substrate through the plurality of sets of the first and second drift regions; A second electrode provided in the base region in the trench, and the first buried region and the second Comprising a third electrode opposed to the buried region via an insulating film.

本発明の他の観点の半導体装置は、基板上に形成した少なくとも１組の、第１の導電型の半導体領域と第２の導電型の半導体領域の第１の組、前記第１の組の半導体領域の一方の端部に接する少なくとも１組の第１の導電型の半導体領域と第２の導電型の半導体領域の第２の組、前記第１の組の半導体領域の他方の端部に接する少なくとも１組の、第１の導電型の半導体領域と第２の導電型の半導体領域の第３の組、及び前記第３の組の半導体領域に電界を与える制御電極を備え、第２の組の半導体領域の電位が第３の組の半導体領域の電位より高くなるように両者間に電圧を印加したとき、第１の組の半導体領域の全域が空乏化され、第２の組の半導体領域の電位が第３の組の半導体領域の電位より高くなるように両者間に電圧を印加するとともに、前記制御電極にしきい値以上の電圧を印加したとき、第３の組の半導体領域から電子が流出して第１の組の半導体領域を経て第２の組の半導体領域に流入し、かつ第２の組の半導体領域から正孔が流出し、第１の組の半導体領域を経て第３の組の半導体領域に流入して第１の組の半導体領域に電子と正孔が共に存在する状態となるように、前記第１の組の半導体領域の形状と厚さを選定したことを特徴とする。   A semiconductor device according to another aspect of the present invention includes at least one set of a first conductivity type semiconductor region and a second conductivity type semiconductor region formed on a substrate, the first set of the first set. At least one pair of first conductivity type semiconductor regions in contact with one end of the semiconductor region, a second set of semiconductor regions of the second conductivity type, and the other end of the first set of semiconductor regions. A third set of first conductive type semiconductor regions and a second conductive type semiconductor region in contact with each other, and a control electrode for applying an electric field to the third set of semiconductor regions; When a voltage is applied between the pair of semiconductor regions so that the potential of the pair of semiconductor regions is higher than the potential of the third set of semiconductor regions, the entire region of the first set of semiconductor regions is depleted, and the second set of semiconductor regions Apply a voltage between the two so that the potential of the region is higher than the potential of the third set of semiconductor regions In both cases, when a voltage equal to or higher than a threshold value is applied to the control electrode, electrons flow out of the third set of semiconductor regions, flow into the second set of semiconductor regions through the first set of semiconductor regions, and Holes flow out from the second set of semiconductor regions, flow into the third set of semiconductor regions via the first set of semiconductor regions, and both electrons and holes exist in the first set of semiconductor regions. The shape and thickness of the first set of semiconductor regions are selected so as to be in a state.

本発明の各実施例において詳細に説明したように、半導体装置を絶縁性のワイドギャップ半導体基板上に形成し、ボディ領域とドレイン領域の間に、定格電圧付近の高電圧を印加した際に完全に空乏化する薄いｐ型とｎ型のドリフトを積層して設ける。これにより、不純物濃度を高くしても高電圧印加時にｐ型及びｎ型の両ドリフト領域で構成する接合から拡がる空乏層でドリフト領域を完全に空乏化できる。その結果、ドリフト領域が等電位分布すなわち一定電界になり高耐圧が実現できる。不純物濃度を高くしているので低オン抵抗化も同時に図れ、高電圧を印加した際の電界の局所集中が少なく最大電界が低いので信頼性が向上する。   As described in detail in each embodiment of the present invention, a semiconductor device is formed on an insulating wide gap semiconductor substrate, and is completely applied when a high voltage near the rated voltage is applied between the body region and the drain region. The thin p-type and n-type drifts that are depleted are stacked. Thereby, even if the impurity concentration is increased, the drift region can be completely depleted by the depletion layer extending from the junction constituted by both the p-type and n-type drift regions when a high voltage is applied. As a result, the drift region has an equipotential distribution, that is, a constant electric field, and a high breakdown voltage can be realized. Since the impurity concentration is increased, the on-resistance can be reduced at the same time, and the local concentration of the electric field when a high voltage is applied is small and the maximum electric field is low, so that the reliability is improved.

また、ボディ領域とバッファー領域の間、もしくはｎ型ベース領域とｐ型ベース領域の間に、定格電圧付近の高電圧を印加した際に両者間が完全に空乏化するような厚さの薄いｐ型とｎ型の両極性のドリフト領域を積層して設ける。これにより、両ドリフト領域の不純物濃度が高い場合でも、高電圧印加時に、主にｐ型、ｎ型両ドリフト領域で構成する接合から拡がる空乏層で両ドリフト領域を完全に空乏化できる。その結果前記両者間が等電位分布すなわち一定電界になり高耐圧化が実現できる。不純物濃度が高いのでオン抵抗も低くなる。更に高電圧を印加した際に電界の局所集中が減少するとともに最大電界が低いので信頼性が向上する。   In addition, when the high voltage near the rated voltage is applied between the body region and the buffer region, or between the n-type base region and the p-type base region, the p-type is thin so that the two are completely depleted. A drift region having both bipolar and n-type drift regions is provided. Thereby, even when the impurity concentration of both drift regions is high, both drift regions can be completely depleted by a depletion layer mainly extending from a junction constituted by both the p-type and n-type drift regions when a high voltage is applied. As a result, an equipotential distribution, that is, a constant electric field is formed between the two, and a high breakdown voltage can be realized. Since the impurity concentration is high, the on-resistance is also low. Further, when a high voltage is applied, the local concentration of the electric field is reduced and the maximum electric field is low, so that the reliability is improved.

以下、本発明の好適な実施例について図１から図１４を参照して詳細に説明する。各実施例の半導体装置は、多数のセグメントが図の左右方向に隣接して形成されている。各図では、中央部の１個のセグメントについて、各要素に符号を付し詳細に説明している。   Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS. In the semiconductor device of each embodiment, a large number of segments are formed adjacent to each other in the horizontal direction of the drawing. In each figure, a single segment in the center is described in detail with reference to each element.

《第１実施例》
図１は、本発明の第１実施例の半導体装置の断面図である。第１実施例はワイドギャップ半導体装置であり、耐圧６１００ＶのＳｉＣ電界効果トランジスタである。図１はそのセグメントの断面構造を示す。図中の絶縁基板１はバナジュームなどの深いエネルギーレベルを形成する不純物を含んだ極めて高抵抗のワイドギャップＳｉＣ（炭化珪素）基板であり、抵抗率は１０９Ωｃｍ以上であり、厚さ（図の上下方向の寸法）は約３５０μｍである。ＳｉＣ基板を用いた半導体装置を一般的にワイドギャップ半導体装置という。第１の導電型のｎ型のドリフト領域２とその上に形成された第２の導電型のｐ型の第２のドリフト領域３はほぼ同じ厚さ（つまり実質的に同様な厚さ）と、同じ不純物濃度とを有しており、厚さが約０．８μｍ、不純物濃度が約８×１０１６ａｔｍ／ｃｍ３である。本実施例の構成では耐圧はｐ型ドリフト領域とｎ型ドリフト領域の厚さの差や不純物濃度の差に依存し、これらの差が少ない方が、耐圧は高くなる。本発明の目的を効果的に達成するためには、ｐ型ドリフト領域とｎ型ドリフト領域の厚さの差は±２０％以下であり、不純物濃度の差は±２５０％以下であるのが望ましい。ｐ型のドリフト領域３の左側には、約５×１０１７ａｔｍ／ｃｍ３の不純物濃度を有するｐ型ボディ領域４が形成され、その中に不純物濃度１×１０１９ａｔｍ／ｃｍ３、厚さ約０．２μｍのｎ型ソース領域５が形成されている。右側には埋込領域である１×１０１９ａｔｍ／ｃｍ３の高不純物濃度のｎ型ドレイン領域６が基板１、ｎ型ドリフト領域２及びｐ型ドリフト領域３に達するように形成されている。ドリフト領域２の長さ、すなわちボディ領域４とドレイン領域６との間の距離は約５２μｍである。ｐ型ボディ領域４には絶縁基板１に達する溝すなわちトレンチ１０Ａが形成されている。トレンチ１０Ａにゲート絶縁膜９としての酸化膜を介してゲート電極１０が設けられている。また、ボディ領域４とソース領域５にはソース電極７が設けられている。ドレイン領域６にはドレイン電極８が設けられている。ｐ型ドリフト領域３の表面には表面保護のためにＳｉ酸化膜またはＳｉ窒化膜１１が形成されている。 << First Example >>
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The first embodiment is a wide gap semiconductor device, which is a SiC field effect transistor having a withstand voltage of 6100V. FIG. 1 shows the cross-sectional structure of the segment. The insulating substrate 1 in the figure is a very high resistance wide gap SiC (silicon carbide) substrate containing impurities forming a deep energy level such as vanadium, the resistivity is 10 9 Ωcm or more, and the thickness (in the figure) The vertical dimension is about 350 μm. A semiconductor device using an SiC substrate is generally called a wide gap semiconductor device. The n-type drift region 2 of the first conductivity type and the p-type second drift region 3 of the second conductivity type formed thereon have substantially the same thickness (that is, substantially the same thickness). And having the same impurity concentration, a thickness of about 0.8 μm, and an impurity concentration of about 8 × 10 16 atm / cm 3 . In the configuration of this embodiment, the breakdown voltage depends on the difference in thickness between the p-type drift region and the n-type drift region and the difference in impurity concentration, and the smaller the difference, the higher the breakdown voltage. In order to effectively achieve the object of the present invention, the difference in thickness between the p-type drift region and the n-type drift region is preferably ± 20% or less, and the difference in impurity concentration is preferably ± 250% or less. . A p-type body region 4 having an impurity concentration of about 5 × 10 17 atm / cm 3 is formed on the left side of the p-type drift region 3 and has an impurity concentration of 1 × 10 19 atm / cm 3 and a thickness thereof. An n-type source region 5 of about 0.2 μm is formed. On the right side, an n-type drain region 6 having a high impurity concentration of 1 × 10 19 atm / cm 3 , which is a buried region, is formed so as to reach the substrate 1, the n-type drift region 2 and the p-type drift region 3. The length of the drift region 2, that is, the distance between the body region 4 and the drain region 6 is about 52 μm. In the p-type body region 4, a groove reaching the insulating substrate 1, that is, a trench 10 </ b> A is formed. A gate electrode 10 is provided in the trench 10 </ b> A through an oxide film as the gate insulating film 9. A source electrode 7 is provided in the body region 4 and the source region 5. A drain electrode 8 is provided in the drain region 6. A Si oxide film or Si nitride film 11 is formed on the surface of the p-type drift region 3 for surface protection.

本実施例のＳｉＣ電界効果トランジスタの製作方法の一例を以下に示す。最初にＳｉＣ絶縁基板１を用意し、この一方の表面上に５×１０１５から３×１０１７ａｔｍ／ｃｍ３の間の所定の低不純物濃度で、０．１から２．０μｍの間の所定の厚さのｎ型ドリフト層２を形成し、次にほぼ同じ厚さと同じ不純物濃度を持つｐ型ドリフト層３を気相成長法等により形成する。更に６×１０１７ａｔｍ／ｃｍ３程度のｐ型ボディ領域４、及び１×１０１９ａｔｍ／ｃｍ３程度のｎ型ドレイン領域６を窒素等のイオン打ち込み等により形成する。イオン打ち込みを用いる場合は打ち込みエネルギーを高エネルギーから低エネルギーへと順次変えて複数回打ち込み、深さ方向にほぼ均一な不純物濃度分布にするのが好ましい。続いて１×１０１９ａｔｍ／ｃｍ３程度の不純物濃度のｎ型ソース領域５を窒素のイオン打ち込み等により形成する。次に、トレンチ１０Ａを形成しその内壁にゲート酸化膜９を形成する。その後、Ｓｉ酸化膜やＳｉ窒化膜等の絶縁膜の表面保護膜１１を気相化学堆積法で形成する。最後に、ソース領域５、ボディ領域４及びドレイン領域６のコンタクト部分の絶縁膜を取り除き、Ａｌ等の金属膜を所定の領域に形成し、ソース電極７、ゲート電極１０及びドレイン電極８を形成する。 An example of a manufacturing method of the SiC field effect transistor of the present embodiment is shown below. First, an SiC insulating substrate 1 is prepared, and a predetermined low impurity concentration between 5 × 10 15 to 3 × 10 17 atm / cm 3 is provided on one surface of the SiC insulating substrate 1 with a predetermined value between 0.1 and 2.0 μm. Next, an n-type drift layer 2 having the same thickness and the same impurity concentration as the p-type drift layer 3 is formed by vapor phase epitaxy or the like. Further, a p-type body region 4 of about 6 × 10 17 atm / cm 3 and an n-type drain region 6 of about 1 × 10 19 atm / cm 3 are formed by ion implantation of nitrogen or the like. When ion implantation is used, it is preferable that the implantation energy is sequentially changed from high energy to low energy to perform implantation a plurality of times to obtain an almost uniform impurity concentration distribution in the depth direction. Subsequently, an n-type source region 5 having an impurity concentration of about 1 × 10 19 atm / cm 3 is formed by nitrogen ion implantation or the like. Next, a trench 10A is formed, and a gate oxide film 9 is formed on the inner wall thereof. Thereafter, a surface protective film 11 of an insulating film such as a Si oxide film or a Si nitride film is formed by a vapor phase chemical deposition method. Finally, the insulating film at the contact portions of the source region 5, the body region 4 and the drain region 6 is removed, a metal film such as Al is formed in a predetermined region, and the source electrode 7, the gate electrode 10 and the drain electrode 8 are formed. .

本実施例の動作を次に説明する。本実施例のＳｉＣ電界効果トランジスタでは、ドレイン電極８の電位がソース電極７の電位より高くなるように高電圧を印加すると、ドリフト領域２と３で構成される接合は逆バイアスされる。その結果両ドリフト領域２と３に空乏層が拡がりほぼ全ドリフト領域２及び３が完全に空乏化される。ドリフト領域３とドレイン領域６で形成される接合からドリフト領域２及びボディ領域４で形成される接合に向かって、ドリフト領域２と３内の電位分布はほぼ等電位分布となる。すなわち、電界がドリフト領域２と３の全域においてほぼ均一になり、この電界がＳｉＣの絶縁破壊電界約３ＭＶ／ｃｍに達するまで印加電圧を高くすることができる。その結果このＳｉＣ電界効果ドランジスタを高耐圧化できる。本実施例の場合、６２００Ｖの高耐圧を実現できた。   The operation of this embodiment will be described next. In the SiC field effect transistor of this embodiment, when a high voltage is applied so that the potential of the drain electrode 8 is higher than the potential of the source electrode 7, the junction formed by the drift regions 2 and 3 is reverse-biased. As a result, a depletion layer extends in both drift regions 2 and 3, and almost all drift regions 2 and 3 are completely depleted. From the junction formed by the drift region 3 and the drain region 6 toward the junction formed by the drift region 2 and the body region 4, the potential distribution in the drift regions 2 and 3 becomes substantially equipotential distribution. That is, the applied voltage can be increased until the electric field becomes substantially uniform throughout the drift regions 2 and 3 and the electric field reaches about 3 MV / cm of the dielectric breakdown field of SiC. As a result, the SiC field effect transistor can be increased in breakdown voltage. In this example, a high breakdown voltage of 6200 V was realized.

なお、高電圧を印加した際、ドリフト領域３とドレイン領域６で形成される接合の表面付近に電界集中が生じ耐圧が規制される場合がある。この電界集中の緩和策を施すことが高耐圧化に有効である。本実施例では、この電界集中を緩和するためにドレイン電極８を厚い表面保護膜１１を介してドリフト領域３の上まで張り出させる、いわゆるフィールドプレートと呼ばれる電界緩和技術を適用している。また、トレンチ１０Ａのコーナー部で電界集中が生じ耐圧が規制される場合があるので、この部分にも電界緩和策を施すのが有効である。本実施例ではトレンチ１０Ａを絶縁基板１内に進入するまで深くして、ゲート絶縁膜９と絶縁基板１を接続し、コーナー部の絶縁膜を実質的に大幅に厚くし電界緩和を図っている。トレンチ１０Ａが浅くて絶縁基板１に達しない構造の場合にはトレンチ１０Ａにｐ型の領域を設けて電界を緩和すること等が有効であり、これにより本実施例と同様の目的を達成できる。   When a high voltage is applied, electric field concentration may occur near the surface of the junction formed by the drift region 3 and the drain region 6, and the withstand voltage may be regulated. Applying this electric field concentration mitigation measure is effective in increasing the breakdown voltage. In this embodiment, in order to alleviate this electric field concentration, an electric field relaxation technique called a field plate is applied in which the drain electrode 8 extends over the drift region 3 through the thick surface protective film 11. In addition, since electric field concentration may occur at the corner portion of the trench 10A and the withstand voltage may be restricted, it is effective to apply an electric field relaxation measure to this portion. In this embodiment, the trench 10A is deepened until it enters the insulating substrate 1, the gate insulating film 9 and the insulating substrate 1 are connected, and the insulating film at the corner is substantially thickened to reduce the electric field. . In the case where the trench 10A is shallow and does not reach the insulating substrate 1, it is effective to reduce the electric field by providing a p-type region in the trench 10A, thereby achieving the same object as in this embodiment.

ゲート電極１０に、しきい値電圧（本実施例のものでは６Ｖ）よりも高い電圧例えば１０Ｖを印加すると、ゲート絶縁膜９を介する電界効果によりボディ領域４の表面にチャネルが形成される。その結果、ソース領域５からドレイン領域６へこのチャネルを介して電流が流れる状態、すなわちオン状態になる。この電流はドリフト領域２を通ってドレイン領域６に流れる。本実施例の場合、ドリフト領域２及び３の不純物濃度を高くしても両ドリフト領域２、３を完全に空乏化できるので、高耐圧が得られる。このように、両ドリフト領域２、３の不純物濃度が高いのでオン時には低抵抗になる。原理的には、耐圧を損ねることなく不純物濃度を約２桁高くすることができるので、オン抵抗を約２桁低くできる、という大きな効果が得られる。本実施例の場合、オン抵抗は１４０ｍΩｃｍ２と低い値が得られた。 When a voltage, for example, 10 V higher than the threshold voltage (6 V in the present embodiment) is applied to the gate electrode 10, a channel is formed on the surface of the body region 4 due to the electric field effect through the gate insulating film 9. As a result, a current flows from the source region 5 to the drain region 6 through this channel, that is, an on state. This current flows through the drift region 2 to the drain region 6. In the case of this embodiment, even if the impurity concentration of the drift regions 2 and 3 is increased, both drift regions 2 and 3 can be completely depleted, so that a high breakdown voltage can be obtained. Thus, since the impurity concentrations of both drift regions 2 and 3 are high, the resistance is low when the switch is on. In principle, since the impurity concentration can be increased by about two orders of magnitude without impairing the breakdown voltage, a great effect is obtained that the on-resistance can be reduced by about two orders of magnitude. In this example, the on-resistance was as low as 140 mΩcm 2 .

本実施例では、ｎ型ドリフト領域２とその上に形成されるｐ型ドリフト領域３の厚さを０．８μｍ、不純物濃度を約８×１０１６ａｔｍ／ｃｍ３としたが、図２及び図３の発明者の実験データに示すように、厚さが０．１μｍから１．２μｍの間で不純物濃度が約５×１０１５ａｔｍ／ｃｍ３から３×１０１７ａｔｍ／ｃｍ３の間の値であれば高耐圧かつ低損失のＳｉＣ電界効果トランジスタが得られる。なお、厚さが１．４μｍ以上、不純物濃度が３×１０１７ａｔｍ／ｃｍ３以上で耐圧が急減しているのは、両ドリフト領域２、３が完全に空乏化する前にドリフト領域２とボディ領域４で形成される接合部で降伏が生じたためである。 In this embodiment, the thickness of the n-type drift region 2 and the p-type drift region 3 formed thereon is 0.8 μm and the impurity concentration is about 8 × 10 16 atm / cm 3 . As shown in the experimental data of 3 inventors, the thickness is between 0.1 μm and 1.2 μm and the impurity concentration is between about 5 × 10 15 atm / cm 3 and 3 × 10 17 atm / cm 3. Then, a SiC field effect transistor having a high breakdown voltage and low loss can be obtained. Note that the breakdown voltage sharply decreases when the thickness is 1.4 μm or more, the impurity concentration is 3 × 10 17 atm / cm 3 or more, and the drift regions 2 and 3 are completely depleted before the drift regions 2 and 3 are completely depleted. This is because yielding has occurred at the joint formed in the body region 4.

本実施例の図１では、各セグメントの形状は紙面に垂直な方向のストライプ状であるが、例えば円形や四角形等であってもかまわない。本実施例ではボディ領域４をドリフト領域３と同じ厚さにしているが、ボディ領域４を厚くしても薄くしても同等の効果が得られる。ボディ領域４を薄くしてボディ領域４とドリフト領域２との間にドリフト領域３が介在しても同等の効果が得られる。更にドレイン領域６は絶縁基板１に接するように深く形成しているが、浅くしてドリフト領域２のみに接するようにしても良い。この場合、浅いので制作が容易になるがドリフト領域２のコーナー部に電界集中が起こり耐圧が低下する場合がある。   In FIG. 1 of the present embodiment, the shape of each segment is a stripe shape in a direction perpendicular to the paper surface, but it may be, for example, a circle or a rectangle. In this embodiment, the body region 4 has the same thickness as the drift region 3, but the same effect can be obtained regardless of whether the body region 4 is thicker or thinner. Even if the body region 4 is thinned and the drift region 3 is interposed between the body region 4 and the drift region 2, the same effect can be obtained. Further, the drain region 6 is formed deep so as to be in contact with the insulating substrate 1, but may be shallow so as to be in contact with only the drift region 2. In this case, production is easy because it is shallow, but electric field concentration may occur in the corner portion of the drift region 2 and the withstand voltage may decrease.

《第２実施例》
図４は、本発明の第２実施例のＳｉＣ電界効果トランジスタのセグメントの断面図を示す。第２実施例では、次の３点を除けば第１の実施例とほぼ同じである。 << Second Embodiment >>
FIG. 4 shows a cross-sectional view of the segment of the SiC field effect transistor of the second embodiment of the present invention. The second embodiment is substantially the same as the first embodiment except for the following three points.

（１）ドリフト領域２と絶縁基板１との間に、ドリフト領域３より薄いｐ型ドリフト領域１２を設けたこと。   (1) A p-type drift region 12 thinner than the drift region 3 is provided between the drift region 2 and the insulating substrate 1.

（２）ｎ型ドレイン領域６を絶縁基板１に達するトレンチ６Ａの内壁に沿って形成し、ドレイン領域６をドリフト領域２、３及び１２に接続させ、ドレイン電極８をドレイン領域６の表面に設けたこと。   (2) The n-type drain region 6 is formed along the inner wall of the trench 6A reaching the insulating substrate 1, the drain region 6 is connected to the drift regions 2, 3 and 12, and the drain electrode 8 is provided on the surface of the drain region 6. Was it.

（３）ゲート電極１０のためのトレンチ９Ａを深くしてドリフト領域１２に達するように形成し、このトレンチの内壁に沿って酸化膜９とゲート電極１０とを形成したこと。   (3) The trench 9A for the gate electrode 10 is deepened to reach the drift region 12, and the oxide film 9 and the gate electrode 10 are formed along the inner wall of the trench.

ｎ型ドリフト領域２の厚さは１．３μｍ、ｐ型ドリフト領域３及び１２の厚さは０．８μｍであり、各々の不純物濃度は約７×１０１６ａｔｍ／ｃｍ３でほぼ同じにしてある。トレンチ６Ａの深さは約３．５μｍ、幅は約８μｍである。トレンチ９Ａの深さは約２．５μｍ、幅は約６μｍである。 The thickness of the n-type drift region 2 is 1.3 μm, the thickness of the p-type drift regions 3 and 12 is 0.8 μm, and the impurity concentration of each is approximately 7 × 10 16 atm / cm 3 and is substantially the same. . The depth of the trench 6A is about 3.5 μm and the width is about 8 μm. The depth of the trench 9A is about 2.5 μm and the width is about 6 μm.

本実施例の電界効果トランジスタでは、ｎ型ドリフト領域２を二つのｐ型ドリフト領域３及び１２で挟み込んでいる。その結果、ドレイン電極８の電位がソース電極７の電位より高い状態になるように高電圧を印加した時、ドリフト領域２と３で形成される接合と、ドリフト領域１２と２で形成される接合とが同時に逆バイアスされ、両ドリフト領域３と１２から空乏層がドリフト領域２に拡がる。ドリフト領域２の厚さがドリフト領域３の２倍以上の厚さなので、所定の高電圧でドリフト層３と１２が空乏化した時にはドリフト層２もほぼ完全に空乏化される。その結果、ドレイン電極８からゲート電極１０に向かって、ドリフト領域２、３及び１２の電位分布はほぼ等電位分布となる。すなわち、電界がドリフト領域２、３及び１２の全域に渡ってほぼ均一になる。この電界がＳｉＣの絶縁破壊電界の約３ＭＶ／ｃｍに達するまで印加電圧を高くすることができるので、高耐圧化ができ、本実施例の場合では６１００Ｖの高耐圧が実現できた。   In the field effect transistor of this embodiment, the n-type drift region 2 is sandwiched between two p-type drift regions 3 and 12. As a result, when a high voltage is applied so that the potential of the drain electrode 8 is higher than the potential of the source electrode 7, the junction formed by the drift regions 2 and 3 and the junction formed by the drift regions 12 and 2. Are simultaneously reverse-biased, and a depletion layer extends from both drift regions 3 and 12 to the drift region 2. Since the thickness of the drift region 2 is more than twice that of the drift region 3, when the drift layers 3 and 12 are depleted at a predetermined high voltage, the drift layer 2 is also almost completely depleted. As a result, the potential distributions of the drift regions 2, 3, and 12 become substantially equipotential distribution from the drain electrode 8 toward the gate electrode 10. That is, the electric field is substantially uniform over the entire drift regions 2, 3 and 12. Since the applied voltage can be increased until this electric field reaches about 3 MV / cm of the SiC dielectric breakdown electric field, the withstand voltage can be increased, and in the present example, a high withstand voltage of 6100 V was realized.

ゲート電極１０にしきい値電圧以上の高い電圧を印加したオン状態では、領域５から、ボディ領域４内に形成されるチャネルとドリフト領域２を通ってドレイン領域６に電流が流れる。ドリフト領域２の厚さがドリフト領域３の厚さの約１．６倍になっているので、ドリフト領域２の上下の接合のビルドイン電圧による空乏層でドリフト領域の厚さが若干薄くなることを考えると、ドリフト領域２、３及び１２の抵抗は、ドリフト領域２及び３の厚さが同じ場合に比べて約１／１．６以下になる。このように抵抗が低減できるので、本実施例の場合、オン抵抗は９０ｍΩｃｍ２という低い値を実現できた。 In an ON state in which a voltage higher than the threshold voltage is applied to the gate electrode 10, a current flows from the region 5 to the drain region 6 through the channel formed in the body region 4 and the drift region 2. Since the thickness of the drift region 2 is about 1.6 times the thickness of the drift region 3, the drift region thickness is slightly reduced in the depletion layer due to the build-in voltage at the upper and lower junctions of the drift region 2. When considered, the resistance of the drift regions 2, 3, and 12 is about 1 / 1.6 or less compared to the case where the drift regions 2 and 3 have the same thickness. Since the resistance can be reduced in this way, in the case of this example, the on-resistance can be as low as 90 mΩcm 2 .

以上のごとく、本実施例では高耐圧を維持しつつオン抵抗を更に低減できるという効果がある。なお、本実施例ではゲート電極１０のトレンチ９Ａの幅と深さは、ドレイン領域６のトレンチ６Ａと異なっているが、上記深さをトレンチ６Ａの深さとほぼ同じにし絶縁基板に達するようにしてもよい。この場合はトレンチ９Ａのコーナー部での電界集中が更に緩和されて耐圧や信頼性が向上する。   As described above, this embodiment has an effect that the on-resistance can be further reduced while maintaining a high breakdown voltage. In this embodiment, the width and depth of the trench 9A of the gate electrode 10 are different from those of the trench 6A of the drain region 6, but the depth is made substantially the same as the depth of the trench 6A so as to reach the insulating substrate. Also good. In this case, the electric field concentration at the corner portion of the trench 9A is further relaxed and the breakdown voltage and reliability are improved.

《第３実施例》
図５は、本発明の第３実施例のＳｉＣ電界効果トランジスタのセグメント断面図である。厚さ３２０μｍのＳｉＣ絶縁基板１の上に、ｎ型ドリフト領域２２、２２Ａ、２２Ｂ、２２Ｃのそれぞれの間に、ｐ型ドリフト領域２３、２３Ａ、２３Ｂ、２３Ｃのそれぞれを挟んで形成したｎ型ドリフト領域とｐ型ドリフト領域の組を順次５組積層している。積層された各ドリフト領域２２、２３の両端にはトレンチ６Ａ、９Ａが絶縁基板１に達するように設けられている。トレンチ９Ａはゲート部用であり、ゲート酸化膜９を介してゲート電極１０が設けられている。トレンチ６Ａはドレイン部用であり、内壁にドレイン領域１６とドレイン電極８が設けられている。最上層のｐ型ドリフト領域３３のゲート部側にはｐ型ボディ領域３４とｎ型ソース領域５、及びこれらの領域に接続されたソース電極３７が設けられている。ｐ型ドリフト領域３３の表面には保護のためにＳｉ酸化膜やＳｉ窒化膜などの表面保護膜１１が設けられている。ｎ型及びｐ型ドリフト領域２２、２３の厚さは共に約０．８μｍ、不純物濃度は約８×１０１６ａｔｍ／ｃｍ３、長さは共に約７５μｍである。ｐ型ボディ領域３４の不純物濃度は約５×１０１７ａｔｍ／ｃｍ３、厚さは約０．８μｍであり、その中に形成されたｎ型ソース領域５は不純物濃度１×１０１９ａｔｍ／ｃｍ３、厚さ約０．２μｍである。ドレイン領域１６の不純物濃度は１×１０１９ａｔｍ／ｃｍ３であり、トレンチ６Ａの深さは約１０μｍである。 << Third embodiment >>
FIG. 5 is a segment cross-sectional view of the SiC field effect transistor according to the third embodiment of the present invention. An n-type drift formed on a 320 μm thick SiC insulating substrate 1 with n-type drift regions 23, 23A, 23B, and 23C sandwiched between n-type drift regions 22, 22A, 22B, and 22C, respectively. Five sets of regions and p-type drift regions are sequentially stacked. At both ends of the stacked drift regions 22 and 23, trenches 6A and 9A are provided so as to reach the insulating substrate 1. The trench 9 </ b> A is for a gate portion, and a gate electrode 10 is provided via a gate oxide film 9. The trench 6A is for the drain portion, and the drain region 16 and the drain electrode 8 are provided on the inner wall. A p-type body region 34, an n-type source region 5, and a source electrode 37 connected to these regions are provided on the gate portion side of the uppermost p-type drift region 33. A surface protective film 11 such as a Si oxide film or a Si nitride film is provided on the surface of the p-type drift region 33 for protection. Both the n-type and p-type drift regions 22 and 23 have a thickness of about 0.8 μm, an impurity concentration of about 8 × 10 16 atm / cm 3 , and a length of about 75 μm. The p-type body region 34 has an impurity concentration of about 5 × 10 17 atm / cm 3 and a thickness of about 0.8 μm. The n-type source region 5 formed therein has an impurity concentration of 1 × 10 19 atm / cm 3. 3 and thickness is about 0.2 μm. The impurity concentration of the drain region 16 is 1 × 10 19 atm / cm 3 , and the depth of the trench 6A is about 10 μm.

本実施例の電界効果トランジスタでは、ｎ型ドリフト領域２２は二つのｐ型ドリフト領域２３にはさまれている。同様にしてｐ型ドリフト領域２３は二つのｎ型ドリフト領域２２にはさまれている。この構成により、ドレイン電極８の電位がソース電極３７の電位より高い状態になるように高電圧を印加した時、各ドリフト領域２２、２３には両側から空乏層が拡がりほぼ完全に空乏化される。その結果、ドレイン電極８からゲート電極１０に向かってドリフト領域２２、２３の電位の分布はほぼ等電位分布となり、電界がドリフト領域２２、２３の全域に渡ってほぼ均一になる。この電界がＳｉＣの絶縁破壊電界の約３ＭＶ／ｃｍに達するまで印加電圧を高くすることができるので、高耐圧化ができる。本実施例では８３００Ｖの高耐圧が実現できた。   In the field effect transistor of this embodiment, the n-type drift region 22 is sandwiched between two p-type drift regions 23. Similarly, the p-type drift region 23 is sandwiched between the two n-type drift regions 22. With this configuration, when a high voltage is applied so that the potential of the drain electrode 8 is higher than the potential of the source electrode 37, a depletion layer extends from both sides of each drift region 22 and 23 and is almost completely depleted. . As a result, the potential distribution of the drift regions 22 and 23 from the drain electrode 8 toward the gate electrode 10 is substantially equipotential distribution, and the electric field is substantially uniform over the entire drift regions 22 and 23. Since the applied voltage can be increased until this electric field reaches about 3 MV / cm of the SiC dielectric breakdown electric field, a high breakdown voltage can be achieved. In this example, a high breakdown voltage of 8300 V was realized.

一方、ドレイン電極８がソース電極７より高電位になるように電圧を印加し、ゲートにしきい値以上の高い電圧を印加したオン状態では、ゲート電極１０に対向するボディ領域４及び各ドリフト領域２及び３の表面に電子が集まり反転層が形成される。また、各ドリフト領域２及び３のゲート電極１０に対向する部分の表面にも電子が集まり蓄積層が形成される。ボディ領域４の反転層はチャネルとして機能し、ソース領域５からチャネル及び上から２層目のｎ型ドリフト領域２２Ｄを通ってドレイン領域１６に電流が流れる。電流の一部はｎ型ドリフト層２２Ｄの蓄積層と上から３層目のｐ型ドリフト領域２３Ｃの反転層を介して４層目のｎ型ドリフト領域２２Ｃに分流しドレイン領域６に流れる。同様にして電流の一部がｎ型ドリフト領域２２Ｃの蓄積層とｐ型ドリフト領域２３Ｂの反転層を介して基板１に近いｎ型ドリフト領域２２Ａに分流しドレイン６に流れる。基板１に近いｎ型ドリフト層になるほどｎ型ドリフト領域２２の蓄積層とｐ型ドリフト領域２３の反転層の抵抗が加算される。従って若干抵抗が大きくなり分流電流が低減する傾向にあるが、本実施例の場合は特に問題になるレベルではなかった。ｎ型ドリフト領域２、２Ａ、２Ｂ、２Ｃ、２Ｄの合成抵抗は図１の構成のものの約１／５に低減し、電界効果トランジスタのオン抵抗が大幅に低減できる。本実施例の場合は、耐圧を８３００Ｖと高くしたにもかかわらず、ドリフト領域の単位面積あたりのオン抵抗は４７ｍΩｃｍ２と大幅に低減できた。 On the other hand, in the ON state in which a voltage is applied so that the drain electrode 8 has a higher potential than the source electrode 7 and a voltage higher than a threshold value is applied to the gate, the body region 4 and each drift region 2 facing the gate electrode 10 are applied. And the electrons gather on the surface of 3 and the inversion layer is formed. Also, electrons accumulate on the surface of each drift region 2 and 3 facing the gate electrode 10 to form a storage layer. The inversion layer of the body region 4 functions as a channel, and a current flows from the source region 5 to the drain region 16 through the channel and the n-type drift region 22D of the second layer from the top. Part of the current flows to the drain region 6 through the accumulation layer of the n-type drift layer 22D and the inversion layer of the third p-type drift region 23C from the top to the n-type drift region 22C of the fourth layer. Similarly, a part of the current is diverted to the n-type drift region 22A near the substrate 1 and flows to the drain 6 via the accumulation layer of the n-type drift region 22C and the inversion layer of the p-type drift region 23B. As the n-type drift layer is closer to the substrate 1, the resistances of the accumulation layer in the n-type drift region 22 and the inversion layer in the p-type drift region 23 are added. Accordingly, the resistance tends to be slightly increased and the shunt current tends to be reduced. However, in the case of the present embodiment, the level was not particularly problematic. The combined resistance of the n-type drift regions 2, 2A, 2B, 2C, and 2D is reduced to about 1/5 that of the configuration of FIG. 1, and the on-resistance of the field effect transistor can be greatly reduced. In the case of this example, the on-resistance per unit area of the drift region was significantly reduced to 47 mΩcm 2 even though the breakdown voltage was increased to 8300V.

以上のごとく、本実施例は耐圧を損ねることなく更に大幅にオン抵抗を低減できるという効果がある。ｎ型ドレイン領域２２、２２Ａ、・・・とｐ型ドレイン領域２３、２３Ａ、・・・の組の積層数を増やすほどこのオン抵抗は低減できる。但し、積層数を増やしすぎると上記の各反転層の抵抗が加算されるという現象により、下層のｎ型及びｐ型ドリフト領域の抵抗が増加する。従って上下のｎ型及びｐ型ドリフト領域の抵抗をそろえるための工夫が必要となる。例えば図６に示すように、下層のｎ型及びｐ型ドリフト領域ほど厚くする構成が極めて有効であった。最上層のドリフト領域３３に対する、最下層のドリフト領域２２の厚さの増大割合は、各ドリフト領域の図の左右方向の長さとｎ型ドリフト領域２２とｐ型ドリフト領域２３の組の数に依存するが、例えば組の数が１５の場合を例に取ると約１．３倍程度が好適である。図６ではｐ型とｎ型の両ドリフト領域２２、２３を下層のものほど順次厚くしたが、ｐ型ドリフト領域の厚さは一定にして、ｎ型ドリフト領域の厚さのみ順次増やしても同様の効果が得られる。この場合も最下層のｎ型ドリフト領域２２の厚さは最上層のｎ型ドリフト領域の厚さの約１．３倍程度が好適である。   As described above, this embodiment has an effect that the on-resistance can be further greatly reduced without impairing the breakdown voltage. As the number of stacked layers of the n-type drain regions 22, 22A,... and the p-type drain regions 23, 23A,. However, the resistance of the n-type and p-type drift regions in the lower layer increases due to the phenomenon that the resistance of each inversion layer is added when the number of stacked layers is excessively increased. Therefore, a device for aligning the resistances of the upper and lower n-type and p-type drift regions is required. For example, as shown in FIG. 6, a configuration in which the lower n-type and p-type drift regions are thicker is extremely effective. The increasing rate of the thickness of the lowermost drift region 22 with respect to the uppermost drift region 33 depends on the length of each drift region in the horizontal direction in the drawing and the number of pairs of the n-type drift region 22 and the p-type drift region 23. However, if the number of sets is 15, for example, about 1.3 times is preferable. In FIG. 6, both the p-type and n-type drift regions 22 and 23 are sequentially increased in thickness in the lower layer. However, the thickness of the p-type drift region is kept constant, and only the thickness of the n-type drift region is increased. The effect is obtained. Also in this case, the thickness of the lowermost n-type drift region 22 is preferably about 1.3 times the thickness of the uppermost n-type drift region.

《第４実施例》
図７は、本発明の第４実施例のＳｉＣ電界効果トランジスタのセグメントの断面図である。本実施例では、ゲート電極１０を含むゲート部がプレーナ構造であり、絶縁基板１に接するドリフト領域３がｐ型であり、その上のドリフト領域２がｎ型である。このように極性が変わった点と、ｎ型ドレイン領域６とｐ型ボディ領域４が絶縁基板１に達している点を除けば、その他の構造は第１実施例とほぼ同じである。ドリフト領域２及び３の厚さや長さ及び不純物濃度は第１実施例とほぼ同じである。ｎ型ソース領域５及びｐ型ボディ領域４の不純物濃度も第１実施例と同じである。 << 4th Example >>
FIG. 7 is a sectional view of a segment of a SiC field effect transistor according to the fourth embodiment of the present invention. In this embodiment, the gate portion including the gate electrode 10 has a planar structure, the drift region 3 in contact with the insulating substrate 1 is p-type, and the drift region 2 thereon is n-type. Except for the fact that the polarity has changed in this way and that the n-type drain region 6 and the p-type body region 4 reach the insulating substrate 1, the other structures are almost the same as those in the first embodiment. The thickness and length of the drift regions 2 and 3 and the impurity concentration are substantially the same as in the first embodiment. The impurity concentrations of the n-type source region 5 and the p-type body region 4 are also the same as in the first embodiment.

高電圧印加時における両ドリフト領域２及び３の機能は、基本的には第１実施例と同じであり、この構成によっても高耐圧を実現できる。オン動作も基本的には同じである。ソース電極７とドレイン電極８に電圧を印加した状態でゲート電極１０にしきい値以上の電圧を印加すると、ゲート電極１０の直下のボディ領域４０の表面電界の極性が反転してチャネルが形成される。その結果、ソース電極７からこのチャネルを介してｎ型ドリフト領域２に電流が流れドレイン８に流入する。   The functions of both drift regions 2 and 3 when a high voltage is applied are basically the same as those of the first embodiment, and a high breakdown voltage can also be realized with this configuration. The on operation is basically the same. When a voltage higher than the threshold value is applied to the gate electrode 10 with the voltage applied to the source electrode 7 and the drain electrode 8, the polarity of the surface electric field of the body region 40 immediately below the gate electrode 10 is reversed to form a channel. . As a result, current flows from the source electrode 7 to the n-type drift region 2 through this channel and flows into the drain 8.

本実施例では 耐圧６１００Ｖ、オン抵抗１３０ｍΩｃｍ２のＳｉＣ電界効果トランジスタが実現できた。本実施例では図４に示すようなトレンチ６Ａ、１０Ａを形成することなく、硼素などのイオン打ち込みだけでｐボディ領域４０を形成し、窒素などのイオン打ち込みでｎ型ソース領域５を形成することができる、従って製作が非常に容易であるという特徴がある。 In this example, a SiC field effect transistor having a breakdown voltage of 6100 V and an on-resistance of 130 mΩcm 2 was realized. In this embodiment, the p body region 40 is formed only by ion implantation of boron or the like and the n-type source region 5 is formed by ion implantation of nitrogen or the like without forming the trenches 6A and 10A as shown in FIG. Therefore, it is characterized by being very easy to manufacture.

《第５実施例》
図８は、本発明の第５実施例のＳｉＣ電界効果トランジスタのセグメントの断面図である。本実施例ではゲート電極１０を含むゲート部がプレーナ構造であり、ｎ型ドリフト領域２がゲート電極１０の直下の表面にまで延長されている点を除けば、その他の構造は第１実施例とほぼ同じである。ドリフト領域２及び３の厚さや長さ及び不純物濃度は第１実施例とほぼ同じである。ｎソース領域５及びｐボディ領域４の不純物濃度も第１実施例とほぼ同じである。 << 5th Example >>
FIG. 8 is a sectional view of a segment of an SiC field effect transistor according to the fifth embodiment of the present invention. In this embodiment, the gate portion including the gate electrode 10 has a planar structure, and the other structure is the same as that of the first embodiment except that the n-type drift region 2 extends to the surface immediately below the gate electrode 10. It is almost the same. The thickness and length of the drift regions 2 and 3 and the impurity concentration are substantially the same as in the first embodiment. The impurity concentrations of the n source region 5 and the p body region 4 are substantially the same as in the first embodiment.

高電圧印加時における両ドリフト領域２及び３の機能も基本的に第１実施例と同じであり、同様の高耐圧が実現できる。オン動作も基本的には同じである。ソース電極７とドレイン電極８に電圧を印加した状態でゲート電極１０にしきい値以上の電圧を印加すると、ゲート電極１０の直下のｐ型ボディ領域４の表面の電界が反転してチャネルが形成されソース電極７からドレイン電極８に電流が流れる。この電流はゲート電極１０の直下のｎ型ドリフト領域２を通り、ついでｐ型ドリフト領域３の下に存在するｎドリフト領域２を通ってドレイン領域６に至る。   The functions of both drift regions 2 and 3 when a high voltage is applied are basically the same as those in the first embodiment, and the same high breakdown voltage can be realized. The on operation is basically the same. When a voltage higher than the threshold value is applied to the gate electrode 10 with the voltage applied to the source electrode 7 and the drain electrode 8, the electric field on the surface of the p-type body region 4 immediately below the gate electrode 10 is inverted to form a channel. A current flows from the source electrode 7 to the drain electrode 8. This current passes through the n-type drift region 2 immediately below the gate electrode 10 and then reaches the drain region 6 through the n-drift region 2 existing under the p-type drift region 3.

本実施例のＳｉＣ電界効果トランジスタでは耐圧６２００Ｖ、オン抵抗１５０ｍΩｃｍ２であった。本実施例ではトレンチを形成することなく、硼素などのイオン打ち込みだけでｐ型ボディ領域４を形成でき、窒素などのイオン打ち込みでｎ型ソース領域５を形成できるので、製作が非常に容易であるという特徴がある。 The SiC field effect transistor of this example had a withstand voltage of 6200 V and an on-resistance of 150 mΩcm 2 . In this embodiment, the p-type body region 4 can be formed only by ion implantation of boron or the like without forming a trench, and the n-type source region 5 can be formed by ion implantation of nitrogen or the like. There is a feature.

《第６実施例》
図９は、本発明の第６実施例の窒化ガリウム（以下ＧａＮと記す）電界効果トランジスタのセグメントの断面図である。絶縁基板１はバナジュームなどの不純物を含んだＳｉＣ基板であり、抵抗率は１０９Ωｃｍ以上、厚さは約３５０μｍである。ＧａＮのｎ型ドリフト領域２とその上に形成されたｐ型ドリフト領域３はほぼ同じ厚さと不純物濃度を有しており、その厚さは約０．８μｍ、不純物濃度は約８×１０１６ａｔｍ／ｃｍ３である。ｐ型ドリフト領域３の左端部には約５×１０１７ａｔｍ／ｃｍ３の不純物濃度を有するｐ型ボディ領域４が形成されている。ボディ領域４の中に不純物濃度１×１０１９ａｔｍ／ｃｍ３、厚さ約０．２μｍのｎ型ソース領域５が形成されている。右端部には１×１０１９ａｔｍ／ｃｍ３の高不純物濃度のｎ型ドレイン領域６がｎ型ドリフト領域２に接するように形成されている。ドリフト領域３の長さ、すなわちボディ領域４とドレイン領域６との間の距離は約５０μｍである。ｐ型ボディ領域４を貫通してドリフト領域２に達するトレンチ９Ａが形成されており、トレンチ９Ａの内壁に酸化膜９を介してゲート電極１０が形成されている。ボディ領域４とソース領域５にはソース電極７が設けられ、ドレイン領域６にはドレイン電極８が設けられている。ｐ型ドリフト領域３の表面には表面保護のためにＳｉ窒化膜１１が形成されている。 << Sixth embodiment >>
FIG. 9 is a sectional view of a segment of a gallium nitride (hereinafter referred to as GaN) field effect transistor according to the sixth embodiment of the present invention. The insulating substrate 1 is a SiC substrate containing impurities such as vanadium, and has a resistivity of 10 9 Ωcm or more and a thickness of about 350 μm. The n-type drift region 2 of GaN and the p-type drift region 3 formed thereon have substantially the same thickness and impurity concentration, the thickness is about 0.8 μm, and the impurity concentration is about 8 × 10 16 atm. / Cm 3 . A p-type body region 4 having an impurity concentration of about 5 × 10 17 atm / cm 3 is formed at the left end of the p-type drift region 3. An n-type source region 5 having an impurity concentration of 1 × 10 19 atm / cm 3 and a thickness of about 0.2 μm is formed in the body region 4. At the right end, an n-type drain region 6 having a high impurity concentration of 1 × 10 19 atm / cm 3 is formed in contact with the n-type drift region 2. The length of the drift region 3, that is, the distance between the body region 4 and the drain region 6 is about 50 μm. A trench 9A that penetrates the p-type body region 4 and reaches the drift region 2 is formed, and a gate electrode 10 is formed on the inner wall of the trench 9A via the oxide film 9. A source electrode 7 is provided in the body region 4 and the source region 5, and a drain electrode 8 is provided in the drain region 6. A Si nitride film 11 is formed on the surface of the p-type drift region 3 for surface protection.

本実施例の動作はほぼ実施例１と同様であるが、ＧａＮはＳｉＣよりも優れた物理的電気的特性を有しているのでパワー半導体装置に好適である。本実施例では、耐圧６６００Ｖ、オン抵抗８０ｍΩｃｍ２のＧａＮ電界効果トランジスタが得られた。ＧａＮはＳｉＣに比べて表面保護膜１１のＳｉ窒化膜との相性がよく信頼性が更に向上する。また、ＧａＮは電子の飽和速度がＳｉＣよりも大きく高速動作に適している。本実施例では６ＧＨｚの遮断周波数のものが実現できた。 The operation of the present embodiment is almost the same as that of the first embodiment, but GaN has physical and electrical properties superior to SiC and is suitable for a power semiconductor device. In this example, a GaN field effect transistor having a breakdown voltage of 6600 V and an on-resistance of 80 mΩcm 2 was obtained. GaN has better compatibility with the Si nitride film of the surface protective film 11 than SiC, and the reliability is further improved. GaN has a higher electron saturation rate than SiC and is suitable for high-speed operation. In this embodiment, a cutoff frequency of 6 GHz was realized.

《第７実施例》
図１０は、本発明の第７実施例の半導体装置の断面図であり、耐圧６１００Ｖの絶縁ゲート型バイポーラトランジスタ（以下、ＩＧＢＴと記す）のセグメントの断面構造を示す。第７実施例の半導体装置はＳｉＣを用いて製作されている。ＳｉＣに代表されるワイドギャップ半導体材料は、シリコン（Ｓｉ）に比べて絶縁破壊電界強度が高いために、Ｓｉを用いたものと同じ不純物濃度でより高耐圧を実現できる。すなわち低損失を維持しつつ高耐圧にでき、２５０℃以上の高温でも動作でき熱伝導性も良いという利点がある。図１０において、絶縁基板１はバナジュームなどの深いエネルギーレベルを形成する不純物を含んだＳｉＣ基板である。その抵抗率は１０９Ωcm以上であり、厚さは約３５０μｍである。絶縁基板１の上に形成されたｎ型の第１のドリフト領域２、とその上に形成されたｐ型の第２のドリフト領域３とはほぼ同じ厚さと不純物濃度を有しており、厚さが約０．８μｍ、不純物濃度が約８×１０１６ａｔｍ／ｃｍ３である。 << Seventh embodiment >>
FIG. 10 is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention, showing a cross-sectional structure of a segment of an insulated gate bipolar transistor (hereinafter referred to as IGBT) having a withstand voltage of 6100V. The semiconductor device of the seventh embodiment is manufactured using SiC. A wide gap semiconductor material typified by SiC has a higher dielectric breakdown field strength than silicon (Si), so that a higher breakdown voltage can be realized with the same impurity concentration as that using Si. In other words, there is an advantage that a high breakdown voltage can be maintained while maintaining a low loss, the operation can be performed at a high temperature of 250 ° C. or higher, and the thermal conductivity is good. In FIG. 10, an insulating substrate 1 is a SiC substrate containing impurities that form a deep energy level such as vanadium. Its resistivity is 10 9 Ωcm or more and its thickness is about 350 μm. The n-type first drift region 2 formed on the insulating substrate 1 and the p-type second drift region 3 formed thereon have substantially the same thickness and impurity concentration. Is about 0.8 μm and the impurity concentration is about 8 × 10 16 atm / cm 3 .

ドリフト領域３の一方の端部に接して、約５×１０１７ａｔｍ／ｃｍ３の不純物濃度を有するｐ型ボディ領域４が形成され、その中に不純物濃度１×１０１９ａｔｍ／ｃｍ３、厚さ約０．２μｍのｎ型エミッタ領域５５が形成されている。ドリフト領域３の他端部には絶縁基板１に達する溝である第１のトレンチ６Ａが形成されている。トレンチ６Ａの内壁には、ドリフト領域２、３に接する、１×１０１８ａｔｍ／ｃｍ３の不純物濃度の第１の埋込領域としてのｎ型バッファー領域６６が形成されている。ｎ型バッファー領域６６の面には１×１０２０ａｔｍ／ｃｍ３の不純物濃度の第２の埋込領域としてのｐ型コレクタ領域７７が形成され、コレクタ領域７７にはコレクタ電極３９が絶縁基板１に達する深さまで形成されている。ドリフト領域３の長さ、すなわちボディ領域４とバッファー領域６６の間の距離は約５２μｍである。 A p-type body region 4 having an impurity concentration of about 5 × 10 17 atm / cm 3 is formed in contact with one end of the drift region 3, and an impurity concentration of 1 × 10 19 atm / cm 3 and a thickness thereof are formed therein. An n-type emitter region 55 having a thickness of about 0.2 μm is formed. A first trench 6 </ b> A that is a groove reaching the insulating substrate 1 is formed at the other end of the drift region 3. On the inner wall of the trench 6A, an n-type buffer region 66 is formed as a first buried region having an impurity concentration of 1 × 10 18 atm / cm 3 in contact with the drift regions 2 and 3 . A p-type collector region 77 as a second buried region having an impurity concentration of 1 × 10 20 atm / cm 3 is formed on the surface of the n-type buffer region 66, and a collector electrode 39 is provided on the insulating substrate 1 in the collector region 77. It is formed to the depth which reaches. The length of the drift region 3, that is, the distance between the body region 4 and the buffer region 66 is about 52 μm.

ｐ型ボディ領域４の近傍には絶縁基板１に達する第２のトレンチ９Ａが形成されている。トレンチ９Ａの内壁面には、ゲート絶縁膜３８を介してゲート電極４０が設けられている。ボディ領域４とエミッタ領域５５に接してエミッタ電極８８が設けられている。ドリフト領域３の表面には表面保護のためにＳｉ酸化膜またはＳｉ窒化膜による保護膜４５が設けられている。   A second trench 9A reaching the insulating substrate 1 is formed in the vicinity of the p-type body region 4. A gate electrode 40 is provided on the inner wall surface of the trench 9 </ b> A via a gate insulating film 38. An emitter electrode 88 is provided in contact with the body region 4 and the emitter region 55. A protective film 45 made of Si oxide film or Si nitride film is provided on the surface of the drift region 3 for surface protection.

本実施例のトランジスタの製作方法の一例は次のとおりである。最初にＳｉＣ絶縁基板１を用意し、この一方の面上に５×１０１５から３×１０１７ａｔｍ／ｃｍ３の間の所定の低不純物濃度で０．１から２．０μｍの間の所定の厚さを持つｎ型ドリフト領域２を気相成長法等により形成する。ついでほぼ同じ厚さと不純物濃度を持つｐ型ドリフト領域３を気相成長法等により形成する。ｐ型ドリフト領域３の上にはＳｉＯ２絶縁酸化膜を形成して表面保護膜４５とする。次に、エッチング等により第１のトレンチ６Ａを形成する。そしてトレンチ６Ａの内壁面に順次ｎ型バッファー領域６６とｐ型コレクタ領域７７をイオン打ち込み、または拡散により形成する。更に、ドリフト領域２と３に接するように、ｐ型ボディ領域４を形成し、ｐ型ボディ領域４の一部分にｎ型エミッタ領域５５をイオン打ち込み等により形成する。イオン打ち込み法を用いる場合は打ち込みエネルギーを高エネルギーから低エネルギーへと順次変えて複数回打ち込み、深さ方向にほぼ均一な不純物濃度分布にするのが好ましい。次に、第２のトレンチ９Ａを形成し、その内壁面を含む上面にゲート絶縁膜３８を形成してその上にゲート電極４０を形成する。エミッタ電極８８及びコレクタ電極３９を形成するためその部分のＳｉＯ２絶縁酸化膜を取り除き、Ａｌ等の金属膜を形成してエミッタ電極８８、コレクタ電極３９を形成して完成する。 An example of a method for manufacturing the transistor of this embodiment is as follows. First, a SiC insulating substrate 1 is prepared, and a predetermined low impurity concentration between 0.1 and 2.0 μm is provided on one surface at a predetermined low impurity concentration between 5 × 10 15 and 3 × 10 17 atm / cm 3 . The n-type drift region 2 having a thickness is formed by a vapor deposition method or the like. Next, a p-type drift region 3 having substantially the same thickness and impurity concentration is formed by a vapor phase growth method or the like. A SiO 2 insulating oxide film is formed on the p-type drift region 3 to form a surface protective film 45. Next, the first trench 6A is formed by etching or the like. Then, an n-type buffer region 66 and a p-type collector region 77 are sequentially formed on the inner wall surface of the trench 6A by ion implantation or diffusion. Further, the p-type body region 4 is formed so as to be in contact with the drift regions 2 and 3, and the n-type emitter region 55 is formed in a part of the p-type body region 4 by ion implantation or the like. In the case of using the ion implantation method, it is preferable that the implantation energy is sequentially changed from high energy to low energy, and implantation is performed a plurality of times to obtain a substantially uniform impurity concentration distribution in the depth direction. Next, the second trench 9A is formed, the gate insulating film 38 is formed on the upper surface including the inner wall surface, and the gate electrode 40 is formed thereon. In order to form the emitter electrode 88 and the collector electrode 39, the SiO 2 insulating oxide film in that portion is removed, and a metal film such as Al is formed to form the emitter electrode 88 and the collector electrode 39, thereby completing the process.

本実施例の動作を次に説明する。本実施例のＳｉＣ―ＩＧＢＴでは、コレクタ電極３９の電位がエミッタ電極８８の電位より高い状態になるようにして高電圧を印加すると、ドリフト領域２と３で構成される接合は逆バイアスされ両ドリフト領域２、３に空乏層が拡がりほぼ全領域が完全に空乏化される。このため、バッファー領域６６からボディ領域４に向かうドリフト領域２と３の電位分布はほぼ等電位分布となる。すなわち、電界がドリフト領域２と３の全域に渡ってほぼ均一になる。この電界がＳｉＣの絶縁破壊電界である約３ＭＶ／ｃｍに達するまで印加電圧を高くできるので高耐圧化が可能となる。本実施例の場合、６１００Ｖの高耐圧を実現できた。   The operation of this embodiment will be described next. In the SiC-IGBT of the present embodiment, when a high voltage is applied so that the potential of the collector electrode 39 is higher than the potential of the emitter electrode 88, the junction formed by the drift regions 2 and 3 is reverse-biased and both drifts occur. A depletion layer spreads in the regions 2 and 3, and almost the entire region is completely depleted. For this reason, the potential distributions of the drift regions 2 and 3 from the buffer region 66 toward the body region 4 are substantially equipotential distributions. That is, the electric field is substantially uniform over the entire drift regions 2 and 3. Since the applied voltage can be increased until this electric field reaches about 3 MV / cm, which is a dielectric breakdown field of SiC, a high breakdown voltage can be achieved. In this example, a high breakdown voltage of 6100 V was realized.

なお、高電圧を印加した際、ドリフト領域３とバッファー領域６６で構成する接合の表面付近に電界集中が生じ耐圧が制限される場合がある。この電界集中に対して電界緩和策を施すのが高耐圧化に有効である。本実施例では、この電界集中を緩和するためにコレクタ電極３９を、厚い表面保護膜４５を介してドリフト領域３の上方にまで張り出させている、いわゆるフィールドプレートと呼ばれる電界緩和技術を適用している。また、ゲート電極４０のトレンチ９Ａのコーナー部２１Ａで電界集中が生じ耐圧が規制される場合があるので、この部分にも電界緩和策を施すのが有効である。本実施例ではトレンチ９Ａを絶縁基板１に達する位置まで深くして、ゲート絶縁膜３８と絶縁基板１を接続し、コーナー部２１Ａのゲート絶縁膜３８を実効的に大幅に厚くして電界緩和を図っている。トレンチ９Ａが浅くて絶縁基板１に達しない構造の場合には、トレンチ９Ａの底にｐ型領域を設けて電界を緩和すること（図示省略）等が有効であり、これにより本実施例と同様の効果が得られる。トレンチ６Ａのコーナー部２１Ｂに関しても同様である。   When a high voltage is applied, electric field concentration may occur near the surface of the junction formed by the drift region 3 and the buffer region 66, and the withstand voltage may be limited. Applying electric field relaxation measures against this electric field concentration is effective for increasing the breakdown voltage. In this embodiment, in order to alleviate this electric field concentration, an electric field relaxation technique called a so-called field plate, in which the collector electrode 39 protrudes to the upper side of the drift region 3 through the thick surface protective film 45, is applied. ing. In addition, since electric field concentration may occur at the corner portion 21A of the trench 9A of the gate electrode 40 and the withstand voltage may be restricted, it is effective to apply an electric field relaxation measure to this portion. In this embodiment, the trench 9A is deepened to a position reaching the insulating substrate 1, the gate insulating film 38 and the insulating substrate 1 are connected, and the gate insulating film 38 in the corner portion 21A is effectively greatly thickened to reduce the electric field. I am trying. In the case where the trench 9A is shallow and does not reach the insulating substrate 1, it is effective to provide a p-type region at the bottom of the trench 9A to reduce the electric field (not shown) and the like. The effect is obtained. The same applies to the corner portion 21B of the trench 6A.

次に、ゲート電極４０にしきい値電圧（本実施例では４Ｖ）よりも高い電圧の例えば１０Ｖを印加すると、ゲート絶縁膜３８を介して与えられる電界効果によりボディ領域４の表面にチャネルが形成される。その結果、エミッタ領域５５からこのチャネルを経て電子が流れる状態すなわちオン状態になる。この電子がドリフト領域２を通ってバッファー領域６６に達すると、コレクタ領域７７から正孔がドリフト領域２に流れ、ボディ領域４を経てエミッタ電極８８に達する。このようにしてドリフト領域２には電子と正孔が共に存在することになり、伝導度変調が起ってドリフト領域２の抵抗が激減する。本実施例の場合、抵抗を小さくするために不純物濃度を高くすることによってもドリフト領域２と３を完全に空乏化できるので、高耐圧化できる。また、ドリフト領域２で伝導度変調を起こすとともにドリフト領域２の不純物濃度を従来のものより高くすることもできることから、オン抵抗を大幅に低くすることができる。原理的には耐圧を損ねることなく不純物濃度を従来のものより約２桁高くできるので、オン抵抗を約２桁低くできる。本実施例の具体例の場合、ＳｉＣのビルトイン電圧（２．７Ｖ）より高い電圧範囲でのオン抵抗は５６ｍΩｃｍ２となり従来のものでは得られない低い値を実現できた。 Next, when a voltage higher than a threshold voltage (4 V in this embodiment), for example, 10 V is applied to the gate electrode 40, a channel is formed on the surface of the body region 4 by the electric field effect applied through the gate insulating film 38. The As a result, an electron flows from the emitter region 55 through this channel, that is, an on state. When the electrons pass through the drift region 2 and reach the buffer region 66, holes flow from the collector region 77 to the drift region 2 and reach the emitter electrode 88 through the body region 4. Thus, both electrons and holes are present in the drift region 2, conductivity modulation occurs, and the resistance of the drift region 2 is drastically reduced. In the case of this embodiment, the drift regions 2 and 3 can be completely depleted also by increasing the impurity concentration in order to reduce the resistance, so that the breakdown voltage can be increased. Further, conductivity modulation can be caused in the drift region 2 and the impurity concentration of the drift region 2 can be made higher than that of the conventional one, so that the on-resistance can be greatly reduced. In principle, the on-resistance can be reduced by about two orders of magnitude because the impurity concentration can be made about two orders of magnitude higher than the conventional one without damaging the breakdown voltage. In the specific example of this example, the on-resistance in the voltage range higher than the built-in voltage (2.7 V) of SiC was 56 mΩcm 2, and a low value that could not be obtained with the conventional one could be realized.

なお、本実施例ではｎ型ドリフト領域２と、その上に形成されたｐ型ドリフト領域３との厚さを０．８μｍ、不純物濃度を約８×１０１６ａｔｍ／ｃｍ３としたが、図２及び図３に示すグラフのデータから明らかなように、ドリフト領域２及び３の厚さが０．１μｍから２μｍの間、不純物濃度が約１×１０１５ａｔｍ／ｃｍ３から３×１０１７ａｔｍ／ｃｍ３の間の値であれば高耐圧で低損失の半導体装置が得られる。図２及び３において、厚さが２μｍ以上、不純物濃度が３×１０１７ａｔｍ／ｃｍ３以上で耐圧が急減しているのは両ドリフト領域２と３が完全に空乏化する前にドリフト領域２とボディ領域４で構成される接合部で従来構造と同じような降伏が生じたためである。 In this embodiment, the thickness of the n-type drift region 2 and the p-type drift region 3 formed thereon is 0.8 μm and the impurity concentration is about 8 × 10 16 atm / cm 3 . As apparent from the graph data shown in FIGS. 2 and 3, the drift regions 2 and 3 have a thickness of 0.1 μm to 2 μm, and the impurity concentration is about 1 × 10 15 atm / cm 3 to 3 × 10 17 atm. If the value is between / cm 3 , a semiconductor device with high breakdown voltage and low loss can be obtained. 2 and 3, the breakdown voltage sharply decreases when the thickness is 2 μm or more, the impurity concentration is 3 × 10 17 atm / cm 3 or more, before the drift regions 2 and 3 are completely depleted. This is because a breakdown similar to that of the conventional structure occurred at the joint portion formed of the body region 4.

本実施例では、セグメントの形状はストライプ状であるが、例えば円形や四角形等であってもかまわない。また、本実施例ではｐ型ボディ領域４をｐ型ドリフト領域３と同じ厚さにしている。しかしｐ型ボディ領域４をｎ型ドラフト領域３より厚くしても、また逆の場合でも同等の効果を実現できる。ｐ型ボディ領域４とｎ型ドリフト領域２との間に他ｐ型ドリフト層が介在する場合（図示省略）でも同等の効果が得られる。更に、ｎ型バッファー領域６６は絶縁基板１に接するように深く形成しているが、浅くしてｎ型ドリフト領域２のみに接するようにしても良い。この場合、浅いので製作が容易になるがｎ型ドリフト領域２のコーナー部２１Ｂに電界集中が起こり耐圧が低下する場合があるので注意が必要である。   In this embodiment, the shape of the segment is a stripe shape, but it may be, for example, a circle or a rectangle. In the present embodiment, the p-type body region 4 has the same thickness as the p-type drift region 3. However, even if the p-type body region 4 is thicker than the n-type draft region 3 and vice versa, the same effect can be realized. The same effect can be obtained even when another p-type drift layer is interposed between the p-type body region 4 and the n-type drift region 2 (not shown). Further, although the n-type buffer region 66 is formed deep so as to be in contact with the insulating substrate 1, it may be made shallow so as to be in contact with only the n-type drift region 2. In this case, manufacturing is easy because it is shallow, but care must be taken because electric field concentration may occur in the corner portion 21B of the n-type drift region 2 and the withstand voltage may decrease.

《第８実施例》
図１１は本発明の半導体装置の第８実施例のＳｉＣ−ＩＧＢＴのセグメントの断面図である。図において、厚さ約３２０μｍのＳｉＣ絶縁基板１の上に、ｎ型ドリフト領域３２Ａ〜３２Ｅのそれぞれの間にｐ型ドリフト領域３３Ａ〜３３Ｄをそれぞれ挟み最上層にｐ型ドリフト領域３を形成した、ｎ型ドリフト領域とｐ型ドリフト領域の組を５組積層している。積層された両ドリフト領域３２Ａ〜３２Ｅ、３３Ａ〜３３Ｄの両端部にはそれぞれ第１のトレンチ６Ａ及び第２のトレンチ９Ａが絶縁基板１に達するように設けられている。第２のトレンチ９Ａはゲート部であり、その内壁にゲート絶縁膜３８を介してゲート電極４０が設けられている。また、第１のトレンチ６Ａにはｎ型バッファー領域６６、ｐ型コレクタ領域７７及びコレクタ電極３９が順次設けられている。最上層のｐ型ドリフト領域３のゲート電極４０に近い部分にはｐ型ボディ領域４とｎ型エミッタ領域５５が設けられ、更にこれらの領域に接続されたエミッタ電極８８が設けられている。ｐ型ドリフト領域３の表面には保護のためにＳｉ酸化膜やＳｉ窒化膜などの保護膜４５が設けられている。ドリフト領域３２Ａ〜３２Ｅとドリフト領域３３Ａ〜３３Ｄの厚さは共に約０．８μｍ、不純物濃度は約８×１０１６ａｔｍ／ｃｍ３、長さは約７５μｍである。ｐ型ボディ領域４の不純物濃度は約５×１０１７ａｔｍ／ｃｍ３、厚さは約０．８μｍであり、その中に形成されたｎ型エミッタ領域５５の不純物濃度は１×１０１９ａｔｍ／ｃｍ３、厚さは約０．２μｍである。トレンチ６Ａ内のｎ型バッファー領域６６の不純物濃度は１×１０１８ａｔｍ／ｃｍ３、ｐ型コレクタ領域７７の不純物濃度は１×１０２０ａｔｍ／ｃｍ３である。トレンチ６Ａ、９Ａの深さは共に約１０μｍである。 << Eighth embodiment >>
FIG. 11 is a sectional view of a SiC-IGBT segment of the eighth embodiment of the semiconductor device of the present invention. In the figure, on the SiC insulating substrate 1 having a thickness of about 320 μm, p-type drift regions 3 are formed in the uppermost layer with p-type drift regions 33A to 33D sandwiched between n-type drift regions 32A to 32E, respectively. Five sets of n-type drift regions and p-type drift regions are stacked. A first trench 6 </ b> A and a second trench 9 </ b> A are provided at both ends of the stacked drift regions 32 </ b> A to 32 </ b> E and 33 </ b> A to 33 </ b> D, respectively, so as to reach the insulating substrate 1. The second trench 9A is a gate portion, and a gate electrode 40 is provided on the inner wall of the second trench 9A via a gate insulating film 38. The n-type buffer region 66, the p-type collector region 77, and the collector electrode 39 are sequentially provided in the first trench 6A. A p-type body region 4 and an n-type emitter region 55 are provided in a portion of the uppermost p-type drift region 3 close to the gate electrode 40, and an emitter electrode 88 connected to these regions is further provided. A protective film 45 such as a Si oxide film or a Si nitride film is provided on the surface of the p-type drift region 3 for protection. The thicknesses of the drift regions 32A to 32E and the drift regions 33A to 33D are both about 0.8 μm, the impurity concentration is about 8 × 10 16 atm / cm 3 , and the length is about 75 μm. The p-type body region 4 has an impurity concentration of about 5 × 10 17 atm / cm 3 and a thickness of about 0.8 μm, and the n-type emitter region 55 formed therein has an impurity concentration of 1 × 10 19 atm / cm 3 . cm 3 and thickness is about 0.2 μm. The impurity concentration of the n-type buffer region 66 in the trench 6A is 1 × 10 18 atm / cm 3 , and the impurity concentration of the p-type collector region 77 is 1 × 10 20 atm / cm 3 . The depths of the trenches 6A and 9A are both about 10 μm.

本実施例のＳｉＣ−ＩＧＢＴでは、最下層のｎ型ドリフト領域３２Ａを除けば各ｎ型ドリフト領域３２Ｂ〜３２Ｅはｐ型ドリフト領域３と３３Ａ〜３３Ｄの隣り合うものに挟まれている。この構成により、コレクタ電極３９の電位がエミッター電極８８の電位より高い状態になるように高電圧を印加した時、各ｐ型ドリフト領域３３Ａ〜３３Ｄには上下両側に隣接するｎ型ドリフト領域３２Ａ〜３２Ｅから効果的に空乏層が拡がり完全に空乏化される。又各ｎ型ドリフト領域３２Ａ〜３２Ｅにも上下に隣接するｐ型ドリフト領域３３Ａ〜３３Ｄから効果的に空乏層が拡がり完全に空乏化される。その結果、バッファー領域６６からゲート電極４０の間の全てのドリフト領域３２Ａ〜３２Ｅ、３３Ａ〜３３Ｄの電位の分布はほぼ等電位分布となり、電界がドリフト領域の全域に渡ってほぼ均一になる。この電界がＳｉＣの絶縁破壊電界である約３ＭＶ／ｃｍに達するまで印加電圧を高くすることができるので、高耐圧化ができ、本実施例の場合では５８００Ｖの高い耐圧のものが実現できた。   In the SiC-IGBT of this example, each of the n-type drift regions 32B to 32E is sandwiched between adjacent p-type drift regions 3 and 33A to 33D except for the lowermost n-type drift region 32A. With this configuration, when a high voltage is applied so that the potential of the collector electrode 39 is higher than the potential of the emitter electrode 88, each of the p-type drift regions 33A to 33D has n-type drift regions 32A to 32A adjacent to the upper and lower sides. The depletion layer effectively extends from 32E and is completely depleted. Further, the depletion layers are effectively expanded from the p-type drift regions 33A to 33D adjacent to each other in the n-type drift regions 32A to 32E, and are completely depleted. As a result, the potential distributions of all the drift regions 32A to 32E and 33A to 33D between the buffer region 66 and the gate electrode 40 are substantially equipotential distributions, and the electric field is substantially uniform over the entire drift region. Since the applied voltage can be increased until this electric field reaches about 3 MV / cm, which is the dielectric breakdown electric field of SiC, a high breakdown voltage can be achieved. In the present embodiment, a high breakdown voltage of 5800 V was realized.

一方、コレクタ電極３９の電位がエミッタ電極８８の電位より高くなるように高電圧を印加するとともにゲート電極４０にしきい値以上の高い電圧を印加してオン状態にすると、ゲート電極４０近傍のｐ型ボディ領域４及び各ｐ型ドリフト領域３３Ａ〜３３Ｄの表面に電子が集められ反転層が形成される。一方、各ｎ型ドリフト領域３２Ａ〜３２Ｅのゲート電極４０近傍の表面にも電子が集められ蓄積層が形成される。ｐ型ボディ領域４の反転層はチャネルとして機能し、ｎ型エミッタ領域５５から、チャネルとして機能するｐ型ボディ領域４と上から２層目のｎ型ドリフト領域３２Ｅを通ってバッファー領域６６に電子が流入する。電子の一部はｎ型ドリフト領域３２Ｅの蓄積層と上から３層目のｐ型ドリフト領域３３Ｄの反転層を経て４層目のｎ型ドリフト領域３２Ｄに分流しバッファー領域６６に流入する。同様にして電子の一部がｎ型ドリフト領域３２Ｄの蓄積層とｐ型ドリフト領域３３Ｃの反転層を経て上から６、８、１０層目のｎ型ドリフト領域３２Ｃ、３２Ｂ、３２Ａに分流しバッファー領域６６に流れる。電子がバッファー領域６６に達するとｐ型コレクタ領域７７から正孔がｎ型ドリフト領域３２Ａ〜３２Ｅに流入し、ｐ型ドリフト領域３３Ａ〜３３Ｄの反転層とｎ型ドリフト領域３２Ａ〜３２Ｅの蓄積層を経てｐ型ボディ領域４を通りエミッタ電極８８に達する。これによりｎ型ドリフト領域３２Ａ〜３２Ｅには電子と正孔が共に存在することになり、伝導度変調が生じてｎ型ドリフト領域３２Ａ〜３２Ｅの抵抗が激減する。この過程で、各ｐ型ドリフト領域３３Ａ〜３３Ｄにも隣接するｎ型ドリフト領域から電子が注入されるために伝導度変調が生じｐ型ドリフト領域の抵抗が低減する。下層のｎ型ドリフト領域３２Ａに近くなるほどｎ型ドリフト領域３２Ａ〜３２Ｅの蓄積層とｐ型ドリフト領域３３Ａ〜３３Ｄの反転層の抵抗が加算されるので若干抵抗値が大きくなり分流電流が減少する傾向にあるが、本実施例の場合は特に問題になる程ではなかった。これによりｎ型ドリフト領域３２Ａ〜３２Ｅ及びｐ型ドリフト領域３３Ａ〜３３Ｅの抵抗は伝導度変調が生じない場合の約１／３に低減し、ＳｉＣ−ＩＧＢＴのオン抵抗を大幅に低減できる。本実施例の場合は、耐圧が５８００Ｖと高いにもかかわらず単位面積あたりのオン抵抗は１８ｍΩｃｍ２と大幅に低減できた。 On the other hand, when a high voltage is applied so that the potential of the collector electrode 39 is higher than the potential of the emitter electrode 88 and a high voltage equal to or higher than the threshold value is applied to the gate electrode 40 to turn on the p-type in the vicinity of the gate electrode 40. Electrons are collected on the surface of the body region 4 and each of the p-type drift regions 33A to 33D to form an inversion layer. On the other hand, electrons are collected on the surfaces of the n-type drift regions 32A to 32E in the vicinity of the gate electrode 40 to form a storage layer. The inversion layer of the p-type body region 4 functions as a channel, and electrons are transferred from the n-type emitter region 55 to the buffer region 66 through the p-type body region 4 functioning as a channel and the second n-type drift region 32E from above. Flows in. Part of the electrons flows through the accumulation layer of the n-type drift region 32E and the inversion layer of the third p-type drift region 33D from the top to the n-type drift region 32D of the fourth layer and flows into the buffer region 66. Similarly, a part of the electrons is divided into the sixth, eighth, and tenth n-type drift regions 32C, 32B, and 32A from the top through the accumulation layer of the n-type drift region 32D and the inversion layer of the p-type drift region 33C. Flow into region 66. When electrons reach the buffer region 66, holes flow from the p-type collector region 77 into the n-type drift regions 32A to 32E, and the inversion layers of the p-type drift regions 33A to 33D and the storage layers of the n-type drift regions 32A to 32E are formed. Then, it passes through the p-type body region 4 and reaches the emitter electrode 88. As a result, both electrons and holes exist in the n-type drift regions 32A to 32E, conductivity modulation occurs, and the resistance of the n-type drift regions 32A to 32E is drastically reduced. In this process, electrons are injected from the n-type drift region adjacent to each of the p-type drift regions 33A to 33D, so that conductivity modulation occurs and the resistance of the p-type drift region is reduced. Since the resistance of the accumulation layer of the n-type drift regions 32A to 32E and the inversion layer of the p-type drift regions 33A to 33D are added closer to the lower n-type drift region 32A, the resistance value slightly increases and the shunt current tends to decrease. However, in the case of this example, it was not particularly problematic. Thereby, the resistances of the n-type drift regions 32A to 32E and the p-type drift regions 33A to 33E are reduced to about 1/3 of the case where no conductivity modulation occurs, and the on-resistance of the SiC-IGBT can be greatly reduced. In the case of this example, the on-resistance per unit area was significantly reduced to 18 mΩcm 2 despite the high breakdown voltage of 5800V.

以上のように、本実施例によれば、高い耐圧を保ちつつ大幅にオン抵抗を低減できるという効果が得られる。各ｎ型ドリフト領域３２Ａ〜３２Ｅと各ｐ型ドリフト領域３３Ａ〜３３Ｄの組の積層数を増やすほどオン抵抗を低減することができる。但し、積層数を増やしすぎると前記のように下層のｎ型ドリフト領域３２Ａに近いものほど抵抗が増加するので、上下のｎ型ドリフト領域３２Ｅと３２Ａの抵抗をそろえるような工夫が必要となる。例えば下層になるほどｎ型ドリフト領域３２Ａ〜３２Ｅとｐ型ドリフト領域３３Ａ〜３３Ｅの厚さを少しづつ厚くしてゆくことなどが極めて有効であった。最下層のドリフト領域３３Ａの厚さの増加割合は、各ドリフト領域の長さと、ｎ型ドリフト領域とｐ型ドリフト領域の対の積層数に依存するが、例えば層数が１５層の場合には、最上層のｐ型ドリフト領域３に比べて最下層のｐ型ドリフト領域３３Ａの厚さを約１．３倍程度に増やすのが好適である。耐圧が５２００Ｖに低減してしまうがｐ型ドリフト領域３３Ａ〜３３Ｄの厚さを一定にして、ｎ型ドリフト領域３２Ａ〜３２Ｅの厚さのみ順次増やしてもオン抵抗に対しては同様の効果が得られる。この場合も最下層のｎ型ドリフト領域３２Ａの厚さは最上層のｎ型ドリフト領域３２Ｅの厚さの約１．３倍程度が好適である。   As described above, according to the present embodiment, an effect that the on-resistance can be significantly reduced while maintaining a high breakdown voltage can be obtained. The on-resistance can be reduced as the number of stacked layers of the n-type drift regions 32A to 32E and the p-type drift regions 33A to 33D is increased. However, if the number of stacked layers is excessively increased, the resistance increases as the layer is closer to the lower n-type drift region 32A as described above, and therefore, it is necessary to devise a technique for aligning the resistances of the upper and lower n-type drift regions 32E and 32A. For example, it is extremely effective to gradually increase the thicknesses of the n-type drift regions 32A to 32E and the p-type drift regions 33A to 33E as the lower layer is formed. The rate of increase in the thickness of the lowermost drift region 33A depends on the length of each drift region and the number of stacked pairs of the n-type drift region and the p-type drift region. For example, when the number of layers is 15, It is preferable to increase the thickness of the lowermost p-type drift region 33A to about 1.3 times that of the uppermost p-type drift region 3. Although the breakdown voltage is reduced to 5200 V, the same effect can be obtained with respect to the on-resistance even if the thickness of the p-type drift regions 33A to 33D is made constant and only the thickness of the n-type drift regions 32A to 32E is sequentially increased. It is done. Also in this case, the thickness of the lowermost n-type drift region 32A is preferably about 1.3 times the thickness of the uppermost n-type drift region 32E.

本半導体装置を１個の基板内に複数個形成し、これらの各半導体装置の同種の電極をそれぞれ共通に接続することにより並列接続して電力容量を増大できる。例えば、本実施例の場合並列接続によりチップ面積１ｃｍ２当たり４０Ａの電流容量にできるので、チップ面積を２５ｃｍ２にすることにより１０００Ａの電流容量のものができる。 By forming a plurality of the semiconductor devices in one substrate and connecting the same type of electrodes of each of these semiconductor devices in common, the power capacity can be increased by connecting them in parallel. For example, in the case of the present embodiment, a current capacity of 40 A per 1 cm 2 of chip area can be achieved by parallel connection. Therefore, a current capacity of 1000 A can be obtained by setting the chip area to 25 cm 2 .

《第９実施例》
図１２は本発明の半導体装置の第９実施例のシリコンＩＧＢＴ（以下Ｓｉ−ＩＧＢＴと記す）のセグメントの断面図である。厚さ約４００μｍのＳｉ基板４１の上にＳｉＯ２の絶縁膜１３を形成し、ついで順次ｎ型ドリフト領域４２Ａ〜４２Ｃのそれぞれとｐ型ドリフト領域４３Ａ〜４３Ｃとのそれぞれの組を３組積層している。積層されたドリフト領域４２Ａ〜４２Ｃ、４３Ａ〜４３Ｃの両端部近傍には深さ約１０μｍの第１及び第２のトレンチ６Ａ、９Ａが絶縁膜１３に達するように設けられている。第２のトレンチ９Ａはゲート電極４０用であり、トレンチ９Ａの内壁にゲート絶縁膜３８を介してゲート電極４０が設けられている。また、第１のトレンチ６Ａ内にはｎ型バッファー領域６６とｐ型コレクタ領域７７、コレクタ電極３９が順次設けられている。最上層のｐ型ドリフト領域４３Ｃのゲート電極４０に近い側にはｐ型ボディ領域４とｎ型エミッタ領域５５が設けられ、これらの領域に接続されるようにエミッタ電極８８が設けられている。ｐ型ドリフト領域４３Ｃの表面には保護のためにＳｉ酸化膜やＳｉ窒化膜などの保護膜４５が設けられている。ｎ型及びｐ型ドリフト領域４２Ａ〜４２Ｃ、４３Ａ〜４３Ｃの厚さは共に約１．５μｍ、不純物濃度は約２．８×１０１５ａｔｍ／ｃｍ３、長さは約３２０μｍである。ｐ型ボディ領域４の不純物濃度は約５×１０１７ａｔｍ／ｃｍ３、厚さは約０．５μｍであり、その中に形成されたｎ型エミッタ領域５５の不純物濃度は１×１０１９ａｔｍ／ｃｍ３、厚さは約０．２μｍである。トレンチ６Ａ内のｎ型バッファー領域６６の不純物濃度は１×１０１８ａｔｍ／ｃｍ３、ｐ型コレクタ領域７７の不純物濃度は１×１０２０ａｔｍ／ｃｍ３である。 << Ninth embodiment >>
FIG. 12 is a sectional view of a segment of a silicon IGBT (hereinafter referred to as Si-IGBT) of the ninth embodiment of the semiconductor device of the present invention. An SiO 2 insulating film 13 is formed on a Si substrate 41 having a thickness of about 400 μm, and then three sets of n-type drift regions 42A to 42C and p-type drift regions 43A to 43C are sequentially stacked. ing. In the vicinity of both end portions of the stacked drift regions 42A to 42C and 43A to 43C, first and second trenches 6A and 9A having a depth of about 10 μm are provided so as to reach the insulating film 13. The second trench 9A is for the gate electrode 40, and the gate electrode 40 is provided on the inner wall of the trench 9A via the gate insulating film 38. An n-type buffer region 66, a p-type collector region 77, and a collector electrode 39 are sequentially provided in the first trench 6A. A p-type body region 4 and an n-type emitter region 55 are provided on the side close to the gate electrode 40 of the uppermost p-type drift region 43C, and an emitter electrode 88 is provided so as to be connected to these regions. A protective film 45 such as a Si oxide film or a Si nitride film is provided on the surface of the p-type drift region 43C for protection. Each of the n-type and p-type drift regions 42A to 42C and 43A to 43C has a thickness of about 1.5 μm, an impurity concentration of about 2.8 × 10 15 atm / cm 3 , and a length of about 320 μm. The impurity concentration of the p-type body region 4 is about 5 × 10 17 atm / cm 3 and the thickness is about 0.5 μm. The impurity concentration of the n-type emitter region 55 formed therein is 1 × 10 19 atm / cm 3 . cm 3 and thickness is about 0.2 μm. The impurity concentration of the n-type buffer region 66 in the trench 6A is 1 × 10 18 atm / cm 3 , and the impurity concentration of the p-type collector region 77 is 1 × 10 20 atm / cm 3 .

本実施例のＳｉ−ＩＧＢＴでは、各ｎ型ドリフト領域４２Ｂ、４２Ｃはｐ型ドリフト領域４３Ａ〜４３Ｃの内のそれぞれ隣接するもので挟まれている。またｐ型ドリフト領域４３Ａは二つのｎ型ドリフト領域４２Ａ、４２Ｂに挟まれている。この状態でコレクタ電極３９の電位がエミッタ電極８８の電位より高い状態になるように高電圧を印加した時、各ドリフト領域４２Ａ〜４２Ｃ、４３Ａ〜４３Ｃには上下両側から効果的に空乏層が拡がり完全に空乏化される。その結果、バッファー領域６６からゲート電極４０に向かってドリフト領域４２Ａ〜４２Ｃ、４３Ａ〜４３Ｃの電位分布はほぼ等電位分布となり、電界がドリフト領域の全域に渡ってほぼ均一になる。この電界がＳｉの絶縁破壊電界の約０．３ＭＶ／ｃｍに達するまで印加電圧を高くすることができるので、高耐圧化ができる。本実施例の場合では４１００Ｖの高耐圧が実現できた。   In the Si-IGBT of this embodiment, the n-type drift regions 42B and 42C are sandwiched between adjacent p-type drift regions 43A to 43C. The p-type drift region 43A is sandwiched between two n-type drift regions 42A and 42B. In this state, when a high voltage is applied so that the potential of the collector electrode 39 is higher than the potential of the emitter electrode 88, depletion layers effectively spread from both the upper and lower sides in each of the drift regions 42A to 42C and 43A to 43C. Completely depleted. As a result, the potential distributions of the drift regions 42A to 42C and 43A to 43C from the buffer region 66 toward the gate electrode 40 are substantially equipotential distributions, and the electric field is substantially uniform over the entire drift region. Since the applied voltage can be increased until this electric field reaches about 0.3 MV / cm of the dielectric breakdown field of Si, a high breakdown voltage can be achieved. In the case of this example, a high withstand voltage of 4100 V was realized.

一方、コレクタ電極３９の電位がエミッタ電極８８の電位より高くなるように高電圧を印加するとともにゲート電極４０にしきい値以上の電圧を印加したオン状態では、ゲート電極４０近傍のｐ型ボディ領域４及び各ｐ型ドリフト領域４３Ａ〜４３Ｃの表面には電子が集められ反転層が形成される。また、各ｎ型ドリフト領域４２Ａ〜４２Ｃのゲート電極４０近傍の表面にも電子が集められ蓄積層が形成される。ｐ型ドリフト領域４３Ａ〜４３Ｃの反転層はチャネルとして機能し、エミッタ領域５５から前記のチャネルと、上から２層目のｎ型ドリフト領域４２Ｃを通ってバッファー領域６６に電子が流入する。電子の一部はｎ型ドリフト領域４２Ｃの蓄積層と、上から３層目のｐ型ドリフト領域４３Ｂの反転層を経て４層目のｎ型ドリフト領域４２Ｂを通りバッファー領域６６に流入する。同様にして電子の一部がｎ型ドリフト領域４２Ｂの蓄積層とｐ型ドリフト領域４３Ｂの反転層を経て６層目のｎ型ドリフト領域４２Ａを通りバッファー領域６６に流入する。電子がバッファー領域６６に達するとｐ型エミッタ領域７７から正孔がｎ型ドリフト領域４２Ａ〜４２Ｃに流入し、ｐ型ドリフト領域４３Ａ〜４３Ｃ、ｎ型ドリフト領域４２Ａ〜４２Ｃの蓄積層を経てｐ型ボディ領域４を通ってエミッタ電極８８に達する。このようにしてｎ型ドリフト領域４２Ａ〜４２Ｃには電子と正孔が共に存在することになり、伝導度変調が起こってｎ型ドリフト領域４２Ａ〜４２Ｃの抵抗が激減する。この過程で、各ｐ型ドリフト領域３３Ａ〜３３Ｄにも隣接するｎ型ドリフト領域から電子が注入されるために伝導度変調が生じｐ型ドリフト領域の抵抗が低減する。下層のｎ型ドリフト領域４２Ａに近いものほどｎ型ドリフト領域４２Ａ〜４２Ｃの蓄積層とｐ型ドリフト領域４３Ａ〜４３Ｃの反転層の抵抗が加算されるので若干抵抗が大きくなり分流電流が低減する傾向にあるが、本実施例の場合は特に問題になる程ではなかった。本実施例では、ｎ型ドリフト領域４２Ａ〜４２Ｃの抵抗は伝導度変調がない場合の約１／５に低減し、電界効果トランジスタのオン抵抗を大幅に低減できる。本実施例の場合は、耐圧を４１００Ｖと高く保ちつつ単位面積あたりのビルトイン電圧より高い電圧範囲でのオン抵抗を７１０ｍΩｃｍ２と大幅に低減できた。 On the other hand, in the ON state where a high voltage is applied so that the potential of the collector electrode 39 is higher than the potential of the emitter electrode 88 and a voltage higher than the threshold is applied to the gate electrode 40, the p-type body region 4 in the vicinity of the gate electrode 40. In addition, electrons are collected on the surfaces of the p-type drift regions 43A to 43C to form inversion layers. Further, electrons are collected on the surfaces of the n-type drift regions 42A to 42C in the vicinity of the gate electrode 40 to form a storage layer. The inversion layers of the p-type drift regions 43A to 43C function as channels, and electrons flow from the emitter region 55 to the buffer region 66 through the channel and the n-type drift region 42C that is the second layer from the top. A part of the electrons flows into the buffer region 66 through the accumulation layer in the n-type drift region 42C and the inversion layer in the third p-type drift region 43B from the top through the fourth n-type drift region 42B. Similarly, part of the electrons flows through the sixth n-type drift region 42A through the accumulation layer of the n-type drift region 42B and the inversion layer of the p-type drift region 43B and into the buffer region 66. When electrons reach the buffer region 66, holes flow from the p-type emitter region 77 into the n-type drift regions 42A to 42C and pass through the accumulation layers of the p-type drift regions 43A to 43C and the n-type drift regions 42A to 42C. It reaches the emitter electrode 88 through the body region 4. In this way, both electrons and holes exist in the n-type drift regions 42A to 42C, conductivity modulation occurs, and the resistance of the n-type drift regions 42A to 42C is drastically reduced. In this process, electrons are injected from the n-type drift region adjacent to each of the p-type drift regions 33A to 33D, so that conductivity modulation occurs and the resistance of the p-type drift region is reduced. The closer to the lower n-type drift region 42A, the resistance of the accumulation layer of the n-type drift regions 42A to 42C and the inversion layer of the p-type drift regions 43A to 43C are added, so that the resistance increases slightly and the shunt current tends to decrease. However, in the case of this example, it was not particularly problematic. In the present embodiment, the resistances of the n-type drift regions 42A to 42C are reduced to about 1/5 of the case where there is no conductivity modulation, and the on-resistance of the field effect transistor can be greatly reduced. In the case of this example, the on-resistance in a voltage range higher than the built-in voltage per unit area could be greatly reduced to 710 mΩcm 2 while keeping the breakdown voltage as high as 4100V.

以上のごとく、本実施例では耐圧を損ねることなく大幅にオン抵抗を低減できる。ｎ型ドリフト領域４２Ａ〜４２Ｃとｐ型ドリフト領域４３Ａ〜４３Ｃの組の積層数を増やすほどこのオン抵抗は低減できる。但し、積層数を増やしすぎると前記のように下層のｎ型ドリフト領域４２Ａに近いものほど抵抗が増加するので、上下のｎ型及びｐ型ドリフト領域の抵抗をそろえるような工夫が必要となる。例えば下層になるほどｎ型及びｐ型ドリフト領域を少しづつ厚くしてゆくことが極めて有効であった。最下層のドリフト領域４２Ａの厚さの増大割合はドリフト領域の長さとｎ型ドリフト領域４２Ａ〜４２Ｃとｐ型ドリフト領域４３Ａ〜４３Ｃの組の積層数に依存するが、例えば積層数が１５層の場合を例に取ると、最上層のｐ型ドリフト領域４３Ｃに対する最下層のｐ型ドリフト領域４３Ａの厚さは約１．３倍程度が好適である。このほか耐圧は若干低くなるがｐ型ドリフト領域の厚さを一定にしてｎ型ドリフト領域の厚さのみ順次増やしてもオン抵抗に関しては同様の効果が得られ、この場合も最下層のｎ型ドリフト領域４２Ａの厚さは最上層のｎ型ドリフト領域４２Ｃの厚さの約１．３倍程度が好適である。   As described above, in this embodiment, the on-resistance can be greatly reduced without impairing the breakdown voltage. The on-resistance can be reduced as the number of stacked layers of the n-type drift regions 42A to 42C and the p-type drift regions 43A to 43C is increased. However, if the number of stacked layers is increased too much, the resistance increases as the layer is closer to the lower n-type drift region 42A as described above. Therefore, it is necessary to devise a technique for aligning the resistances of the upper and lower n-type and p-type drift regions. For example, it has been extremely effective to gradually increase the thickness of the n-type and p-type drift regions as the lower layer is reached. The rate of increase in the thickness of the lowermost drift region 42A depends on the length of the drift region and the number of stacked layers of the n-type drift regions 42A to 42C and the p-type drift regions 43A to 43C. Taking the case as an example, the thickness of the lowermost p-type drift region 43A with respect to the uppermost p-type drift region 43C is preferably about 1.3 times. In addition, although the breakdown voltage is slightly lowered, the same effect can be obtained with respect to the on-resistance even if the thickness of the n-type drift region is increased successively while keeping the thickness of the p-type drift region constant. The thickness of the drift region 42A is preferably about 1.3 times the thickness of the uppermost n-type drift region 42C.

《第１０実施例》
図１３は本発明の第１０実施例のＳｉＣターンオフサイリスタ（以下、ＳｉＣ−ＧＴＯと記す）のセグメントの断面図である。厚さ約３２０μｍのＳｉＣ絶縁基板５１の上に順次、ｎ型ドリフト領域５２Ａ〜５２Ｃのそれぞれとｐ型ドリフト領域５３Ａ〜５３Ｃのそれぞれとの組を３組積層している。積層されたｎ型ドリフト領域５２Ａ〜５２Ｃとｐ型ドリフト領域５３Ａ〜５３Ｃの両端部近傍にはトレンチ６Ａ、９Ａが絶縁基板５１に達するように設けられている。トレンチ９Ａの内壁にはｐ型ベース領域９４、ｎ型エミッタ領域９５、カソード電極５８が順次設けられている。また、トレンチ６Ａの内壁には、ｎ型ベース領域８６、ｐ型エミッタ領域８７、コレクタ電極６９が順次設けられている。最上層のｐ型ドリフト領域５３Ｃのｎ型エミッタ領域９５に近い部分には、ｐ型ベース領域９４に接続されたｐ型コンタクト部１４が設けられている。コンタクト部１４はゲート電極４０に接続されている。ｐ型ドリフト領域５３Ｃの表面には保護のためにＳｉ酸化膜やＳｉ窒化膜などの保護膜４５が設けられている。ｎ型及びｐ型ドリフト領域５２Ａ〜５２Ｃ、５３Ａ〜５３Ｃの厚さは共に約０．８μｍ、不純物濃度は約８×１０１６ａｔｍ／ｃｍ３、長さは約７５μｍである。ｐ型及びｎ型ベース領域９４、８６の不純物濃度は約７×１０１７ａｔｍ／ｃｍ３、厚さは約１．２μｍである。ｎ型及びｐ型エミッタ領域９５、８７の不純物濃度は１×１０２０ａｔｍ／ｃｍ３、厚さは約０．４μｍである。トレンチ６Ａ、９Ａの深さは共に約６μｍである。 << Tenth embodiment >>
FIG. 13 is a sectional view of a segment of an SiC turn-off thyristor (hereinafter referred to as SiC-GTO) according to a tenth embodiment of the present invention. Three pairs of n-type drift regions 52A to 52C and p-type drift regions 53A to 53C are sequentially stacked on a SiC insulating substrate 51 having a thickness of about 320 μm. Trench 6A, 9A is provided in the vicinity of both end portions of n-type drift regions 52A-52C and p-type drift regions 53A-53C so as to reach insulating substrate 51. A p-type base region 94, an n-type emitter region 95, and a cathode electrode 58 are sequentially provided on the inner wall of the trench 9A. An n-type base region 86, a p-type emitter region 87, and a collector electrode 69 are sequentially provided on the inner wall of the trench 6A. A p-type contact portion 14 connected to the p-type base region 94 is provided in a portion near the n-type emitter region 95 of the uppermost p-type drift region 53C. The contact part 14 is connected to the gate electrode 40. A protective film 45 such as a Si oxide film or a Si nitride film is provided on the surface of the p-type drift region 53C for protection. Each of the n-type and p-type drift regions 52A to 52C and 53A to 53C has a thickness of about 0.8 μm, an impurity concentration of about 8 × 10 16 atm / cm 3 , and a length of about 75 μm. The p-type and n-type base regions 94 and 86 have an impurity concentration of about 7 × 10 17 atm / cm 3 and a thickness of about 1.2 μm. The n-type and p-type emitter regions 95 and 87 have an impurity concentration of 1 × 10 20 atm / cm 3 and a thickness of about 0.4 μm. The depths of the trenches 6A and 9A are both about 6 μm.

本実施例のＳｉＣ−ＧＴＯでは、ｎ型ドリフト領域５２Ｂ、５２Ｃはｐ型ドリフト領域５３Ａ〜５３Ｃの内のそれぞれ隣接するものに挟まれている。またｐ型ドリフト領域５３Ａは隣接するｎ型ドリフト領域５２Ａと５２Ｂに挟まれている。この状態で、アノード電極６９の電位がカソード電極５８の電位より高い状態になるように高電圧を印加した時、ｎ型ドリフト領域５２Ａ〜５２Ｃにはｐ型ベース領域９４及び隣接するｐ型ドリフト領域５３Ａ〜５３Ｃから効果的に空乏層が拡がり完全に空乏化される。同時にｐ型ドリフト領域５３Ａ〜５３Ｃにはｎ型ベース領域８６及び隣接するｎ型ドリフト領域５２Ａ〜５３Ｃから効果的に空乏層が拡がり完全に空乏化される。その結果、ｐ型ベース領域９４とｎ型ベース領域８６の間のドリフト領域５２Ａ〜５２Ｃ、５３Ａ〜５３Ｃの電位分布はほぼ等電位分布となり、電界がドリフト領域５２Ａ〜５２Ｃ、５３Ａ〜５３Ｃの全域に渡ってほぼ均一になる。この電界がＳｉＣの絶縁破壊電界の約３ＭＶ／ｃｍに達するまで前記印加電圧を高くすることができるので、高耐圧化ができ、本実施例の場合では４５００Ｖの高耐圧を実現できた。   In the SiC-GTO of the present embodiment, the n-type drift regions 52B and 52C are sandwiched between adjacent p-type drift regions 53A to 53C. The p-type drift region 53A is sandwiched between adjacent n-type drift regions 52A and 52B. In this state, when a high voltage is applied so that the potential of the anode electrode 69 is higher than the potential of the cathode electrode 58, the n-type drift regions 52A to 52C include the p-type base region 94 and the adjacent p-type drift region. The depletion layer effectively spreads from 53A to 53C and is completely depleted. At the same time, a depletion layer effectively extends from the n-type base region 86 and the adjacent n-type drift regions 52A to 53C to the p-type drift regions 53A to 53C and is completely depleted. As a result, the potential distributions of the drift regions 52A to 52C and 53A to 53C between the p-type base region 94 and the n-type base region 86 are substantially equipotential distributions, and the electric field is distributed throughout the drift regions 52A to 52C and 53A to 53C. It becomes almost uniform across. Since the applied voltage can be increased until this electric field reaches about 3 MV / cm of the SiC dielectric breakdown electric field, the breakdown voltage can be increased, and in the present embodiment, a high breakdown voltage of 4500 V can be realized.

通電電流の制御においては、アノード電極６９の電位がカソード電極５８の電位より高くなるように高電圧を印加するとともにゲート電極４０からゲート電流を流すことによりオンにでき、またゲート電流を引き抜くことによりオフにできる。ｐ型ベース領域９４の抵抗は絶縁基板５１に近いほど若干大きくなり分流ゲート電流が低減する傾向にあるが、本実施例の場合は特に問題になる程ではなかった。この結果、アノード電極６９とカソード電極５８間の抵抗は従来のＧＴＯの約１／５に低減できる。本実施例の場合は、耐圧を４５００Ｖに高くしたにもかかわらずビルトイン電圧より高い電圧範囲での単位面積あたりのオン抵抗は１７ｍΩｃｍ２であり大幅に低減できた。 In the control of the energization current, a high voltage is applied so that the potential of the anode electrode 69 is higher than the potential of the cathode electrode 58 and the gate current is passed from the gate electrode 40, and the gate current is extracted. Can be turned off. The resistance of the p-type base region 94 tends to be slightly larger as it is closer to the insulating substrate 51, and the shunt gate current tends to be reduced. However, in the case of the present embodiment, it was not particularly problematic. As a result, the resistance between the anode electrode 69 and the cathode electrode 58 can be reduced to about 1/5 of the conventional GTO. In the case of this example, the on-resistance per unit area in the voltage range higher than the built-in voltage was 17 mΩcm 2 even though the withstand voltage was increased to 4500 V, which could be greatly reduced.

以上のごとく、本実施例は耐圧を保ちつつ更に大幅にオン抵抗を低減できるという効果が得られる。ｎ型ドリフト領域とｐ型ドリフト領域の対の積層数を増やすほどこのオン抵抗は更に低減できる。但し、積層数を増やしすぎると前記のようにｐ型ベース領域９４の抵抗が増加するためターンオフ時に基板５１側のドリフト領域５２Ａを流れる電流を効果的に引き抜けないという不都合が生じることがある。そのような場合にはｐ型ベース領域９４の基板５１に近い部分の不純物濃度を若干増加させればよい。   As described above, the present embodiment provides an effect that the on-resistance can be further greatly reduced while maintaining the withstand voltage. The on-resistance can be further reduced as the number of stacked layers of the n-type drift region and the p-type drift region is increased. However, if the number of stacked layers is increased too much, the resistance of the p-type base region 94 increases as described above, so that there is a problem that the current flowing through the drift region 52A on the substrate 51 side cannot be effectively pulled out at the time of turn-off. In such a case, the impurity concentration in the portion near the substrate 51 in the p-type base region 94 may be slightly increased.

《第１１実施例》
図１４は、本発明の半導体装置の第１１実施例のＳｉＣ−ＭＯＳ電界効果サイリスタのセグメントの断面図である。厚さ約３２０μｍのＳｉＣ絶縁基板６１の上に、ｎ型ドリフト領域６２Ａ〜６２Ｅのそれぞれの間にｐ型ドリフト領域６３Ａ〜６３Ｅをそれぞれ挟んで形成したｎ型ドリフト領域とｐ型ドリフト領域の組を５組積層している。積層されたドリフト領域６２Ａ〜６２Ｅ、６３Ａ〜６３Ｅの両端部にはトレンチ６Ａ、９Ａが絶縁基板６１に達するように設けられている。一方のトレンチ９Ａの内壁には、ｐ型ベース領域９４、ｎ型エミッタ領域９５、カソード電極５８が順次設けられている。また、他方のトレンチ６Ａの内壁にはｎ型ベース領域８６とｐ型エミッタ領域８７、アノード電極６９が順次設けられている。最上層のｐ型ドリフト領域６３Ｅの表面及びｎ型ベース領域８６とｐ型エミッタ領域８７の端部にゲート酸化膜１１Ａを介してゲート電極７０が対向するよう形成されており、その他の表面には保護のためにＳｉ酸化膜やＳｉ窒化膜などの保護膜４５が設けられている。ドリフト領域６２Ａ〜６３Ｅ、エミッタ領域８７、９５、ベース領域８６、９４の各領域の導電型を前記のものと逆にする場合には、ゲート電極７０はｐ型ベース領域９４とｎ型エミッタ領域９５の端部にゲート酸化膜１１Ａを介して対向するように形成してもよい。ｎ型及びｐ型ドリフト領域６２Ａ〜６２Ｅ、６３Ａ〜６３Ｅの厚さは約０．８μｍ、不純物濃度は約８×１０１６ａｔｍ／ｃｍ３、長さは約７５μｍである。ｐ型及びｎ型ベース領域９４、８６の不純物濃度は共に約７×１０１７ａｔｍ／ｃｍ３、厚さは約１．２μｍである。ｎ型及びｐ型エミッタ領域９５、８７の不純物濃度は１×１０２０ａｔｍ／ｃｍ３、厚さは約０．４μｍである。トレンチ６Ａ、９Ａの深さは共に約１０μｍである。 << Eleventh embodiment >>
FIG. 14 is a sectional view of a segment of a SiC-MOS field effect thyristor according to an eleventh embodiment of the semiconductor device of the present invention. On the SiC insulating substrate 61 having a thickness of about 320 μm, a pair of an n-type drift region and a p-type drift region formed by sandwiching the p-type drift regions 63A to 63E between the n-type drift regions 62A to 62E, respectively. Five sets are stacked. Trenches 6A and 9A are provided at both ends of the stacked drift regions 62A to 62E and 63A to 63E so as to reach the insulating substrate 61. A p-type base region 94, an n-type emitter region 95, and a cathode electrode 58 are sequentially provided on the inner wall of one trench 9A. An n-type base region 86, a p-type emitter region 87, and an anode electrode 69 are sequentially provided on the inner wall of the other trench 6A. A gate electrode 70 is formed so as to face the surface of the uppermost p-type drift region 63E and the end portions of the n-type base region 86 and the p-type emitter region 87 with a gate oxide film 11A interposed therebetween. A protective film 45 such as a Si oxide film or a Si nitride film is provided for protection. When the conductivity types of the drift regions 62A to 63E, the emitter regions 87 and 95, and the base regions 86 and 94 are reversed from those described above, the gate electrode 70 includes the p-type base region 94 and the n-type emitter region 95. It may be formed so as to be opposed to the end of this through the gate oxide film 11A. The n-type and p-type drift regions 62A to 62E and 63A to 63E have a thickness of about 0.8 μm, an impurity concentration of about 8 × 10 16 atm / cm 3 , and a length of about 75 μm. Both the p-type and n-type base regions 94 and 86 have an impurity concentration of about 7 × 10 17 atm / cm 3 and a thickness of about 1.2 μm. The n-type and p-type emitter regions 95 and 87 have an impurity concentration of 1 × 10 20 atm / cm 3 and a thickness of about 0.4 μm. The depths of the trenches 6A and 9A are both about 10 μm.

本実施例のＳｉＣ−ＭＯＳ電界効果サイリスタでは、ｎ型ドリフト領域６２Ｂ〜６２Ｅはそれぞれｐ型ドリフト領域６３Ａ〜６３Ｅの内の隣接するものに挟まれている。またｐ型ドリフト領域６３Ａはｎ型ドリフト領域６２Ａ、６２Ｂにより挟まれている。これにより、アノード電極６９の電位がカソード電極５８の電位より高い状態になるように高電圧を印加した時、ｎ型ドリフト領域６２Ａ〜６２Ｅにはｐ型ベース領域９４とｐ型ドリフト領域６３Ａ〜６３Ｅから効果的に空乏層が拡がり完全に空乏化される。また、ｐ型ドリフト領域６３Ａ〜６３Ｅにはｎ型ベース領域８６とｎ型ドリフト領域６２Ａ〜６２Ｅから効果的に空乏層が拡がり完全に空乏化される。その結果、ｐ型ベース領域９４とｎ型ベース領域８６の間のドリフト領域６２Ａ〜６２Ｅ、６３Ａ〜６３Ｅの電位分布はほぼ等電位分布となり、電界がドリフト領域の全域に渡ってほぼ均一になる。この電界がＳｉＣの絶縁破壊電界の約３ＭＶ／ｃｍに達するまで印加電圧を高くすることができるので、高耐圧化ができる。本実施例の場合では４７００Ｖの高耐圧を実現できた。   In the SiC-MOS field effect thyristor of the present embodiment, the n-type drift regions 62B to 62E are sandwiched between adjacent ones of the p-type drift regions 63A to 63E. The p-type drift region 63A is sandwiched between the n-type drift regions 62A and 62B. Accordingly, when a high voltage is applied so that the potential of the anode electrode 69 is higher than the potential of the cathode electrode 58, the p-type base region 94 and the p-type drift regions 63A to 63E are applied to the n-type drift regions 62A to 62E. From this, the depletion layer is effectively expanded and completely depleted. In addition, a depletion layer effectively extends from the n-type base region 86 and the n-type drift regions 62A to 62E to the p-type drift regions 63A to 63E and is completely depleted. As a result, the potential distributions of the drift regions 62A to 62E and 63A to 63E between the p-type base region 94 and the n-type base region 86 are substantially equipotential distributions, and the electric field is substantially uniform over the entire drift region. Since the applied voltage can be increased until this electric field reaches about 3 MV / cm of the SiC dielectric breakdown electric field, a high breakdown voltage can be achieved. In this example, a high breakdown voltage of 4700 V was realized.

通電電流の制御においては、アノード電極６９がカソード電極５８より高い電位になるように高電圧を印加する。またゲート電極７０にはその電位がアノード電極６９の電位よりも低くなるように電圧を印加する。この電圧がゲート電極７０の下のｎ型ベース領域８６の表面のしきい値電圧以上になると、ｎ型ベース領域８６の表面にチャネルが形成され正孔がｐ型エミッタ領域８７からｐ型ドリフト領域６３Ｅに流入する。この正孔はｐ型ベース領域９４に達するとｎ型エミッタ領域９５からの電子の注入を促し、電子がまず最上層のｐ型ドリフト領域６３Ｅに流入する。この電子は、ｎ型エミッタ領域９５、ｐ型ベース領域９４と最上層のｐ型ドリフト領域６３Ｅ及びｎ型ベース領域８６で構成されるｎｐｎトランジスタをオンにし、ｐ型エミッタ領域８７からｎ型ベース領域８６への正孔の注入を促進する。この正孔の注入によりｐ型エミッタ領域８７、ｎ型ベース領域８６、ｐ型ドリフト領域６３Ｅで構成されるｐｎｐトランジスタをオンにし、ついには最上層のｐ型ドリフト領域６３Ｅを含むｐｎｐｐｎサイリスタをオンにする。この過程で、最上層のｐ型ドリフト領域６３Ｅの下のｎ型ドリフト領域６２Ｅの電位は最上層のｐ型ドリフト領域６３Ｅよりも高いので、ｎ型エミッタ領域９５からｐ型ドリフト領域６３Ｅに注入された電子の一部はｎ型ドリフト領域６２Ｅに流れてｎ型ベース領域８６に至り、ｐ型エミッタ領域８７からｎ型ベース領域８６、ｎ型ドリフト領域６２Ｅへの正孔の注入を促す。これにより、ｐ型エミッタ領域８７、ｎ型ベース領域８６、ｎ型ドリフト領域６２Ｅ、ｐ型ベース領域９４で構成されるｐｎｐトランジスタがオンとなり多量の正孔が前記ｐｎｐトランジスタを流れ、ｎ型エミッタ領域９５からの多量の電子の注入を促す。その結果ｎ型エミッタ領域９５、ｐ型ベース領域９４、ｎ型ドリフト領域６２Ｅ、ｎ型ベース領域８６で構成されるｎｐｎトランジスタがオンとなり、更に多量の正孔のｎ型ベース領域８６への注入を促進させることになる。これは、ｐｎｐトランジスタとｎｐｎトランジスタによる正帰還の増幅動作を招き、ついにはｐｎｎｐｎサイリスタがオンする。また、この過程で、３層目のｐ型ドリフト領域６３Ｄの電位が２層目のｎ型ドリフト領域６２Ｅよりも低いので、ｐ型エミッタ領域８７からｎ型ドリフト領域６２Ｅに注入された正孔の一部は、ｐ型ドリフト領域６３Ｄを流れ、ｐ型ベース領域９４に至る。これによりｎ型エミッタ領域９５からｐ型ベース領域９４、ｐ型ドリフト領域６３Ｄへの電子の注入を促し、３層目のｎｐｎトランジスタをオンにし、ついで３層目のｐｎｐトランジスタをオンにする。その結果３層目のｎｐｎトランジスタとｐｎｐトランジスタで構成される３層目のｐｎｐｐｎサイリスタがオンになる。このようにして、順次ｎ型及びｐ型ドリフト領域６２Ｄ、６３Ｃ、６２Ｃ、６３Ｂ，６２Ｂ、６３Ａ及び６２Ａを含む第４、５、６、７、８、９及び１０層目のサイリスタがオンになり、ついにはＳｉＣ−ＭＯＳ電界効果サイリスタ全体がオンになる。   In controlling the energization current, a high voltage is applied so that the anode electrode 69 has a higher potential than the cathode electrode 58. A voltage is applied to the gate electrode 70 so that the potential is lower than the potential of the anode electrode 69. When this voltage becomes equal to or higher than the threshold voltage of the surface of the n-type base region 86 under the gate electrode 70, a channel is formed on the surface of the n-type base region 86 and holes are transferred from the p-type emitter region 87 to the p-type drift region. It flows into 63E. When the holes reach the p-type base region 94, the holes prompt the injection of electrons from the n-type emitter region 95, and the electrons first flow into the uppermost p-type drift region 63E. The electrons turn on the npn transistor composed of the n-type emitter region 95, the p-type base region 94, the uppermost p-type drift region 63E and the n-type base region 86, and the p-type emitter region 87 to the n-type base region. It facilitates the injection of holes into 86. This hole injection turns on the pnp transistor including the p-type emitter region 87, the n-type base region 86, and the p-type drift region 63E, and finally turns on the pnppn thyristor including the uppermost p-type drift region 63E. To do. In this process, since the potential of the n-type drift region 62E under the uppermost p-type drift region 63E is higher than that of the uppermost p-type drift region 63E, it is injected from the n-type emitter region 95 into the p-type drift region 63E. A part of the electrons flow into the n-type drift region 62E and reach the n-type base region 86, and the injection of holes from the p-type emitter region 87 to the n-type base region 86 and the n-type drift region 62E is promoted. As a result, the pnp transistor including the p-type emitter region 87, the n-type base region 86, the n-type drift region 62E, and the p-type base region 94 is turned on, and a large amount of holes flow through the pnp transistor. Encourage injection of large quantities of electrons from 95. As a result, the npn transistor including the n-type emitter region 95, the p-type base region 94, the n-type drift region 62E, and the n-type base region 86 is turned on, and more holes are injected into the n-type base region 86. It will be promoted. This causes a positive feedback amplification operation by the pnp transistor and the npn transistor, and finally the pnnpn thyristor is turned on. Further, in this process, since the potential of the third layer p-type drift region 63D is lower than that of the second layer n-type drift region 62E, holes injected from the p-type emitter region 87 into the n-type drift region 62E A part flows through the p-type drift region 63D and reaches the p-type base region 94. As a result, injection of electrons from the n-type emitter region 95 to the p-type base region 94 and the p-type drift region 63D is promoted, and the third-layer npn transistor is turned on, and then the third-layer pnp transistor is turned on. As a result, the third-layer pnppn thyristor composed of the third-layer npn transistor and pnp transistor is turned on. Thus, the fourth, fifth, sixth, seventh, eighth, ninth and tenth thyristors including the n-type and p-type drift regions 62D, 63C, 62C, 63B, 62B, 63A and 62A are sequentially turned on. Finally, the entire SiC-MOS field effect thyristor is turned on.

本実施例の場合は、耐圧を４７００Ｖと高くできたにもかかわらず、ビルトイン電圧以上の高い電圧範囲での単位面積あたりのオン抵抗は１１ｍΩｃｍ２となり大幅に低減できた。また、ＭＯＳゲート型の半導体装置なのでゲート電極７０を含むゲート回路の消費電力は第１０の実施例のＳｉＣ−ＧＴＯに比べて大幅に低減できる。 In the case of this example, the on-resistance per unit area in a high voltage range equal to or higher than the built-in voltage was 11 mΩcm 2 even though the withstand voltage could be increased to 4700 V, which could be greatly reduced. Further, since it is a MOS gate type semiconductor device, the power consumption of the gate circuit including the gate electrode 70 can be significantly reduced as compared with the SiC-GTO of the tenth embodiment.

以上のごとく、本実施例は耐圧を高く保ちつつ大幅にオン抵抗を低減できるという効果があり、半導体装置の消費電力を大幅に低減できるとともに、ゲート電極７０につながるゲート駆動回路の消費電力も低減できる。なお、ｎ型ドリフト領域６２Ａ〜６２Ｅとｐ型ドリフト領域６３Ａ〜６３Ｅの組の積層数を増やすほどこのオン抵抗は低減できる。   As described above, the present embodiment has an effect that the on-resistance can be significantly reduced while maintaining a high breakdown voltage, so that the power consumption of the semiconductor device can be greatly reduced, and the power consumption of the gate driving circuit connected to the gate electrode 70 is also reduced. it can. The on-resistance can be reduced as the number of stacked layers of the n-type drift regions 62A to 62E and the p-type drift regions 63A to 63E is increased.

以上、第１から第１１の実施例について詳細に説明したが、本発明は更に多くの適用範囲あるいは派生構造を包含するものである。例えば同一基板上に形成した基本となる素子を多数並列に接続することにより、大電流・大容量化を実現できる。また、ＳｉＣ絶縁基板としてはバナジュウムを含んだＳｉＣ基板に限定されるものではなく、サファイア絶縁基板やクロムを含んだガリウム砒素絶縁基板等を使用してもよい。   Although the first to eleventh embodiments have been described in detail above, the present invention includes more application ranges or derived structures. For example, a large current and large capacity can be realized by connecting a large number of basic elements formed on the same substrate in parallel. The SiC insulating substrate is not limited to the SiC substrate containing vanadium, and a sapphire insulating substrate, a gallium arsenide insulating substrate containing chromium, or the like may be used.

前記各実施例では、ＳｉとＳｉＣを用いた素子の場合について説明したが、本発明は、ダイヤモンド、ガリウムナイトライド、アルミニュウムナイトライド、硫化亜鉛など他の半導体材料を用いた素子にも有効である。前記各実施例のトレンチ６Ａ、９Ａは内壁面が垂直に近いが内壁面をすり鉢状のゆるやかな傾斜にした溝状（グルーブ）に形成してもよい。このようにすると、ｎ型及びｐ型ドリフト層の組の数が１０組以上と多いときの埋込領域や電極の形成が容易になり、コスト低減と歩留りの向上に有利となる。   In each of the above-described embodiments, the case of an element using Si and SiC has been described. However, the present invention is also effective for an element using other semiconductor materials such as diamond, gallium nitride, aluminum nitride, and zinc sulfide. . The trenches 6A and 9A in each of the above embodiments may be formed in a groove shape (groove) in which the inner wall surface is nearly vertical but the inner wall surface has a mortar-like shape. This makes it easy to form buried regions and electrodes when the number of n-type and p-type drift layers is as large as 10 or more, which is advantageous for cost reduction and yield improvement.

また、前記の各実施例において、ｎ型領域をｐ型領域に、ｐ型領域をｎ型領域に置き変えた場合でも本発明の構成を適用できる。   In each of the above embodiments, the configuration of the present invention can be applied even when the n-type region is replaced with a p-type region and the p-type region is replaced with an n-type region.

本発明の半導体装置の耐圧は、ｐ型ドリフト領域とｎ型ドリフト領域の厚さの差や不純物濃度の差に影響を受ける。従って本発明の目的を効果的に達成するためには、ｐ型ドリフト領域とｎ型ドリフト領域の厚さの差は±２０％以下に、不純物濃度の差は±２５０％以下にするのが好適である。   The breakdown voltage of the semiconductor device of the present invention is affected by the difference in thickness between the p-type drift region and the n-type drift region and the difference in impurity concentration. Therefore, in order to effectively achieve the object of the present invention, it is preferable that the difference in thickness between the p-type drift region and the n-type drift region is ± 20% or less and the difference in impurity concentration is ± 250% or less. It is.

本発明の電界効果トランジスタの第１実施例を示す断面図Sectional drawing which shows 1st Example of the field effect transistor of this invention 本発明の第１実施例の電界効果トランジスタの耐圧とドリフト領域の不純物濃度との関係を示すグラフThe graph which shows the relationship between the proof pressure of the field effect transistor of 1st Example of this invention, and the impurity concentration of a drift region. 本発明の第１実施例の電界効果トランジスタの耐圧とドリフト領域の厚さの関係を示すグラフThe graph which shows the relationship between the proof pressure of the field effect transistor of 1st Example of this invention, and the thickness of a drift region. 本発明の電界効果トランジスタの第２実施例を示す断面図Sectional drawing which shows 2nd Example of the field effect transistor of this invention 本発明の電界効果トランジスタの第３実施例を示す断面図Sectional drawing which shows 3rd Example of the field effect transistor of this invention 本発明の電界効果トランジスタの第３実施例の他の例を示す断面図Sectional drawing which shows the other example of 3rd Example of the field effect transistor of this invention 本発明の電界効果トランジスタの第４実施例を示す断面図Sectional drawing which shows 4th Example of the field effect transistor of this invention 本発明の電界効果トランジスタの第５実施例を示す断面図Sectional drawing which shows 5th Example of the field effect transistor of this invention 本発明の電界効果トランジスタの第６実施例を示す断面図Sectional drawing which shows 6th Example of the field effect transistor of this invention 本発明の第７実施例のＳｉＣ−ＩＧＢＴの断面図Sectional drawing of SiC-IGBT of 7th Example of this invention 本発明の第８実施例のＳｉＣ−ＩＧＢＴの断面図Sectional drawing of SiC-IGBT of 8th Example of this invention 本発明の第９実施例のＳｉ−ＩＧＢＴの断面図Sectional drawing of Si-IGBT of 9th Example of this invention 本発明の第１０実施例のＳｉＣ−ＧＴＯの断面図Sectional drawing of SiC-GTO of 10th Example of this invention 本発明の第１１実施例のＳｉＣ−ＭＯＳサイリスタの断面図Sectional drawing of the SiC-MOS thyristor of 11th Example of this invention 従来のトレンチ型電界効果半導体装置の断面図Sectional view of a conventional trench field effect semiconductor device 従来の高耐圧半導体装置の断面図Sectional view of a conventional high voltage semiconductor device

符号の説明Explanation of symbols

１ 絶縁基板
２ ｎ型ドリフト領域
３ ｐ型ドリフト領域
４ ｐ型ボディ領域
５ ソース領域
６、１６ ドレイン領域
６Ａ トレンチ
７ ソース電極
８ ドレイン電極
９、１９ 酸化膜
９Ａ トレンチ
１０ ゲート電極
１１ 表面保護膜
１２ ｐ型ドリフト領域
１４ ｐ型コンタクト部
２２、２２Ａ、２２Ｂ、２２Ｃ、２２Ｄ ｎ型ドリフト領域
２３、２３Ａ、２３Ｂ、２２Ｃ ｐ型ドリフト領域
３２Ａ〜３２Ｅ ｎ型ドリフト領域
３３ ｐ型ドリフト領域
３３Ａ〜３３Ｄ ｐ型ドリフト領域
３４ ボディ領域
３７ ソース電極
３９ コレクタ電極
４０ ゲート電極
４１ Ｓｉ基板
４２Ａ〜４２Ｃ ｎ型ドリフト領域
４３Ａ〜４３Ｃ ｐ型ドリフト領域
５１ 絶縁基板
５２Ａ〜５２Ｃ ｎ型ドリフト領域
５３Ａ〜５３Ｃ ｐ型ドリフト領域
５５ エミッタ領域
５８ カソード電極
６２Ａ〜６２Ｅ ｎ型ドリフト領域
６３Ａ〜６３Ｅ ｐ型ドリフト領域
６６ バッファー領域
６８ ゲート電極
６９ アノード電極
７０ ゲート電極
７７ コレクタ領域
８６ ｎ型ベース領域
８７ ｐ型エミッタ領域
８８ エミッタ電極
９４ ｐ型ベース領域
９５ ｎ型エミッタ領域
１０１ ドレイン領域
１０２ ドリフト領域
１０３ ボディ領域
１０４ ソース領域
１０５ ゲート絶縁膜
１０６ ゲート電極
１０７ ソース電極
１０８ ドレイン電極
１１０ 凹部 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 n-type drift region 3 p-type drift region 4 p-type body region 5 source region 6, 16 drain region 6A trench 7 source electrode 8 drain electrode 9, 19 oxide film 9A trench 10 gate electrode 11 surface protective film 12 p Type drift region 14 p type contact portion 22, 22A, 22B, 22C, 22D n type drift region 23, 23A, 23B, 22C p type drift region 32A to 32E n type drift region 33 p type drift region 33A to 33D p type drift Region 34 Body region 37 Source electrode 39 Collector electrode 40 Gate electrode 41 Si substrate 42A-42C n-type drift region 43A-43C p-type drift region 51 Insulating substrate 52A-52C n-type drift region 53A-53C p-type drift region 55 emitter region 58 Sword electrodes 62A to 62E n-type drift region 63A to 63E p-type drift region 66 buffer region 68 gate electrode 69 anode electrode 70 gate electrode 77 collector region 86 n-type base region 87 p-type emitter region 88 emitter electrode 94 p-type base region 95 n-type emitter region 101 drain region 102 drift region 103 body region 104 source region 105 gate insulating film 106 gate electrode 107 source electrode 108 drain electrode 110 recess

Claims (20)

高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の両方に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、
前記第１のドリフト領域、前記ボディ領域及び第１の導電型の領域に形成したトレンチの内壁面に形成した絶縁膜、及び
前記トレンチの内壁面に前記絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定されたことを特徴とするワイドギャップ半導体装置。 First drift region of a first conductivity type formed on the high-resistance wide-gap semiconductor substrate,
The first was formed on the drift region, the first second conductive type second drift region that have a same impurity concentration as the same thickness as the drift region,
A buried region of a first conductivity type formed so as to be in contact with the first and second drift regions;
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region formed in contact with both the drift region,
A first conductivity type region formed in a part of the body region;
A second electrode provided in the body region and the region of the first conductivity type ;
An insulating film formed on an inner wall surface of a trench formed in the first drift region, the body region, and the first conductivity type region; and
A control electrode provided on the inner wall surface of the trench via the insulating film ,
The thickness of the first and second drift region, upon application of the rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A wide gap semiconductor device characterized by being selected to be 高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
前記基板と第１のドリフト領域の間に設けられ、前記第２のドリフト領域と同じ厚さと同じ不純物濃度を有する第３のドリフト領域、
前記第１、第２及び第３のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の両方に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、
前記第１のドリフト領域、前記ボディ領域及び第１の導電型の領域に形成したトレンチの内壁面に形成した絶縁膜、及び
前記トレンチの内壁面に前記絶縁膜を介して設けた制御電極を備え、
前記第１のドリフト領域の厚さが、前記第２のドリフト領域及び第３のドリフト領域の厚さより厚く、前記第１、第２及び第３のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１、第２及び第３のドリフト領域が完全な空乏層となるように選定されたことを特徴とするワイドギャップ半導体装置。 First drift region of a first conductivity type formed on the high-resistance wide-gap semiconductor substrate,
The first was formed on the drift region, a second drift region of a second conductivity type that have a first same impurity concentration as the drift region,
A third drift region provided between the substrate and the first drift region and having the same thickness and the same impurity concentration as the second drift region;
A buried region of a first conductivity type formed so as to be in contact with the first , second and third drift regions;
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region formed in contact with both the drift region,
A first conductivity type region formed in a part of the body region;
A second electrode provided in the body region and the region of the first conductivity type ;
An insulating film formed on an inner wall surface of a trench formed in the first drift region, the body region and the first conductivity type region, and a control electrode provided on the inner wall surface of the trench via the insulating film. ,
The thickness of the first drift region is greater than the thickness of the second drift region and the third drift region, and the thickness of the first , second, and third drift regions is the first electrode. If when applying the rated voltage between the second electrode, the first, wide-gap semiconductor device, characterized in that the second and third drift region is chosen to be the entire depletion layer complete. 前記埋込領域が基板に接していることを特徴とする請求項１又は２記載のワイドギャップ半導体装置。 3. The wide gap semiconductor device according to claim 1, wherein the buried region is in contact with the substrate. 高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
前記基板、前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の両方に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、
前記第１のドリフト領域、前記ボディ領域及び第１の導電型の領域を貫通して前記基板に達するトレンチの内壁面に形成した絶縁膜、及び
前記トレンチの内壁面に前記絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定されたことを特徴とするワイドギャップ半導体装置。 First drift region of a first conductivity type formed on the high-resistance wide-gap semiconductor substrate,
The first was formed on the drift region, the first second conductive type second drift region that have a same impurity concentration as the same thickness as the drift region,
The substrate, prior Symbol first conductivity type buried region formed in contact both with the first and second drift regions,
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region formed in contact with both the drift region,
A first conductivity type region formed in a part of the body region;
A second electrode provided in the body region and the region of the first conductivity type ;
An insulating film formed on an inner wall surface of a trench that penetrates the first drift region, the body region, and the first conductivity type region and reaches the substrate; and
A control electrode provided on the inner wall surface of the trench via the insulating film ,
The thickness of the first and second drift region, upon application of the rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A wide gap semiconductor device characterized by being selected to be 高抵抗のワイドギャップ半導体の基板上に形成した第２の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第１の導電型の第２のドリフト領域、
前記基板、及び前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記基板及び前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記第１導電型の領域及びボディ領域に設けた第２の電極、及び
前記ボディ領域、前記第１の領域及び前記第２のドリフト領域上に絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定されたことを特徴とするワイドギャップ半導体装置。 A first drift region of a second conductivity type formed on a substrate of a high resistance wide gap semiconductor;
A second drift region of the first conductivity type formed on the first drift region and having the same thickness and the same impurity concentration as the first drift region;
The substrate, and the first conductive type buried region formed in contact both with the first and second drift regions,
A first electrode formed in the buried region;
A body region of a second conductivity type formed so as to be separated from the buried region by a predetermined distance and in contact with the substrate and the first and second drift regions;
A first conductivity type region formed in a part of the body region;
A second electrode provided in the first conductivity type region and the body region; and a control electrode provided via an insulating film on the body region , the first region and the second drift region ,
The thickness of the first and second drift region, upon application of the rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A wide gap semiconductor device characterized by being selected to be 高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、
前記ボディ領域に接して表面にまで延長された第１導電型のドリフト領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記第１導電型の領域及びボディ領域に設けた第２の電極、及び
前記表面にまで延長された第１のドリフト領域、前記ボディ領域及び前記第１の導電型領域上に絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定したことを特徴とするワイドギャップ半導体装置。 First drift region of a first conductivity type formed on the high-resistance wide-gap semiconductor substrate,
The first was formed on the drift region, the first second conductive type second drift region that have a same impurity concentration as the same thickness as the drift region,
A first conductivity type buried region formed in contact both with the first and second drift regions,
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region forms the shape in contact with the drift region,
A first conductivity type drift region extending to the surface in contact with the body region;
A first conductivity type region formed in a part of the body region;
The second electrode provided on the first conductivity type region and the body region, and the first drift region, which is extended to the surface, through the insulating layer in the body region and the first conductivity type region on A control electrode provided,
The thickness of the first and second drift regions, when applying a rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A wide gap semiconductor device characterized by being selected to be 高抵抗の第１の種類の材料を用いたワイドギャップ半導体の基板上に形成した、低抵抗の第２の種類の材料を用いた第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する前記第２の種類の材料を用いた第２の導電型の第２のドリフト領域、
前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記第１導電型の領域及びボディ領域に設けた第２の電極、及び
前記ボディ領域及び前記第１の導電型の領域を貫通して前記第１のドリフト領域に達するトレンチの内壁面に絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定されたことを特徴とするワイドギャップ半導体装置。 A first drift region of a first conductivity type using a low resistance second type material formed on a wide gap semiconductor substrate using a high resistance first type material;
The first was formed on the drift region, the first second conductive type second drift region with the second type of material having the same impurity concentration as the same thickness as the drift region,
A first conductivity type buried region formed in contact both with the first and second drift regions,
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region formed in contact with the drift region,
A first conductivity type region formed in a part of the body region;
A second electrode provided in the first conductivity type region and the body region ; and an insulating film on an inner wall surface of the trench reaching the first drift region through the body region and the first conductivity type region A control electrode provided via
The thickness of the first and second drift region, upon application of the rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A wide gap semiconductor device characterized by being selected to be 前記第１の種類の材料が、バナジュームを含んだＳｉＣ、サファイア及びクロムを含んだガリウム砒素から選択した１種の材料であり、
前記第２の種類の材料が、ＳｉＣ、ダイヤモンド、ガリウムナイトライド、アルミニュウムナイトライド及び硫化亜鉛から選択した１種の材料である請求項７記載のワイドギャップ半導体装置。 The first type of material is a material selected from SiC containing vanadium, sapphire and gallium arsenide containing chromium;
8. The wide gap semiconductor device according to claim 7, wherein the second type material is one material selected from SiC, diamond, gallium nitride, aluminum nitride, and zinc sulfide. 前記ワイドギャップ半導体基板の材料が、バナジュームを含んだＳｉＣ、サファイア及びクロムを含んだガリウム砒素から選択した１種の材料であり、
前記第１及び第２のドリフト領域及びボディ領域の材料が、ＳｉＣ、ダイヤモンド、ガリウムナイトライド、アルミニュウムナイトライド及び硫化亜鉛から選択した１種の材料である請求項１、２、４、５又は６記載のワイドギャップ半導体装置。 The material of the wide gap semiconductor substrate is one material selected from SiC containing vanadium, sapphire and gallium arsenide containing chromium,
The material of the first and second drift regions and the body region, SiC, diamond, claim 1 gallium nitride, which is one material selected from aluminum Niu arm nitride and zinc sulfide, 2, 4, 5 or 6 The wide gap semiconductor device described. 基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の両方に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、
前記第１のドリフト領域、前記ボディ領域及び第１の導電型の領域に形成したトレンチの内壁面に形成した絶縁膜、及び
前記トレンチの内壁面に前記絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定されたことを特徴とする半導体装置。 First drift region of a first conductivity type formed on the substrate,
The first was formed on the drift region, the first second conductive type second drift region that have a same impurity concentration as the same thickness as the drift region,
A buried region of a first conductivity type formed so as to be in contact with the first and second drift regions;
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region formed in contact with both the drift region,
A first conductivity type region formed in a part of the body region;
A second electrode provided in the body region and the region of the first conductivity type ;
An insulating film formed on an inner wall surface of a trench formed in the first drift region, the body region, and the first conductivity type region; and
A control electrode provided on the inner wall surface of the trench via the insulating film ,
The thickness of the first and second drift region, upon application of the rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A semiconductor device characterized by being selected. 基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
前記基板と第１のドリフト領域の間に設けられ、前記第２のドリフト領域と同じ厚さと同じ不純物濃度を有する第３のドリフト領域、
前記第１、第２及び第３のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の両方に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、
前記第１のドリフト領域、前記ボディ領域及び第１の導電型の領域に形成したトレンチの内壁面に形成した絶縁膜、及び
前記トレンチの内壁面に前記絶縁膜を介して設けた制御電極を備え、
前記第１のドリフト領域の厚さが、前記第２のドリフト領域及び第３のドリフト領域の厚さより厚く、前記第１、第２及び第３のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１、第２及び第３のドリフト領域が完全な空乏層となるように選定されたことを特徴とする半導体装置。 First drift region of a first conductivity type formed on the substrate,
The first was formed on the drift region, a second drift region of a second conductivity type that have a first same impurity concentration as the drift region,
A third drift region provided between the substrate and the first drift region and having the same thickness and the same impurity concentration as the second drift region;
A buried region of a first conductivity type formed so as to be in contact with the first , second and third drift regions;
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region formed in contact with both the drift region,
A first conductivity type region formed in a part of the body region;
A second electrode provided in the body region and the region of the first conductivity type ;
An insulating film formed on an inner wall surface of a trench formed in the first drift region, the body region and the first conductivity type region, and a control electrode provided on the inner wall surface of the trench via the insulating film. ,
The thickness of the first drift region is greater than the thickness of the second drift region and the third drift region, and the thickness of the first , second, and third drift regions is the first electrode. If when applying the rated voltage between the second electrode, the first semiconductor device in which the second and third drift region is characterized by being chosen to be all the depletion layer complete. 前記埋込領域が基板に接していることを特徴とする請求項１０又は１１記載の半導体装置。 Said buried region is a semiconductor device according to claim 10 or 11 further characterized in that in contact with the substrate. 基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
基板、前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域の両方に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記ボディ領域及び前記第１の導電型の領域に設けた第２の電極、
前記第１のドリフト領域、前記ボディ領域及び第１の導電型の領域を貫通して前記基板に達するトレンチの内壁面に形成した絶縁膜、及び
前記トレンチの内壁面に前記絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定されたことを特徴とする半導体装置。 First drift region of a first conductivity type formed on the substrate,
The first was formed on the drift region, the first second conductive type second drift region that have a same impurity concentration as the same thickness as the drift region,
A buried region of a first conductivity type formed so as to be in contact with the substrate and the first and second drift regions;
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region formed in contact with both the drift region,
A first conductivity type region formed in a part of the body region;
A second electrode provided in the body region and the region of the first conductivity type ;
An insulating film formed on an inner wall surface of a trench that penetrates the first drift region, the body region, and the first conductivity type region and reaches the substrate; and
A control electrode provided on the inner wall surface of the trench via the insulating film ,
The thickness of the first and second drift region, upon application of the rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A semiconductor device characterized by being selected. 基板上に形成した第２の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第１の導電型の第２のドリフト領域、
前記基板、及び前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記基板及び前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記第１導電型の領域及びボディ領域に設けた第２の電極、及び
前記ボディ領域、前記第１の領域及び前記第２のドリフト領域上に絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定されたことを特徴とする半導体装置。 A first drift region of a second conductivity type formed on the substrate ;
A second drift region of the first conductivity type formed on the first drift region and having the same thickness and the same impurity concentration as the first drift region;
The substrate, and the first conductive type buried region formed in contact both with the first and second drift regions,
A first electrode formed in the buried region;
A body region of a second conductivity type formed so as to be separated from the buried region by a predetermined distance and in contact with the substrate and the first and second drift regions;
A first conductivity type region formed in a part of the body region;
A second electrode provided in the first conductivity type region and the body region; and a control electrode provided via an insulating film on the body region , the first region and the second drift region ,
The thickness of the first and second drift region, upon application of the rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A semiconductor device characterized by being selected. 基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、
前記ボディ領域に接して表面にまで延長された第１導電型のドリフト領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記第１導電型の領域及びボディ領域に設けた第２の電極、及び
前記表面にまで延長された第１のドリフト領域、前記ボディ領域及び前記第１の導電型領域上に絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さを、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定したことを特徴とする半導体装置。 First drift region of a first conductivity type formed on the substrate,
The first was formed on the drift region, the first second conductive type second drift region that have a same impurity concentration as the same thickness as the drift region,
A first conductivity type buried region formed in contact both with the first and second drift regions,
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region forms the shape in contact with the drift region,
A first conductivity type drift region extending to the surface in contact with the body region;
A first conductivity type region formed in a part of the body region;
The second electrode provided on the first conductivity type region and the body region, and the first drift region, which is extended to the surface, through the insulating layer in the body region and the first conductivity type region on A control electrode provided,
The thickness of the first and second drift regions, when applying a rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A semiconductor device, characterized by being selected. 基板上に形成した、低抵抗の材料を用いた第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する前記低抵抗の材料を用いた第２の導電型の第２のドリフト領域、
前記第１及び第２のドリフト領域に共に接するように形成した第１の導電型の埋込領域、
前記埋込領域に形成した第１の電極、
前記埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記第１の導電型の領域に設けた第２の電極、及び
前記ボディ領域及び前記第１の導電型の領域を貫通して前記第１のドリフト領域に達するトレンチの内壁面に絶縁膜を介して設けた制御電極を備え、
前記第１及び第２のドリフト領域の厚さが、前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように選定されたことを特徴とする半導体装置。 Formed on the substrate, a first drift region of a first conductivity type using the wood charge a low resistance,
The first was formed on the drift region, the first second conductive type second drift region using said low-resistance material having the same impurity concentration as the same thickness as the drift region,
A first conductivity type buried region formed in contact both with the first and second drift regions,
A first electrode formed in the buried region;
Wherein apart from the buried region by a predetermined distance, said first and second second conductivity type body region formed in contact with the drift region,
A first conductivity type region formed in a part of the body region;
A second electrode provided in the region of the first conductivity type ; and an inner wall surface of a trench reaching the first drift region through the body region and the region of the first conductivity type via an insulating film Control electrode provided,
The thickness of the first and second drift region, upon application of the rated voltage between the first electrode and the second electrode, the first and second drift region and depletion whole complete A semiconductor device characterized by being selected. 前記低抵抗の材料が、ＳｉＣ、ダイヤモンド、ガリウムナイトライド、アルミニュウムナイトライド及び硫化亜鉛から選択した１種の材料である請求項１６に記載の半導体装置。 The semiconductor device according to claim 16 , wherein the low-resistance material is one material selected from SiC, diamond, gallium nitride, aluminum nitride, and zinc sulfide. 前記第１及び第２のドリフト領域及びボディ領域の材料が、ＳｉＣ、ダイヤモンド、ガリウムナイトライド、アルミニュウムナイトライド及び硫化亜鉛から選択した１種の材料である請求項１０、１１、１３、１４又は１５記載の半導体装置。 The material of the first and second drift regions and the body region is one material selected from SiC, diamond, gallium nitride, aluminum nitride, and zinc sulfide, 10 , 11 , 13 , 14 or 15 The semiconductor device described. 高抵抗のワイドギャップ半導体の基板上に形成した第１の導電型の第１のドリフト領域、
前記第１のドリフト領域の上に形成した、前記第１のドリフト領域と同じ厚さと同じ不純物濃度を有する第２の導電型の第２のドリフト領域、
前記第１及び第２のドリフト領域に共に接するように形成した、前記第１及び第２のドリフト領域よりも高い不純物濃度を有する第１の導電型の第１の埋込領域、
前記第１の導電型の第１の埋込領域に接して形成した高不純物濃度を有する第２の導電型の第２の埋込領域、
前記第２の導電型の第２の埋込領域に形成した第１の電極、
前記第１の埋込領域から所定の距離だけ離れ、前記第１及び第２のドリフト領域に接するように形成した第２の導電型のボディ領域、
前記ボディ領域の一部に形成した第１の導電型の領域、
前記第１の導電型の領域に形成した第２の電極、
前記第１のドリフト領域、前記ボディ領域及び第１の導電型の領域に形成したトレンチの内壁面に形成した絶縁膜、及び
前記トレンチの内壁面に前記絶縁膜を介して設けた制御電極、
を備えたバイポーラ半導体装置であって、
前記第１の電極と第２の電極間に定格電圧を印加したとき、前記第１及び第２のドリフト領域が完全な空乏層となるように前記第１及び第２のドリフト領域の厚さが選定されたことを特徴とするバイポーラ半導体装置。 First drift region of a first conductivity type formed on the high-resistance wide-gap semiconductor substrate,
The first was formed on the drift region, a second drift region of the second conductivity type having a first same impurity concentration as the same thickness as the drift region,
The first及 beauty was formed so as to contact both the second drift region, the first buried region of the first conductivity type that have a said higher impurity concentration than the first及 beauty second drift region ,
It said first conductivity type first second conductivity type second buried region of that having a high impurity concentration formed in contact with the buried region,
A first electrode formed in a second buried region of the second conductivity type;
A body region of a second conductivity type formed so as to be separated from the first buried region by a predetermined distance and in contact with the first and second drift regions;
A first conductivity type region formed in a part of the body region;
A second electrode formed in the region of the first conductivity type;
An insulating film formed on an inner wall surface of a trench formed in the first drift region, the body region, and the first conductivity type region; and
A control electrode provided on the inner wall surface of the trench via the insulating film ,
A bipolar semiconductor device comprising:
The thickness of the case of applying the rated voltage between the first electrode and the second electrode, the first and second drift region such that the first and second drift regions is complete depletion A bipolar semiconductor device characterized in that is selected. 前記半導体装置が１個の基板に複数個形成され、各半導体装置の同種の電極がそれぞれ共通に接続されたことを特徴とする請求項１、２、４、５、６、７、１０、１１、１３、１４、１５、１６又は１９に記載の半導体装置。 The semiconductor device is formed in plural on one substrate, according to claim 1 in which the same kind of electrodes of each semiconductor device is characterized in that it is connected in common, respectively, 2, 4, 5, 6, 7, 10, 11 , 13 , 14 , 15 , 16 or 19 .
JP2006211156A 1999-05-21 2006-08-02 Semiconductor device Expired - Fee Related JP4653704B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006211156A JP4653704B2 (en) 1999-05-21 2006-08-02 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP14248599 1999-05-21
JP2006211156A JP4653704B2 (en) 1999-05-21 2006-08-02 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP30601299A Division JP3987251B2 (en) 1999-05-21 1999-10-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2006303543A JP2006303543A (en) 2006-11-02
JP4653704B2 true JP4653704B2 (en) 2011-03-16

Family

ID=37471380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006211156A Expired - Fee Related JP4653704B2 (en) 1999-05-21 2006-08-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4653704B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008198787A (en) * 2007-02-13 2008-08-28 Rohm Co Ltd GaN-BASED SEMICONDUCTOR DEVICE
MY186880A (en) 2017-02-14 2021-08-26 Nissan Motor Semiconductor device and manufacturing method of the same
EP3783640B1 (en) 2018-04-19 2023-03-01 Nissan Motor Co., Ltd. Semiconductor device and method of manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999056321A1 (en) * 1998-04-23 1999-11-04 Infineon Technologies Ag Lateral high-voltage sidewall transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS572574A (en) * 1980-06-06 1982-01-07 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field effect transistor
GB2089119A (en) * 1980-12-10 1982-06-16 Philips Electronic Associated High voltage semiconductor devices
EP0164095A3 (en) * 1984-06-08 1987-01-07 Eaton Corporation Vertical bidirectional stacked power fet
JP3173268B2 (en) * 1994-01-06 2001-06-04 富士電機株式会社 Semiconductor device having MIS field-effect transistor
JPH09266311A (en) * 1996-01-22 1997-10-07 Fuji Electric Co Ltd Semiconductor device and its manufacture
CN1156017C (en) * 1997-06-23 2004-06-30 小詹姆斯·艾伯特·库珀 Power semiconductor device in wide-band-gap semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999056321A1 (en) * 1998-04-23 1999-11-04 Infineon Technologies Ag Lateral high-voltage sidewall transistor

Also Published As

Publication number Publication date
JP2006303543A (en) 2006-11-02

Similar Documents

Publication Publication Date Title
US10461077B2 (en) Method of manufacturing a semiconductor device
JP6753951B2 (en) Semiconductor devices and power converters
JP3502371B2 (en) Semiconductor element
WO2017047286A1 (en) Semiconductor device
JP2002185015A (en) High breakdown voltage semiconductor device
JP2009055063A (en) Gate turnoff thyristor
WO2019239632A1 (en) Power semiconductor device and method of manufacturing same
JP4488935B2 (en) High voltage semiconductor device
US10593792B2 (en) Semiconductor device and method for manufacturing the same
US7470960B1 (en) High-voltage power semiconductor device with body regions of alternating conductivity and decreasing thickness
CN111512448B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
US11049942B2 (en) Power semiconductor device
WO2005091372A1 (en) Voltage-controlled semiconductor device
US10930775B2 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
JP4653704B2 (en) Semiconductor device
JP3987251B2 (en) Semiconductor device
JPH0730111A (en) Insulated-gate field-effect transistor
JP2017092364A (en) Semiconductor device and semiconductor device manufacturing method
JP4700148B2 (en) Voltage-driven bipolar semiconductor device
US20150187918A1 (en) Power semiconductor device
US20230139229A1 (en) Semiconductor device and power converter
JP2021028962A (en) Silicon carbide semiconductor device
JP2022136715A (en) insulated gate semiconductor device
JP2020096086A (en) Power semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060802

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100113

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100928

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101119

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101214

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101217

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131224

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees