JP4599421B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010410 layer Substances 0.000 claims description 81
- 238000003860 storage Methods 0.000 claims description 65
- 239000000758 substrate Substances 0.000 claims description 44
- 239000011229 interlayer Substances 0.000 claims description 23
- 238000012545 processing Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 229910052814 silicon oxide Inorganic materials 0.000 description 26
- 230000002093 peripheral effect Effects 0.000 description 25
- 238000005530 etching Methods 0.000 description 23
- 238000002955 isolation Methods 0.000 description 19
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 10
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 9
- 230000005684 electric field Effects 0.000 description 9
- 238000001459 lithography Methods 0.000 description 9
- 239000000243 solution Substances 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 238000012805 post-processing Methods 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910003855 HfAlO Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- -1 hafnium aluminate Chemical class 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
Description
図1A及びBは、第1実施例の半導体装置101の側方断面図である。当該半導体装置101はここでは、チャージトラップ型の不揮発性メモリ、詳細には、MONOS型のフラッシュメモリである。図1A及びBには、当該半導体装置101を構成するセルトランジスタの断面が示されている。
図15A及びBは、第2実施例の半導体装置101の側方断面図である。図1Bでは、第1のゲート絶縁膜121及び電荷蓄積絶縁膜122が素子分離層145間に形成されている。これに対し、図15Bでは、第1のゲート絶縁膜121及び電荷蓄積絶縁膜122が素子分離層145上に形成されている。
図16A及びBは、第3実施例の半導体装置101の側方断面図である。図16A及び図16Bではそれぞれ、第2のゲート絶縁膜123の上面における、側面S2間の幅W2が、ゲート電極124の下面における、側面S3間の幅W3よりも狭くなっている。第2のゲート絶縁膜123及びゲート電極124の構造は、図16Aや図16Bに示すような構造でも構わない。即ち、W2<W3の関係は、少なくとも第2のゲート絶縁膜123の上面とゲート電極124の下面との間で成立していれば十分である。図3A及びBで説明したような効果は、このような構造でも発揮される。
111 基板
121 第1のゲート絶縁膜
122 電荷蓄積絶縁膜
123 第2のゲート絶縁膜
124 ゲート電極
131 層間絶縁膜
141 Nウェル
142 Pウェル
143 ソース拡散層
144 ドレイン拡散層
145 素子分離層
201 犠牲酸化膜
211 シリコン酸化膜
212 シリコン窒化膜
213 マスク層
221 マスク層
Claims (5)
- 基板と、
前記基板上に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に形成された電荷蓄積絶縁膜と、
前記電荷蓄積絶縁膜上に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成されたゲート電極と、
前記電荷蓄積絶縁膜、前記第2のゲート絶縁膜、及び前記ゲート電極の側面を覆う層間絶縁膜とを備え、
前記第2のゲート絶縁膜の側面間の幅は、前記電荷蓄積絶縁膜の側面間の幅、及び前記ゲート電極の側面間の幅よりも狭く、前記第2のゲート絶縁膜の側面は、前記電荷蓄積絶縁膜の側面、及び前記ゲート電極の側面に比べ後退しており、
前記第2のゲート絶縁膜の比誘電率は、前記層間絶縁膜の比誘電率よりも大きいことを特徴とする半導体装置。 - 前記第2のゲート絶縁膜の側面は、前記ゲート電極の側面に比べ、一側面あたり、前記ゲート電極の側面間の幅の5%から25%分だけ後退していることを特徴とする請求項1に記載の半導体装置。
- 前記基板上に形成された複数のトランジスタを備え、
前記第1のゲート絶縁膜は、前記電荷蓄積絶縁膜、前記第2のゲート絶縁膜、及び前記ゲート電極の前記側面の方向に隣接する前記トランジスタ間に連続して形成されていることを特徴とする請求項1又は2に記載の半導体装置。 - 基板と、
前記基板上に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に形成された電荷蓄積絶縁膜と、
前記電荷蓄積絶縁膜上に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成されたゲート電極と、
前記電荷蓄積絶縁膜、前記第2のゲート絶縁膜、及び前記ゲート電極の側面を覆う層間絶縁膜とを備え、
前記第2のゲート絶縁膜の上面における側面間の幅は、前記電荷蓄積絶縁膜の側面間の幅、及び前記ゲート電極の下面における側面間の幅よりも狭く、前記第2のゲート絶縁膜の上面における側面は、前記電荷蓄積絶縁膜の側面、及び前記ゲート電極の下面における側面に比べ後退しており、
前記第2のゲート絶縁膜の比誘電率は、前記層間絶縁膜の比誘電率よりも大きいことを特徴とする半導体装置。 - 基板上に、第1のゲート絶縁膜と電荷蓄積絶縁膜と第2のゲート絶縁膜とゲート電極層とを順に堆積し、
前記ゲート電極層と前記第2のゲート絶縁膜と前記電荷蓄積絶縁膜とを加工して、前記ゲート電極層からゲート電極を形成し、
前記第2のゲート絶縁膜の側面を、前記電荷蓄積絶縁膜の側面及び前記ゲート電極の側面に対し後退させて、前記第2のゲート絶縁膜の側面間の幅を、前記電荷蓄積絶縁膜の側面間の幅及び前記ゲート電極の側面間の幅よりも狭くし、
前記第2のゲート絶縁膜よりも比誘電率の小さい層間絶縁膜を、前記電荷蓄積絶縁膜、前記第2のゲート絶縁膜、及び前記ゲート電極の側面を覆うように形成することを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2008052167A JP4599421B2 (ja) | 2008-03-03 | 2008-03-03 | 半導体装置及びその製造方法 |
US12/396,820 US20090218615A1 (en) | 2008-03-03 | 2009-03-03 | Semiconductor device and method of manufacturing the same |
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JP2008052167A JP4599421B2 (ja) | 2008-03-03 | 2008-03-03 | 半導体装置及びその製造方法 |
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JP2009212216A JP2009212216A (ja) | 2009-09-17 |
JP4599421B2 true JP4599421B2 (ja) | 2010-12-15 |
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CN103456390B (zh) | 2013-02-05 | 2016-04-27 | 南昌欧菲光科技有限公司 | 导电膜及其制造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06318709A (ja) * | 1993-03-12 | 1994-11-15 | Citizen Watch Co Ltd | 半導体不揮発性記憶装置およびその製造方法 |
JP2003258128A (ja) * | 2002-02-27 | 2003-09-12 | Nec Electronics Corp | 不揮発性半導体記憶装置およびその製造方法ならびにその動作方法 |
JP2004165553A (ja) * | 2002-11-15 | 2004-06-10 | Toshiba Corp | 半導体記憶装置 |
JP2005064178A (ja) * | 2003-08-11 | 2005-03-10 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2005191593A (ja) * | 2005-02-21 | 2005-07-14 | Seiko Epson Corp | 不揮発性記憶装置 |
JP2006121094A (ja) * | 2004-10-21 | 2006-05-11 | Samsung Electronics Co Ltd | 電荷トラップ膜を有する不揮発性メモリセル構造物及びその製造方法 |
JP2008141153A (ja) * | 2006-12-04 | 2008-06-19 | Hynix Semiconductor Inc | 半導体メモリ素子およびその製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US7001807B1 (en) * | 2001-12-20 | 2006-02-21 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
JP4040534B2 (ja) * | 2003-06-04 | 2008-01-30 | 株式会社東芝 | 半導体記憶装置 |
KR20050116976A (ko) * | 2004-06-09 | 2005-12-14 | 동부아남반도체 주식회사 | 플래시 메모리 소자 및 이의 프로그래밍/소거 방법 |
KR100823713B1 (ko) * | 2006-09-08 | 2008-04-21 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 이의 제조 방법 |
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2008
- 2008-03-03 JP JP2008052167A patent/JP4599421B2/ja not_active Expired - Fee Related
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2009
- 2009-03-03 US US12/396,820 patent/US20090218615A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06318709A (ja) * | 1993-03-12 | 1994-11-15 | Citizen Watch Co Ltd | 半導体不揮発性記憶装置およびその製造方法 |
JP2003258128A (ja) * | 2002-02-27 | 2003-09-12 | Nec Electronics Corp | 不揮発性半導体記憶装置およびその製造方法ならびにその動作方法 |
JP2004165553A (ja) * | 2002-11-15 | 2004-06-10 | Toshiba Corp | 半導体記憶装置 |
JP2005064178A (ja) * | 2003-08-11 | 2005-03-10 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2006121094A (ja) * | 2004-10-21 | 2006-05-11 | Samsung Electronics Co Ltd | 電荷トラップ膜を有する不揮発性メモリセル構造物及びその製造方法 |
JP2005191593A (ja) * | 2005-02-21 | 2005-07-14 | Seiko Epson Corp | 不揮発性記憶装置 |
JP2008141153A (ja) * | 2006-12-04 | 2008-06-19 | Hynix Semiconductor Inc | 半導体メモリ素子およびその製造方法 |
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US20090218615A1 (en) | 2009-09-03 |
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