JP4595069B2 - Quasi-planar waveguide type Josephson junction array structure, digital-analog converter using the same, programmable array for Josephson voltage standard, chip for Josephson voltage standard, Josephson voltage generator - Google Patents

Quasi-planar waveguide type Josephson junction array structure, digital-analog converter using the same, programmable array for Josephson voltage standard, chip for Josephson voltage standard, Josephson voltage generator Download PDF

Info

Publication number
JP4595069B2
JP4595069B2 JP2005168938A JP2005168938A JP4595069B2 JP 4595069 B2 JP4595069 B2 JP 4595069B2 JP 2005168938 A JP2005168938 A JP 2005168938A JP 2005168938 A JP2005168938 A JP 2005168938A JP 4595069 B2 JP4595069 B2 JP 4595069B2
Authority
JP
Japan
Prior art keywords
josephson
microwave
voltage standard
josephson junction
junction array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005168938A
Other languages
Japanese (ja)
Other versions
JP2006344761A (en
Inventor
弘毅 山森
彰 東海林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute of Advanced Industrial Science and Technology AIST filed Critical National Institute of Advanced Industrial Science and Technology AIST
Priority to JP2005168938A priority Critical patent/JP4595069B2/en
Publication of JP2006344761A publication Critical patent/JP2006344761A/en
Application granted granted Critical
Publication of JP4595069B2 publication Critical patent/JP4595069B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Analogue/Digital Conversion (AREA)

Description

本願発明は、バイアス電流とマイクロ波の印加により一定電圧を発生する準平面導波路型ジョセフソン接合の多数個を直列接続したジョセフソン接合アレーと、それにより構成される電圧標準装置等に関する。   The present invention relates to a Josephson junction array in which a large number of quasi-planar waveguide type Josephson junctions that generate a constant voltage by applying a bias current and a microwave are connected in series, a voltage standard device constituted by the Josephson junction array, and the like.

ジョセフソン電圧標準装置は、周波数を正確に電圧に変換できる交流ジョセフソン効果という物理法則に基づいている。
ジョセフソン接合装置は一般に電圧−周波数変換器とみなすことができる。直流電圧Ｖを接合に印加すると、ジョセフソン電流は周波数ｆ＝ＫＪ Ｖ（ＫＪ ＝４８３５９７．９ＧＨｚ／Ｖ；ジョセフソン定数）で振動する。しかしながら、一つの接合からの電磁波放射出力は比較的小さい。高周波結合回路（シャント抵抗等）により、各接合の位相を同相にすることができるので、Ｎ２ に比例するような出力を取り出すことができる。ここでＮは積層構造中の接合の数である。これとは逆に、周波数を変えることにより電圧を出力することができる。
また、ジョセフソン接合を任意数直列接続してジョセフソンＤ／Ａ変換器を構成することもできる。例えば、デジタル入力バイアス電流（二進数０００．．．００１０１０）が印加されると、アナログ出力電圧Ｖａ−ｏｕｔ （０＋２×Ｖ０ ＋０＋８×Ｖ０ ＋０＝１０Ｖ０ ）を得ることができる。なお、各ビットに対応する素子は特定の接合数からなる接合部のスタックである。
ところで、シリコンなどを材料とするチップ上のジョセフソン接合にマイクロ波を供給するためにはマイクロ波伝送線路が用いられる。マイクロ波伝送線路としては、準平面型導波路（Ｃｏｐｌａｎａｒ Ｗａｖｅｇｕｉｄｅ： ＣＰＷ） が利用されてきた（下記非特許文献１参照）。 The Josephson voltage standard is based on the physical law of AC Josephson effect that can accurately convert frequency to voltage.
Josephson junction devices can generally be considered voltage-frequency converters. When a DC voltage V is applied to the junction, the Josephson current oscillates at a frequency f = K J V (K J = 483597.9 GHz / V; Josephson constant). However, the electromagnetic radiation output from one junction is relatively small. Since the phase of each junction can be made in-phase by a high-frequency coupling circuit (such as a shunt resistor), an output proportional to N 2 can be taken out. Here, N is the number of junctions in the laminated structure. On the contrary, a voltage can be output by changing the frequency.
Further, a Josephson D / A converter can be configured by connecting an arbitrary number of Josephson junctions in series. For example, when a digital input bias current (binary number 000... 001010) is applied, an analog output voltage V a-out (0 + 2 × V 0 + 0 + 8 × V 0 + 0 = 10V 0 ) can be obtained. The element corresponding to each bit is a stack of junctions having a specific number of junctions.
By the way, a microwave transmission line is used to supply a microwave to a Josephson junction on a chip made of silicon or the like. A quasi-planar waveguide (CPW) has been used as a microwave transmission line (see Non-Patent Document 1 below).

図（５）は従来の準平面型導波路の断面図である。
図（５）には、誘電体基板１の一面に信号導体配線２と接地導体（外部導体）３が設けられた配線構造である準平面型導波路が示されている。信号配線が接地導体にはさまれた構造になっており、誘電体の一面のみを使って信号伝送ができるため、回路の特性評価や他の回路との接続が容易である。 FIG. 5 is a cross-sectional view of a conventional quasi-planar waveguide.
FIG. 5 shows a quasi-planar waveguide having a wiring structure in which the signal conductor wiring 2 and the ground conductor (external conductor) 3 are provided on one surface of the dielectric substrate 1. Since the signal wiring has a structure sandwiched between ground conductors and signal transmission is possible using only one surface of the dielectric, circuit characteristics evaluation and connection with other circuits are easy.

図（６）は従来のジョセフソン接合アレーの平面図である。
図（６）の電圧標準で用いられるジョセフソン接合アレーは、超伝導体の下部電極４と常伝導体の中間層５と超伝導体の上部電極６から構成されるジョセフソン接合を、下部電極と兼用した下部配線４と上部配線７で多数個直列に接続したものである。 FIG. 6 is a plan view of a conventional Josephson junction array.
The Josephson junction array used in the voltage standard of FIG. 6 is a Josephson junction composed of a superconductor lower electrode 4, a normal conductor intermediate layer 5 and a superconductor upper electrode 6. A plurality of lower wirings 4 and upper wirings 7 are also connected in series.

図（６）の平面図および図（７）の断面図に示すように、すべての接合に均一にマイクロ波を印加するために、ジョセフソン接合アレーも接合の両側に接地導体３を配置し、準平面型の伝送線路を形成したものも知られている（非特許文献２参照）。   As shown in the plan view of FIG. (6) and the cross-sectional view of FIG. (7), in order to uniformly apply microwaves to all the junctions, the Josephson junction array is also provided with ground conductors 3 on both sides of the junction, A device in which a quasi-planar transmission line is formed is also known (see Non-Patent Document 2).

ジョセフソン接合で発生した熱によって下部電極４または上部電極６の超伝導性が失われるのを防ぐ目的で、図（８）に示すように幅を大きくした下部電極９によってジョセフソン接合で発生した熱を基板１に逃がす改良がされている。（非特許文献３参照）
Ｃ．Ｐ．Ｗｅｎ： ＩＥＥＥ Ｔｒａｎｓ ｏｎ Ｍｉｃｒｏｗａｅ Ｔｈｅｏｒｙ ａｎｄ Ｔｅｃｈｎｉｑｕｅｓ ＭＩＴ−１７ （２） Ｄｅｃｅｍｂｅｒ １９６９， ｐｐ．１０８７−１０９０ 「Ｃｏｐｌａｎａｒ Ｗａｖｅｇｕｉｄｅ： Ａ Ｓｕｒｆａｃｅ Ｓｔｒｉｐ Ｔｒａｎｓｍｉｓｓｉｏｎ Ｌｉｎｅ Ｓｕｉｔａｂｌｅ ｆｏｒ Ｎｏｎｒｅｃｉｐｒｏｃａｌ Ｇｙｒｏｍａｇｎｅｔｉｃ Ｄｅｖｉｃｅ Ａｐｐｌｉｃａｔｉｏｎｓ」 Ｓ．Ｐ．Ｂｅｎｚ： Ａｐｐｌ． Ｐｈｙｓ． Ｌｅｔｔ． ６７ （１８）， ３０ Ｏｃｔｏｂｅｒ １９９５， ｐｐ．２７１４−２７１６「Ｓｕｐｅｒｃｏｎｄｕｃｔｏｒ −ｎｏｒｍａｌ −ｓｕｐｅｒｃｏｎｄｕｃｔｏｒ ｊｕｎｃｔｉｏｎｓ ｆｏｒ ｐｒｏｇｒａｍｍａｂｌｅ ｖｏｌｔａｇｅ ｓｔａｎｄａｒｄｓ」 Ｙ．Ｃｈｏｎｇ， Ｐ．Ｄ．Ｄｒｅｓｓｅｌｈａｕｓ， ａｎｄ Ｓ．Ｐ．Ｂｅｎｚ： Ａｐｐｌ． Ｐｈｙｓ． Ｌｅｔｔ． ８３ （９）， １ Ｓｅｐｔｅｍｂｅｒ ２００３， ｐｐ．１７９４−１７９６ 「Ｔｈｅｒｍａｌ ｔｒａｎｓｐｏｒｔ ｉｎ ｓｔａｃｋｅｄ ｓｕｐｅｒｃｏｎｄｕｃｔｏｒ−ｎｏｒｍａｌ ｍｅｔａｌ−ｓｕｐｅｒｃｏｎｄｕｃｔｏｒ Ｊｏｓｅｐｈｓｏｎ ｊｕｎｃｔｉｏｎｓ」 小暮裕明： 電磁界シミュレータで学ぶ高周波の世界， ＣＱ出版社， １９９９年， 第１章， ２０頁 Ｋ．Ｃ．Ｇｕｐｔａ： “Ｍｉｃｒｏｓｔｒｉｐ Ｌｉｎｅｓ ａｎｄ Ｓｌｏｔｌｉｎｅｓ”， （Ａｒｔｅｃｈ Ｈｏｕｓｅ， Ｂｏｓｔｏｎ／Ｌｏｎｄｏｎ， １９９６） 第７章， ３７６頁 Ｃ．Ａ．Ｈａｍｉｌｔｏｎ， Ｃ．Ｊ．Ｂｕｒｒｏｕｇｈｓ， Ｒ．Ｌ．Ｋａｕｔｚ： ＩＥＥＥ Ｔｒａｎｓ ｏｎ Ａｐｐｌ． Ｓｕｐｅｒｃｏｎｄ．， ４４ （２） Ａｐｒｉｌ １９９５， ｐｐ．２２３−２２５ 「Ｊｏｓｅｐｈｓｏｎ Ｄ／Ａ Ｃｏｎｖｅｒｔｅｒ ｗｉｔｈ Ｆｕｎｄａｍｅｎｔａｌ Ａｃｃｕｒａｃｙ」 In order to prevent the superconductivity of the lower electrode 4 or the upper electrode 6 from being lost due to the heat generated in the Josephson junction, the lower electrode 9 having a larger width as shown in FIG. Improvements have been made to release heat to the substrate 1. (See Non-Patent Document 3)
C. P. Wen: IEEE Trans on Microway Theory and Techniques MIT-17 (2) December 1969, pp. 15-27. 1087-1090 “Coplanar Waveguide: A Surface Strip Transmission Line Sustainable for Non-reciprocal Gyromagnetic Devices Applications” S. P. Benz: Appl. Phys. Lett. 67 (18), 30 October 1995, pp. 2714-2716 "Superconductor -normal -superconductor junctions for programmable voltage standards" Y. Chong, P.A. D. Dresselhaus, and S.M. P. Benz: Appl. Phys. Lett. 83 (9), 1 September 2003, pp. 1794-1796 "Thermal transport in stacked superconductor-normal metal-superconductor Josephson junctions" Hiroaki Kogure: High-frequency world to learn with an electromagnetic simulator, CQ Publisher, 1999, Chapter 1, page 20 K. C. Gupta: “Microstrip Lines and Slotlines”, (Artech House, Boston / London, 1996) Chapter 7, page 376 C. A. Hamilton, C.I. J. et al. Burroughs, R.A. L. Kautz: IEEE Trans on Appl. Supercond. , 44 (2) April 1995, pp. 223-225 “Josephson D / A Converter with Fundamental Accuracy”

超伝導薄膜の表面インピーダンスＺｓは下記数１の式で与えられる。（非特許文献４参照）

Figure 0004595069

ここで、ωは角周波数、μ０は真空中の透磁率、λはロンドン侵入長、σは複素導電率、ｄは膜厚である。従って、超伝導材料を電極および配線として用いる場合、膜厚ｄがロンドン侵入長λより小さいと表面インピーダンスが増加し減衰が急激に大きくなる。ジョセフソン接合アレーの配線で減衰があると、大きなマイクロ波を入力しなければならないという問題だけでなく、電圧標準用ジョセフソン接合アレーにおいて接合に印加されるマイクロ波電力がすべての接合において均一である必要があるにもかかわらず、減衰によりマイクロ波の電力にばらつきが生じ動作マージンを低下させるという深刻な問題も発生する。したがって、下部電極兼下部配線９及び上部配線７はロンドン侵入長より十分厚くなければならない。しかしここで問題となるのは、超伝導材料としてチッ化ニオブのようなロンドン侵入長が長い材料を用いた場合、膜厚を非常に厚くしなければならいことである。チッ化ニオブは段差が大きいと結晶の粒界が発生し流せる電流が急激に減少してしまうという問題点がある。図（７）に示すように下部電極４の端（エッジ）の上を上部配線７が横切ると、上部配線７には下部電極４の膜厚に相当する段差が発生し、上部配線７に流せる電流が著しく減少してしまう。したがって、上部配線７の臨界電流値が著しく減少してしまうという問題があり、下部電極４を厚くするには限界がある。
本発明の目的は、上記問題点に鑑み、表面インピーダンスの増加によるマイクロ波の減衰を防止するようにした準平面導波路型ジョセフソン接合アレー構造体、それを用いたデジタル−アナログ変換器、プログラマブルジョセフソン電圧標準用接合アレー、ジョセフソン電圧標準用チップ、ジョセフソン電圧発生装置を提供することにある。 The surface impedance Z s of the superconducting thin film is given by the following equation (1). (See Non-Patent Document 4)
Figure 0004595069
Here, ω is the angular frequency, μ 0 is the magnetic permeability in vacuum, λ is the London penetration length, σ is the complex conductivity, and d is the film thickness. Therefore, when using a superconducting material as an electrode and wiring, if the film thickness d is smaller than the London penetration length λ, the surface impedance increases and the attenuation increases rapidly. Not only does a large microwave input have to be attenuated in the Josephson junction array wiring, but the microwave power applied to the junction in the voltage standard Josephson junction array is uniform across all junctions. In spite of the necessity, there is a serious problem that the microwave power varies due to attenuation and the operation margin is lowered. Therefore, the lower electrode / lower wiring 9 and the upper wiring 7 must be sufficiently thicker than the London penetration length. However, the problem here is that when a material having a long London penetration length such as niobium nitride is used as a superconductive material, the film thickness must be very large. Niobium nitride has a problem in that when the step is large, crystal grain boundaries are generated and the current that can be flowed rapidly decreases. As shown in FIG. 7, when the upper wiring 7 crosses the end (edge) of the lower electrode 4, a step corresponding to the film thickness of the lower electrode 4 is generated in the upper wiring 7 and can flow to the upper wiring 7. The current is significantly reduced. Therefore, there is a problem that the critical current value of the upper wiring 7 is remarkably reduced, and there is a limit to making the lower electrode 4 thick.
In view of the above problems, an object of the present invention is to provide a quasi-planar waveguide type Josephson junction array structure that prevents microwave attenuation due to an increase in surface impedance, a digital-analog converter using the same, and a programmable It is an object to provide a junction array for Josephson voltage standard, a chip for Josephson voltage standard, and a Josephson voltage generator.

線路に流れる電流の分布は一様ではなく、線路の両縁に沿ったわずかな部分に強い電流が流れている。これはエッジの特異性あるいはエッジの偏りとも呼ばれている（非特許文献５参照）。
図（１）は本発明の実施例の平面図である。 図（１）に示すような準平面導波路型ジョセフソン接合の場合も、電界は接地導体３と下部電極９の隙間に集中する（非特許文献６参照）ので、マイクロ波電流は接地導体３と下部電極９のギャップの近傍を集中的に流れる。従って、ギャップ近傍の厚さ（図（１）の１０の部分）を厚くすれば、下部電極９全体の膜厚を大きくしなくても同様の効果が得られ、表面インピーダンスの増加によるマイクロ波の減衰を防止することが可能になる。
具体的には、
（１）ジョセフソン接合アレー構造体は、
準平面導波路型ジョセフソン接合アレー構造体は、基板上に複数個の下部電極を相互に離間した状態で直列に配置し、
前記下部電極の上に２個の中間層を相互に離間した状態で前記下部電極の配置方向に沿って直列に配置し、前記直列方向に隣り合わせの２個の前記中間層上にそれらを連結する上部電極を配置したジョセフソン接合を複数個備え、
前記下部電極上に、前記中間層の両側に離間してマイクロ波用配線を設け、前記マイクロ波用配線の外側に接地導体を設けたことを特徴とする。
（２）上記（１）記載のジョセフソン接合アレー構造体において、
上記基板は、誘電体又は半導体で形成されていることを特徴とする。
（３）上記（１）記載のジョセフソン接合アレー構造体において、
上記外部導体は、超伝導体で形成されていることを特徴とする。
（４）上記（１）記載のジョセフソン接合アレー構造体において、
上記絶縁膜は、誘電体で形成されていることを特徴とする。
（５）デジタル−アナログ変換器は、
マイクロ波入力端子とマイクロ波終端抵抗との間に上記（１）乃至（４）のいずれか１項記載の準平面導波路型ジョセフソン接合を任意数の接合ずつ直列に配置することを特徴とする。
（６）プログラマブルジョセフソン電圧標準用接合アレーは、
上記（５）記載のデジタル−アナログ変換器を用いて構成したことを特徴とする。
（７）ジョセフソン電圧標準用チップは、
上記（６）記載のプログラマブル電圧標準用接合アレーを基板上に設けたことを特徴とする。
（８）ジョセフソン電圧発生装置は、
上記（７）記載のプログラマブル電圧標準用チップ、チップ冷却用の冷凍機、マイクロ波源、バイアス電流源を備えたことを特徴とする。 The distribution of the current flowing in the line is not uniform, and a strong current flows in a small portion along both edges of the line. This is also called edge peculiarity or edge bias (see Non-Patent Document 5).
FIG. 1 is a plan view of an embodiment of the present invention. Also in the case of the quasi-planar waveguide type Josephson junction as shown in FIG. 1A, the electric field is concentrated in the gap between the ground conductor 3 and the lower electrode 9 (see Non-Patent Document 6). And flows in the vicinity of the gap between the lower electrode 9 in a concentrated manner. Therefore, if the thickness in the vicinity of the gap (10 portion in FIG. 1) is increased, the same effect can be obtained without increasing the entire thickness of the lower electrode 9, and the microwaves due to the increase in surface impedance can be obtained. It becomes possible to prevent attenuation.
In particular,
(1) Josephson junction array structure is
The quasi-planar waveguide type Josephson junction array structure has a plurality of lower electrodes arranged in series in a state of being separated from each other on a substrate,
Two intermediate layers are arranged on the lower electrode in series along the arrangement direction of the lower electrode in a state of being separated from each other, and are connected to the two intermediate layers adjacent to each other in the series direction. It has a number of Josephson junctions with an upper electrode.
A microwave wiring is provided on the lower electrode so as to be separated from both sides of the intermediate layer, and a ground conductor is provided outside the microwave wiring.
(2) In the Josephson junction array structure according to (1) above,
The substrate is formed of a dielectric or a semiconductor.
(3) In the Josephson junction array structure according to (1) above,
The outer conductor is made of a superconductor.
(4) In the Josephson junction array structure according to (1) above,
The insulating film is formed of a dielectric material.
(5) The digital-analog converter
The quasi-planar waveguide type Josephson junction according to any one of the above (1) to (4) is arranged in series between any number of junctions between a microwave input terminal and a microwave termination resistor. To do.
(6) The programmable Josephson voltage standard junction array is
The digital-analog converter described in the above (5) is used.
(7) Josephson voltage standard chip is
The programmable voltage standard junction array described in (6) above is provided on a substrate.
(8) The Josephson voltage generator is
A programmable voltage standard chip described in (7) above, a refrigerator for cooling the chip, a microwave source, and a bias current source are provided.

図（１）に示すように準平面導波路型ジョセフソン接合アレーの下部電極兼下部配線９の上部でかつ接地導体３とのギャップの近傍にマイクロ波専用の配線１０を配置することによって、下部電極兼下部配線の全体の膜厚を大きくしたのと同様の効果が得られる。下部電極兼下部配線９そのものは薄くできるので、回路の段差の増加を抑制し上部配線７の臨界電流の減少といった問題も発生することなく、同時にマイクロ波の電極における減衰を防ぐことが出来る。マイクロ波の減衰を防ぐことは、大きなマイクロ波を供給する必要がなくなるとコストダウンになるだけでなく、ジョセフソン接合アレー内におけるマイクロ波の減衰が減少すれば、アレー内の接合のマイクロ波の均一性が向上し電圧標準回路の動作マージンを向上させることも可能になる。   As shown in FIG. 1 (1), the microwave-dedicated wiring 10 is disposed above the lower electrode / lower wiring 9 of the quasi-planar waveguide type Josephson junction array and in the vicinity of the gap with the ground conductor 3. The same effect can be obtained as when the entire film thickness of the electrode and lower wiring is increased. Since the lower electrode / lower wiring 9 itself can be made thin, it is possible to prevent the microwave electrode from being attenuated at the same time without causing an increase in the level difference of the circuit and the problem of a decrease in the critical current of the upper wiring 7. Preventing microwave attenuation not only reduces costs when it is no longer necessary to supply large microwaves, but also reduces the attenuation of microwaves in the Josephson junction array if the attenuation of the microwaves in the array decreases. The uniformity can be improved and the operation margin of the voltage standard circuit can be improved.

以下に、発明を実施するための最良の形態を示す。   The best mode for carrying out the invention will be described below.

本発明の準平面導波路型ジョセフソン接合アレー構造体は、すべての接合に均一にマイクロ波を印加するために、ジョセフソン接合アレーの接合部の両側に接地導体３を配置し、準平面型の伝送線路を形成する。
図（２）は本発明の実施例の平面図である。図（２）に示すように、基板１上に超伝導材料の下部電極兼下部配線９を形成し、下部電極兼下部配線９上に中間層（常伝導体）５と超伝導材料の上部電極６を順に成膜する。次に上部電極６と中間層５をパターンエッチングしてジョセフソン接合を形成する。それらの上に層間絶縁膜８を成膜し全体を覆う。ジョセフソン接合を直列に接続するために上部電極６の上部の層間絶縁膜８に穴をあけコンタクトホールを形成する。このとき同時に、マイクロ波用の配線を下部電極兼下部配線９に接続するために、下部電極兼下部配線９の上の層間絶縁膜８にも穴をあけてコンタクトホール１１を形成する。全体に上部配線となる超伝導膜を成膜しパタ―ニングおよびエッチングして上部配線７とマイクロ波用配線１０を同時に形成する。このように作製を容易にするために、上部配線７とマイクロ波用配線１０は同一レイヤーの導体膜を用いることができる。 In the quasi-planar waveguide type Josephson junction array structure of the present invention, the ground conductor 3 is disposed on both sides of the junction of the Josephson junction array in order to uniformly apply microwaves to all junctions. The transmission line is formed.
FIG. 2 is a plan view of the embodiment of the present invention. As shown in FIG. 2B, a lower electrode / lower wiring 9 made of superconducting material is formed on a substrate 1, and an intermediate layer (normal conductor) 5 and an upper electrode made of superconducting material are formed on the lower electrode / lower wiring 9. 6 are sequentially formed. Next, the upper electrode 6 and the intermediate layer 5 are pattern-etched to form a Josephson junction. An interlayer insulating film 8 is formed thereon to cover the whole. In order to connect the Josephson junctions in series, a hole is formed in the interlayer insulating film 8 above the upper electrode 6 to form a contact hole. At the same time, in order to connect the wiring for microwaves to the lower electrode / lower wiring 9, a hole is also formed in the interlayer insulating film 8 on the lower electrode / lower wiring 9 to form a contact hole 11. A superconducting film to be the upper wiring is formed on the entire surface, patterned and etched to form the upper wiring 7 and the microwave wiring 10 simultaneously. In order to facilitate the fabrication as described above, the upper wiring 7 and the microwave wiring 10 can use a conductor film of the same layer.

図（３）は、図（１）のＢＢ断面図に相等し、図（２）とは別の実施例である。
図（３）に示すように基板１の上に下部電極兼下部配線９と中間層（常伝導体）５と上部電極６を成膜する。上部電極６と中間層５をエッチングしてジョセフソン接合を形成する。このとき同時にダミーのジョセフソン接合１２を残しておく。このダミーのジョセフソン接合１２がマイクロ波の通り道となり下部配線９を厚くしたのと同様の効果が得られる。つぎに層間絶縁膜８を成膜し全体を覆う。ジョセフソン接合を直列に接続するために上部電極６の上部の層間絶縁膜８に穴をあけコンタクトホールを形成する。全体に上部配線となる超伝導膜を成膜しパタ―ニングおよびエッチングして上部配線７を形成する。マイクロ波用配線を形成するのにジョセフソン接合を流用しているため新たにプロセスの負担が増えることはなく容易に実現可能である。 FIG. (3) is equivalent to the BB cross-sectional view of FIG. (1) and is an embodiment different from FIG. (2).
As shown in FIG. 3, a lower electrode / lower wiring 9, an intermediate layer (normal conductor) 5, and an upper electrode 6 are formed on the substrate 1. The upper electrode 6 and the intermediate layer 5 are etched to form a Josephson junction. At the same time, the dummy Josephson junction 12 is left. This dummy Josephson junction 12 becomes a path for microwaves, and the same effect can be obtained as when the lower wiring 9 is made thicker. Next, an interlayer insulating film 8 is formed to cover the whole. In order to connect the Josephson junctions in series, a hole is formed in the interlayer insulating film 8 above the upper electrode 6 to form a contact hole. An upper wiring 7 is formed by forming a superconducting film as an upper wiring on the whole, patterning and etching. Since the Josephson junction is used to form the microwave wiring, it can be easily realized without increasing the burden on the process.

図（４）は本発明のプログラマブル電圧標準用デジタル−アナログ変換器の概念図である。
マイクロ波入力端子１３とマイクロ波終端抵抗１４との間に図（２）または図（３）のような準平面導波路を構成するジョセフソン接合をｍｋ個の接合ずつ直列に配置することで、最小桁の接合数がｍ個でビット数がｋビットのデジタル−アナログ変換器を構成する。このジョセフソン接合をｍｋ個の接合ずつ直列に配置したものをバイナリアレーという。（例えば、非特許文献６参照） 例えば、分解能が８ビットで、最小桁の接合数が１２８接合の場合、１２８個、２５６個、５１２個、１０２４個、２０４８個、４０９６個、８１９２個、１６３８４個のジョセフソン接合を含むアレーを直列に配置すればよい。
図（４）に示すように、マイクロ波をジョセフソン接合アレーの片方から供給し反対側の端に接続したマイクロ波終端抵抗１４まで伝送し終端させる。バイナリアレー１５に直流バイアス電流をオンオフすることで、バイナリアレー１５を介したデジタル入力をアナログ出力電圧１６に変換する。 FIG. 4 is a conceptual diagram of the digital-analog converter for programmable voltage standard according to the present invention.
By arranging m k junctions in series between the microwave input terminal 13 and the microwave termination resistor 14, the Josephson junctions constituting the quasi-planar waveguide as shown in FIG. A digital-analog converter having the minimum number of junctions of m and the number of bits of k bits is configured. This Josephson junction arranged in series with m k junctions is called a binary array. (For example, see Non-Patent Document 6) For example, when the resolution is 8 bits and the minimum number of junctions is 128 junctions, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 An array including one Josephson junction may be arranged in series.
As shown in FIG. 4 (4), the microwave is supplied from one side of the Josephson junction array and transmitted to the microwave termination resistor 14 connected to the opposite end to be terminated. By turning on / off the DC bias current in the binary array 15, the digital input via the binary array 15 is converted into the analog output voltage 16.

バイナリ配置のジョセフソン接合アレーでデジタル−アナログ変換器を構成し、Ｓｉウェハなどの基板上に作製しチップ状に切り出したものをジョセフソン電圧標準チップといい、チップを冷却するための冷凍機、マイクロ波源、バイアス電流源など電圧標準として動作させるのに必要な一式をジョセフソン電圧標準装置という。本願発明の準平面型ジョセフソン接合アレーを用い電圧標準装置を構成することによって、臨界温度の高いチッ化ニオブ薄膜を用いることが可能になるため動作温度を従来の４．２Ｋよりずっと大きな１０Ｋ程度にすることが可能になり、冷凍機が小型になる、消費電力が小さくなる、冷凍機のノイズが小さくなるなど、コストダウンと可搬性に関係する多くの利点がある。また、本願発明によりマイクロ波の減衰が小さくなるためマイクロ波源も小型にすることが可能になり、同様にコストダウンにもつながる。また、マイクロ波の減衰を防止するということはジョセフソン接合に供給されるマイクロ波を均一にすることにもなり、これは動作マージンを増加させ性能向上にもなる。   A binary-arranged Josephson junction array constitutes a digital-analog converter, which is fabricated on a substrate such as a Si wafer and cut into a chip, called a Josephson voltage standard chip, a refrigerator for cooling the chip, A set required to operate as a voltage standard such as a microwave source and a bias current source is called a Josephson voltage standard device. By constructing a voltage standard device using the quasi-planar Josephson junction array of the present invention, it becomes possible to use a niobium nitride thin film having a high critical temperature, so that the operating temperature is about 10K which is much higher than the conventional 4.2K. There are many advantages related to cost reduction and portability, such as miniaturization of the refrigerator, reduction of power consumption, and reduction of noise of the refrigerator. Further, since the attenuation of the microwave is reduced by the present invention, the microwave source can be made small, and the cost is similarly reduced. Further, preventing the attenuation of the microwave also makes the microwave supplied to the Josephson junction uniform, which increases the operation margin and improves the performance.

本発明の実施例の平面図である。It is a top view of the Example of this invention. 図１のＢＢ断面図である。It is BB sectional drawing of FIG. 図１のＢＢ断面図で図２とは別の実施例である。1 is a cross-sectional view taken along the line BB in FIG. プログラマブル電圧標準用デジタル−アナログ変換器の概念図である。It is a conceptual diagram of the digital-analog converter for programmable voltage standards. 従来の準平面型導波路の断面図である。It is sectional drawing of the conventional quasi-planar waveguide. 従来のジョセフソン接合アレーの平面図である。It is a top view of the conventional Josephson junction array. 図６のＡＡ断面図である。It is AA sectional drawing of FIG. 従来の改良型ジョセフソン接合アレーの断面図である。It is sectional drawing of the conventional improved type Josephson junction array.

符号の説明Explanation of symbols

１：基板
２：信号配線導体
３：接地導体
４：下部電極兼下部配線
５：中間層（常伝導体）
６：上部電極
７：上部配線
８：層間絶縁膜
９：幅を大きくした下部電極兼下部配線
１０：マイクロ波専用配線
１１：コンタクトホール
１２：マイクロ波用ダミー接合
１３：マイクロ波入力端子
１４：マイクロ波終端抵抗
１５：バイアス電流入力（デジタル入力）
１６：出力電圧
１７：ジョセフソン接合アレー
1: Substrate 2: Signal wiring conductor 3: Ground conductor 4: Lower electrode and lower wiring 5: Intermediate layer (normal conductor)
6: Upper electrode 7: Upper wiring 8: Interlayer insulating film 9: Widened lower electrode / lower wiring 10: Microwave dedicated wiring 11: Contact hole 12: Microwave dummy junction 13: Microwave input terminal 14: Micro Wave termination resistor 15: Bias current input (digital input)
16: Output voltage 17: Josephson junction array

Claims (8)

基板上に複数個の下部電極を相互に離間した状態で直列に配置し、
前記下部電極の上に２個の中間層を相互に離間した状態で前記下部電極の配置方向に沿って直列に配置し、前記直列方向に隣り合わせの２個の前記中間層上にそれらを連結する上部電極を配置したジョセフソン接合を複数個備え、
前記下部電極上に、前記中間層の両側に離間してマイクロ波用配線を設け、前記マイクロ波用配線の外側に接地導体を設けたことを特徴とする準平面導波路型ジョセフソン接合アレー構造体。 A plurality of lower electrodes are arranged in series on the substrate in a state of being separated from each other,
Two intermediate layers are arranged on the lower electrode in series along the arrangement direction of the lower electrode in a state of being separated from each other, and are connected to the two intermediate layers adjacent to each other in the series direction. It has a number of Josephson junctions with an upper electrode.
A quasi-planar waveguide type Josephson junction array structure in which microwave wiring is provided on both sides of the intermediate layer on the lower electrode, and a ground conductor is provided outside the microwave wiring. body. 上記基板は、誘電体又は半導体で形成されていることを特徴とする請求項１記載のジョセフソン接合アレー構造体。   The Josephson junction array structure according to claim 1, wherein the substrate is made of a dielectric or a semiconductor. 上記外部導体は、超伝導体で形成されていることを特徴とする請求項１記載のジョセフソン接合アレー構造体。   2. The Josephson junction array structure according to claim 1, wherein the outer conductor is made of a superconductor. 上記絶縁膜は、誘電体で形成されていることを特徴とする請求項１記載のジョセフソン接合アレー構造体。   The Josephson junction array structure according to claim 1, wherein the insulating film is formed of a dielectric. マイクロ波入力端子とマイクロ波終端抵抗との間に請求項１乃至４のいずれか１項記載の準平面導波路型ジョセフソン接合を任意数の接合ずつ直列に配置することを特徴とするデジタル−アナログ変換器。   5. A digital-characteristic circuit comprising: a quasi-planar waveguide type Josephson junction according to any one of claims 1 to 4 arranged in series between any number of junctions between a microwave input terminal and a microwave termination resistor. Analog converter. 請求項５記載のデジタル−アナログ変換器を用いて構成したことを特徴とするプログラマブルジョセフソン電圧標準用接合アレー。   6. A programmable Josephson voltage standard junction array comprising the digital-analog converter according to claim 5. 請求項６記載のプログラマブル電圧標準用接合アレーを基板上に設けたことを特徴とするジョセフソン電圧標準用チップ。   7. A Josephson voltage standard chip, comprising the programmable voltage standard junction array according to claim 6 provided on a substrate. 請求項７記載のプログラマブル電圧標準用チップ、チップ冷却用の冷凍機、マイクロ波源、バイアス電流源を備えたことを特徴とするジョセフソン電圧発生装置。
A Josephson voltage generator comprising the programmable voltage standard chip according to claim 7, a refrigerator for cooling the chip, a microwave source, and a bias current source.
JP2005168938A 2005-06-09 2005-06-09 Quasi-planar waveguide type Josephson junction array structure, digital-analog converter using the same, programmable array for Josephson voltage standard, chip for Josephson voltage standard, Josephson voltage generator Expired - Fee Related JP4595069B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005168938A JP4595069B2 (en) 2005-06-09 2005-06-09 Quasi-planar waveguide type Josephson junction array structure, digital-analog converter using the same, programmable array for Josephson voltage standard, chip for Josephson voltage standard, Josephson voltage generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005168938A JP4595069B2 (en) 2005-06-09 2005-06-09 Quasi-planar waveguide type Josephson junction array structure, digital-analog converter using the same, programmable array for Josephson voltage standard, chip for Josephson voltage standard, Josephson voltage generator

Publications (2)

Publication Number Publication Date
JP2006344761A JP2006344761A (en) 2006-12-21
JP4595069B2 true JP4595069B2 (en) 2010-12-08

Family

ID=37641497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005168938A Expired - Fee Related JP4595069B2 (en) 2005-06-09 2005-06-09 Quasi-planar waveguide type Josephson junction array structure, digital-analog converter using the same, programmable array for Josephson voltage standard, chip for Josephson voltage standard, Josephson voltage generator

Country Status (1)

Country Link
JP (1) JP4595069B2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170777A (en) * 2008-01-18 2009-07-30 National Institute Of Advanced Industrial & Technology Programmable josephson voltage standard apparatus
JP5414031B2 (en) * 2009-02-26 2014-02-12 独立行政法人産業技術総合研究所 AC voltage generating circuit using Josephson element and AC voltage standard circuit
JP5709168B2 (en) * 2011-08-01 2015-04-30 独立行政法人産業技術総合研究所 Josephson junction array structure, digital-analog converter using the structure, and superconducting voltage standard circuit
US10541659B2 (en) 2013-10-15 2020-01-21 Yale University Low-noise josephson junction-based directional amplifier
US9948254B2 (en) * 2014-02-21 2018-04-17 Yale University Wireless Josephson bifurcation amplifier
WO2016138406A1 (en) 2015-02-27 2016-09-01 Yale University Josephson junction-based circulators and related systems and methods
WO2016138408A1 (en) 2015-02-27 2016-09-01 Yale University Techniques for producing quantum amplifiers and related systems and methods
KR20180004132A (en) 2015-04-17 2018-01-10 예일 유니버시티 Wireless Josephson Parametric Converter
WO2017123940A1 (en) 2016-01-15 2017-07-20 Yale University Techniques for manipulation of two-quantum states and related systems and methods
US11737376B2 (en) 2017-12-11 2023-08-22 Yale University Superconducting nonlinear asymmetric inductive element and related systems and methods
CN108761156A (en) * 2018-08-24 2018-11-06 北京无线电计量测试研究所 A kind of solid-state refrigeration quantum voltage standard devices
CA3125986A1 (en) 2019-01-17 2020-07-23 Yale University Josephson nonlinear circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57112087A (en) * 1980-12-29 1982-07-12 Nagaoka Gijutsu Kagaku Daigaku Josephson voltage standard device
JP2003069096A (en) * 2001-08-27 2003-03-07 Japan Science & Technology Corp Continuous oscillation milliwave/sub-milliwave laser based on integrated circuit including intrinsic josephson element

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450728A (en) * 1987-08-20 1989-02-27 Gds Kk Feeding device utilizing superconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57112087A (en) * 1980-12-29 1982-07-12 Nagaoka Gijutsu Kagaku Daigaku Josephson voltage standard device
JP2003069096A (en) * 2001-08-27 2003-03-07 Japan Science & Technology Corp Continuous oscillation milliwave/sub-milliwave laser based on integrated circuit including intrinsic josephson element

Also Published As

Publication number Publication date
JP2006344761A (en) 2006-12-21

Similar Documents

Publication Publication Date Title
JP4595069B2 (en) Quasi-planar waveguide type Josephson junction array structure, digital-analog converter using the same, programmable array for Josephson voltage standard, chip for Josephson voltage standard, Josephson voltage generator
Hyltin Microstrip transmission on semiconductor dielectrics
US10897235B2 (en) Superconducting signal amplifier
US10305015B1 (en) Low loss architecture for superconducting qubit circuits
US10651361B2 (en) Bumped resonator structure
EP3443666B1 (en) Clock distribution network for a superconducting integrated circuit
Schulze et al. Design and fabrication of 10 V SINIS Josephson arrays for programmable voltage standards
US11006527B2 (en) Integrating Josephson amplifiers or Josephson mixers into printed circuit boards
US20230276719A1 (en) Quantum chip and fabrication method therefor
Findikoglu et al. Electrical characteristics of coplanar waveguide devices incorporating nonlinear dielectric thin films of SrTiO3 and Sr0. 5Ba0. 5TiO3
Ranzani et al. A 4: 1 transmission-line impedance transformer for broadband superconducting circuits
JP2005223468A (en) Quasi-planar microwave transmission line
US7774034B2 (en) Signal switching device
JP3820444B2 (en) Tuning circuits and superconducting integrated circuits using tunnel junction elements.
JP4604239B2 (en) Meander line type Josephson junction array
JPS6288381A (en) Superconducting switching apparatus
Khaira et al. Cryogenic analog microwave variable attenuator using RF-SQUIDs for quantum systems
JPH0529809A (en) Transmission line
JP3972003B2 (en) Signal switching device
JP2024502454A (en) Tunable Josephson Junction Oscillator
JP3284293B2 (en) Oxide superconducting Josephson junction array device and method of manufacturing the same
Klushin et al. Toward a programmable HTS Josephson voltage standard: recent results
JP4129522B2 (en) Constant voltage generator and method of manufacturing constant voltage generator
JP2880612B2 (en) Circuit board for mounting Josephson device
JP3213204B2 (en) High-frequency circuit device using superconductor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070314

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080129

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100824

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100825

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131001

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131001

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees