JP4593951B2 - マルチチップパッケージの製造方法 - Google Patents
マルチチップパッケージの製造方法 Download PDFInfo
- Publication number
- JP4593951B2 JP4593951B2 JP2004095148A JP2004095148A JP4593951B2 JP 4593951 B2 JP4593951 B2 JP 4593951B2 JP 2004095148 A JP2004095148 A JP 2004095148A JP 2004095148 A JP2004095148 A JP 2004095148A JP 4593951 B2 JP4593951 B2 JP 4593951B2
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- JP
- Japan
- Prior art keywords
- chip
- wiring
- package
- insulating film
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
Landscapes
- Wire Bonding (AREA)
Description
上面に端子を有する第1のチップ(下段チップ)と、該第1のチップ上に配設され下面に端子を有する第2のチップ(上段チップ)と、前記第1のチップと前記第2のチップとの間に配設され、表面が接着性を有する絶縁層で被覆された配線パターンとを備え、
前記第1及び第2のチップのそれぞれの端子と前記配線パターンとが、前記絶縁層を貫通する導体で接続されることを特徴としている。
前記絶縁層を両面接着テープとして形成し、前記第1のチップと前記第2のチップとを相互に押し付けることによって、双方のチップを固着させることを特徴としている。
11:下段チップ
12:上段チップ
13:チップ間配線
14:端子パッド
15:金属バンプ
16:端子パッド
17:金属バンプ
18:下部絶縁膜
19a:金属膜
19:配線層
20:上部絶縁膜
21:接続孔
22:外部接続孔
23:外部接続用金属バンプ
24:ダイパッド
25:リード
26:金属ワイヤ
28:配線用金属ワイヤ
41:下段チップ
42:上段チップ
43:端子
44:配線
45:金属バンプ
46:端子
47:配線
48:金属バンプ
49:金属ワイヤ
50:モールド樹脂
51:ダイパッド
52:リード
Claims (1)
- 上面に端子を有する第1のチップと、該第1のチップ上に配設され下面に端子を有する第2のチップと、を単一のパッケージに収容して成るマルチチップパッケージの製造方法において、
粘着性を有する第1の絶縁層上に所望の配線パターンを形成する第1のステップと、
前記配線パターンを粘着性を有する第2の絶縁層で被覆する第2のステップと、
前記第1及び第2の絶縁層の、前記第1及び第2のチップに応じた所定の位置に、前記第1及び第2のチップの端子上に形成される導体が収まるように接続孔を形成し、前記第1及び第2の絶縁層と前記配線パターンとから成るチップ間配線層を形成する第3のステップと、
基板上に前記第1のチップを取り付け、前記第1及び第2のチップの前記端子上に前記導体を形成する第4のステップと、
前記第1及び第2のチップの前記導体が前記接続孔に収まるように、前記第1チップ上に前記チップ間配線層を載せ、前記チップ間配線層上に前記第2チップを載せて、前記第1及び第2のチップとを接合させる第5のステップと、
前記第2の絶縁層の縁部で、かつ、前記第1のチップの前記導体が収まる前記接続孔の真上の位置に、外部接続孔を形成する第6のステップと、
前記外部接続孔内の前記配線パターン上に外部接続用導体を形成する第7のステップと、
前記外部接続用導体とリードとをワイヤボンディングする第8のステップと、
を有する、マルチチップパッケージの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004095148A JP4593951B2 (ja) | 2004-03-29 | 2004-03-29 | マルチチップパッケージの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004095148A JP4593951B2 (ja) | 2004-03-29 | 2004-03-29 | マルチチップパッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005285943A JP2005285943A (ja) | 2005-10-13 |
JP4593951B2 true JP4593951B2 (ja) | 2010-12-08 |
Family
ID=35184023
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004095148A Expired - Fee Related JP4593951B2 (ja) | 2004-03-29 | 2004-03-29 | マルチチップパッケージの製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP4593951B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5068133B2 (ja) * | 2007-10-17 | 2012-11-07 | 新光電気工業株式会社 | 半導体チップ積層構造体及び半導体装置 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0677285A (ja) * | 1992-08-28 | 1994-03-18 | Toshiba Corp | Ic素子の実装方法 |
JPH1056040A (ja) * | 1996-08-08 | 1998-02-24 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH11163252A (ja) * | 1997-12-02 | 1999-06-18 | Rohm Co Ltd | 半導体装置 |
JP2001102515A (ja) * | 1999-09-28 | 2001-04-13 | Nec Ic Microcomput Syst Ltd | 半導体装置 |
JP2002198395A (ja) * | 2000-12-26 | 2002-07-12 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2002343930A (ja) * | 2001-05-16 | 2002-11-29 | Fujitsu Ltd | 半導体装置 |
JP2003209206A (ja) * | 2002-01-16 | 2003-07-25 | Seiko Instruments Inc | 配線を内在する多層構造基材を有する実装構造体 |
JP2005251953A (ja) * | 2004-03-03 | 2005-09-15 | Nec Electronics Corp | 半導体装置 |
-
2004
- 2004-03-29 JP JP2004095148A patent/JP4593951B2/ja not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0677285A (ja) * | 1992-08-28 | 1994-03-18 | Toshiba Corp | Ic素子の実装方法 |
JPH1056040A (ja) * | 1996-08-08 | 1998-02-24 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH11163252A (ja) * | 1997-12-02 | 1999-06-18 | Rohm Co Ltd | 半導体装置 |
JP2001102515A (ja) * | 1999-09-28 | 2001-04-13 | Nec Ic Microcomput Syst Ltd | 半導体装置 |
JP2002198395A (ja) * | 2000-12-26 | 2002-07-12 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2002343930A (ja) * | 2001-05-16 | 2002-11-29 | Fujitsu Ltd | 半導体装置 |
JP2003209206A (ja) * | 2002-01-16 | 2003-07-25 | Seiko Instruments Inc | 配線を内在する多層構造基材を有する実装構造体 |
JP2005251953A (ja) * | 2004-03-03 | 2005-09-15 | Nec Electronics Corp | 半導体装置 |
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JP2005285943A (ja) | 2005-10-13 |
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