JP4587774B2 - 半導体デバイスを形成する方法 - Google Patents
半導体デバイスを形成する方法 Download PDFInfo
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- JP4587774B2 JP4587774B2 JP2004312244A JP2004312244A JP4587774B2 JP 4587774 B2 JP4587774 B2 JP 4587774B2 JP 2004312244 A JP2004312244 A JP 2004312244A JP 2004312244 A JP2004312244 A JP 2004312244A JP 4587774 B2 JP4587774 B2 JP 4587774B2
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- 238000000034 method Methods 0.000 title claims description 53
- 239000004065 semiconductor Substances 0.000 title description 11
- 239000000758 substrate Substances 0.000 claims description 115
- 125000006850 spacer group Chemical group 0.000 claims description 59
- 239000004020 conductor Substances 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 16
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000003870 refractory metal Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 239000011241 protective layer Substances 0.000 description 16
- 229910021332 silicide Inorganic materials 0.000 description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
Claims (6)
- 基板の表面に第1のゲート・スタックを有する基板を用意するステップと、
前記基板の前記表面に第2のゲート・スタックを設けるステップと、
前記第1のゲート・スタックおよび前記第2のゲート・スタックの側壁に沿って第1のスペーサを形成するステップと、
前記第1及び第2のゲート・スタック上にエッチ耐性ライナを形成するステップと、
前記第1及び第2のゲート・スタックの側壁に沿って前記ライナ上に第2のスペーサを形成するステップと、
前記スペーサによって覆われていない前記基板および第1及び第2のゲート・スタックの領域からエッチングによって前記ライナを除去し、前記第2のスペーサによって覆われている前記基板および第1及び第2のゲート・スタックの領域に前記ライナを残すステップと、
前記ライナによって覆われていない前記基板および第1及び第2のゲート・スタックのうちの一方のゲート・スタックの領域のみに、事前清浄化プロセスを実行し、その後高融点金属の層を付着させ、次にアニールすることによって、導電材料を形成するステップと
をこの順序で実行するステップを含む、半導体デバイスを形成する方法。 - 前記第2のスペーサによって覆われていない前記基板およびゲート・スタックの領域から前記ライナを除去し、前記第2のスペーサによって覆われている前記基板およびゲート・スタックの領域に前記ライナを残すステップの後に、
前記導電材料を形成する前に前記導電材料を形成しないゲート・スタックを覆う前記基板の前記表面に絶縁層を形成するステップ
をさらに含む請求項1に記載の方法。 - 前記一方のゲート・スタックがトランジスタ・ゲート・スタックを備え、他方のゲート・スタックが抵抗スタックを含む請求項1に記載の方法。
- 前記ライナがAl2O3、HfO2、およびTa2O3からなるグループから選択される材料を含む請求項1に記載の方法。
- 前記ライナがSiCを含む請求項1に記載の方法。
- 前記ライナが7〜150の範囲の誘電率を有する材料を含む請求項1に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/713,227 US7064027B2 (en) | 2003-11-13 | 2003-11-13 | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005150713A JP2005150713A (ja) | 2005-06-09 |
JP4587774B2 true JP4587774B2 (ja) | 2010-11-24 |
Family
ID=34573664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004312244A Expired - Fee Related JP4587774B2 (ja) | 2003-11-13 | 2004-10-27 | 半導体デバイスを形成する方法 |
Country Status (4)
Country | Link |
---|---|
US (3) | US7064027B2 (ja) |
JP (1) | JP4587774B2 (ja) |
KR (1) | KR100562234B1 (ja) |
CN (1) | CN100452302C (ja) |
Families Citing this family (19)
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US7064027B2 (en) * | 2003-11-13 | 2006-06-20 | International Business Machines Corporation | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
JP4069867B2 (ja) * | 2004-01-05 | 2008-04-02 | セイコーエプソン株式会社 | 部材の接合方法 |
US8535383B2 (en) * | 2004-01-12 | 2013-09-17 | DePuy Synthes Products, LLC | Systems and methods for compartmental replacement in a knee |
US20060157750A1 (en) * | 2005-01-20 | 2006-07-20 | Samsung Electronics Co., Ltd. | Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof |
US7790561B2 (en) * | 2005-07-01 | 2010-09-07 | Texas Instruments Incorporated | Gate sidewall spacer and method of manufacture therefor |
US7399690B2 (en) | 2005-11-08 | 2008-07-15 | Infineon Technologies Ag | Methods of fabricating semiconductor devices and structures thereof |
US20070224808A1 (en) * | 2006-03-23 | 2007-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicided gates for CMOS devices |
US7361539B2 (en) * | 2006-05-16 | 2008-04-22 | International Business Machines Corporation | Dual stress liner |
US7768041B2 (en) * | 2006-06-21 | 2010-08-03 | International Business Machines Corporation | Multiple conduction state devices having differently stressed liners |
JP4716938B2 (ja) * | 2006-06-30 | 2011-07-06 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US7696036B2 (en) * | 2007-06-14 | 2010-04-13 | International Business Machines Corporation | CMOS transistors with differential oxygen content high-k dielectrics |
KR100864930B1 (ko) * | 2007-11-30 | 2008-10-23 | 주식회사 동부하이텍 | 액정 표시 소자용 구동 소자의 제조 방법 |
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- 2004-10-27 JP JP2004312244A patent/JP4587774B2/ja not_active Expired - Fee Related
- 2004-11-11 CN CNB2004100909735A patent/CN100452302C/zh not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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JP2005150713A (ja) | 2005-06-09 |
KR100562234B1 (ko) | 2006-03-22 |
US7064027B2 (en) | 2006-06-20 |
US7307323B2 (en) | 2007-12-11 |
US20050104095A1 (en) | 2005-05-19 |
CN100452302C (zh) | 2009-01-14 |
CN1617304A (zh) | 2005-05-18 |
KR20050046536A (ko) | 2005-05-18 |
US20080036017A1 (en) | 2008-02-14 |
US20060145275A1 (en) | 2006-07-06 |
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