JP4566105B2 - 電子部品およびその実装構造 - Google Patents
電子部品およびその実装構造 Download PDFInfo
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- JP4566105B2 JP4566105B2 JP2005280624A JP2005280624A JP4566105B2 JP 4566105 B2 JP4566105 B2 JP 4566105B2 JP 2005280624 A JP2005280624 A JP 2005280624A JP 2005280624 A JP2005280624 A JP 2005280624A JP 4566105 B2 JP4566105 B2 JP 4566105B2
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- Prior art keywords
- wiring
- insulating substrate
- substrate
- electric element
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
2・・・絶縁基板
3・・・配線基板
4・・・外部回路基板
10・・・電子部品
11・・・接続パッド
13・・・接着層
14・・・ボンディングワイヤ
15・・・封止樹脂
27・・・接着層
31・・・絶縁層
32・・・内部配線
33・・・ビアホール配線
34、35・・・表層配線
36・・・接続導体
41・・・配線
t1・・・絶縁基板の厚み
S1・・・絶縁基板の主面の面積
S2・・・配線基板の主面の面積
Claims (6)
- 配線基板の上面に該配線基板よりも面積の小さい絶縁基板が接合され、前記絶縁基板の上面に電気素子が接合されてなる電子部品において、前記電気素子は、内部の配線の周囲の絶縁領域が多孔質であるか、または、駆動あるいは振動することにより機能を発現する立体構造を有しており、前記絶縁基板が前記電気素子と前記配線基板とを電気的に接続するための内部配線を具備しておらず、前記配線基板と前記絶縁基板および前記絶縁基板と前記電気素子とをそれぞれ有機樹脂を主体とする接着層を介して接合してなり、前記配線基板の前記絶縁基板の周辺に形成された表層配線と前記電気素子とをボンディングワイヤを介して電気的に接続してなり、0〜150℃における、前記絶縁基板の熱膨張係数と前記電気素子の熱膨張係数との差が、前記絶縁基板の熱膨張係数と前記配線基板の熱膨張係数との差よりも小さいことを特徴とする電子部品。
- 0〜150℃における、前記絶縁基板の熱膨張係数と前記電気素子の熱膨張係数との差が2×10−6/℃以下であることを特徴とする請求項1記載の電子部品。
- 前記絶縁基板のヤング率が100GPa以上であることを特徴とする請求項1または2記載の電子部品。
- 前記絶縁基板の厚みが0.2〜1mmであることを特徴とする請求項1〜3のいずれかに記載の電子部品。
- 請求項1〜4のいずれかに記載の電子部品を外部回路基板に、前記配線基板の表面に設けられた複数の外部接続用表層電極と前記外部回路基板の表面に設けられた複数の接続端子とを接続用導体を介して接続して、実装しており、0〜150℃における、前記外部回路基板の熱膨張係数と前記配線基板の熱膨張係数との差が9×10−6/℃以下であることを特徴とする電子部品の実装構造。
- 前記外部回路基板がプリント樹脂基板であることを特徴とする請求項5に記載の電子部品の実装構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005280624A JP4566105B2 (ja) | 2005-09-27 | 2005-09-27 | 電子部品およびその実装構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2005280624A JP4566105B2 (ja) | 2005-09-27 | 2005-09-27 | 電子部品およびその実装構造 |
Publications (2)
Publication Number | Publication Date |
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JP2007095832A JP2007095832A (ja) | 2007-04-12 |
JP4566105B2 true JP4566105B2 (ja) | 2010-10-20 |
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Application Number | Title | Priority Date | Filing Date |
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JP2005280624A Expired - Fee Related JP4566105B2 (ja) | 2005-09-27 | 2005-09-27 | 電子部品およびその実装構造 |
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JP (1) | JP4566105B2 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273240A (ja) * | 1994-03-31 | 1995-10-20 | Hitachi Ltd | 樹脂封止形半導体装置 |
JP2002076193A (ja) * | 2000-08-30 | 2002-03-15 | Kyocera Corp | 半導体素子収納用パッケージおよびパッケージ実装基板 |
JP2005026363A (ja) * | 2003-06-30 | 2005-01-27 | Toshiba Corp | 半導体装置とその製造方法 |
JP2005050878A (ja) * | 2003-07-29 | 2005-02-24 | Kyocera Corp | 積層型配線基板および電気装置並びにその実装構造 |
-
2005
- 2005-09-27 JP JP2005280624A patent/JP4566105B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273240A (ja) * | 1994-03-31 | 1995-10-20 | Hitachi Ltd | 樹脂封止形半導体装置 |
JP2002076193A (ja) * | 2000-08-30 | 2002-03-15 | Kyocera Corp | 半導体素子収納用パッケージおよびパッケージ実装基板 |
JP2005026363A (ja) * | 2003-06-30 | 2005-01-27 | Toshiba Corp | 半導体装置とその製造方法 |
JP2005050878A (ja) * | 2003-07-29 | 2005-02-24 | Kyocera Corp | 積層型配線基板および電気装置並びにその実装構造 |
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JP2007095832A (ja) | 2007-04-12 |
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