JP4524190B2 - 半導体構造体を製造する方法 - Google Patents
半導体構造体を製造する方法 Download PDFInfo
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- JP4524190B2 JP4524190B2 JP2004566393A JP2004566393A JP4524190B2 JP 4524190 B2 JP4524190 B2 JP 4524190B2 JP 2004566393 A JP2004566393 A JP 2004566393A JP 2004566393 A JP2004566393 A JP 2004566393A JP 4524190 B2 JP4524190 B2 JP 4524190B2
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- 238000000034 method Methods 0.000 title claims description 47
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 37
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 76
- 239000004020 conductor Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Description
12 メモリ・セル
14 トレンチ型蓄積キャパシタ
16 縦型MOSFET
18 深トレンチ
20 n+型埋め込みプレート
22 窒化物/酸化物ノード誘電体
24 n+型ポリシリコン
26 n+型ポリシリコン
28 カラー酸化物
30 n+型埋め込みストラップ拡散領域
34 ゲート酸化物
36 n+型ポリシリコン・ゲート導体
38 パッド膜
40 薄層
42 シリコン窒化物層
44 ハードマスク層
46 トレンチ
48 スペーサ
52 SiGe層
56 上表面
58 エピタキシャル・シリコン
58 歪みシリコン層
60 シリコン窒化物層
62 浅トレンチ分離(STI)
64 支援ゲート誘電体
66 支援ゲート導体
68 ワード線導体
70 シリコン窒化物
Claims (16)
- (a)無歪み領域にメモリ・セルが形成されている半導体基板を準備するステップと、
(b)前記半導体基板のうち前記メモリ・セルが形成されている無歪み領域に隣接する部分に歪み層領域を選択的に形成するステップと、
(c)前記歪み層領域に金属−酸化物−半導体型電界効果トランジスタ(MOSFET)を形成するステップとを含む、半導体構造体を製造する方法。 - 前記メモリ・セルが、トレンチ型蓄積キャパシタ及び縦型MOSFETを有するDRAMセルであり、前記歪み層領域のMOSFETが支援部のMOSFETである、請求項1に記載の方法。
- 前記半導体基板がシリコンであり、前記ステップ(b)が、SiGe層及び該SiGe層上に歪みシリコン層を形成する、請求項1に記載の方法。
- (イ)無歪み層領域にメモリ・セルが形成された半導体基板を準備するステップと、
(ロ)前記半導体基板のうち前記メモリ・セルが形成されている無歪み領域に隣接して底面および側壁面を有するトレンチを形成するステップと、
(ハ)前記トレンチにSiGe層を成長させるステップと、
(ニ)前記SiGe層の上に歪みシリコン層を成長させるステップと、
(ホ)前記歪みシリコン層にMOSFETを形成するステップとを含む、半導体構造体を製造する方法。 - 前記メモリ・セルが、トレンチ型蓄積キャパシタ及び縦型MOSFETを有するDRAMセルであり、前記歪みシリコン層のMOSFETが支援部のMOSFETである、請求項4に記載の方法。
- 前記ステップ(ロ)と前記ステップ(ハ)の間に、前記トレンチの側壁面にスペーサを形成するステップを行う、請求項4に記載の方法。
- 前記スペーサの材料がシリコン酸化物又はシリコン窒化物である、請求項6に記載の方法。
- 前記ステップ(ハ)が、前記SiGe層をエピタキシャルに成長させる、請求項4に記載の方法。
- 前記ステップ(ニ)が、 前記歪みシリコン層をエピタキシャルに成長させる、請求項4に記載の方法。
- 前記歪みシリコンの層の厚さが2.5nm〜10nmである、請求項4に記載の方法。
- (あ)無歪み層領域にメモリ・セルが形成された半導体基板を準備するステップと、
(い)前記メモリ・セルが形成されている無歪み領域の上及び前記半導体基板のうち前記無歪み層領域に隣接する領域の表面に少なくとも第1シリコン酸化物層、第1シリコン窒化物層及び第2シリコン酸化物層をこの順番で形成するステップと、
(う)前記メモリ・セルが形成されている無歪み領域に隣接する領域の前記第1シリコン酸化物層、前記第1シリコン窒化物層、前記第2シリコン酸化物層及び前記第1シリコン酸化物層の下の前記半導体基板の部分を除去することによりトレンチを形成するステップと、
(え)前記メモリ・セルが形成されている無歪み領域の前記第2シリコン酸化物層を除去するステップと、
(お)前記トレンチの側壁面にスペーサを形成するステップと、
(か)前記トレンチ内にSiGe層を成長させるステップと、
(き)前記SiGe層の上に歪みシリコン層を成長させるステップと、
(く)前記メモリ・セルが形成されている無歪み領域の前記第1シリコン窒化物層を除去するステップと、
(け)前記第1シリコン酸化物層の上に第2シリコン窒化物層を形成するステップと、
(こ)前記歪みシリコン層に浅いトレンチ分離領域を形成し、該浅いトレンチ分離領域により囲まれた歪みシリコン層にMOSFETを形成するステップとを記載の順序で行う、半導体構造体を製造する方法。 - 前記メモリ・セルが、トレンチ型蓄積キャパシタ及び縦型MOSFETを有するDRAMセルであり、前記歪みシリコン層のMOSFETが支援部のMOSFETである、請求項11に記載の方法。
- 前記スペーサの材料がシリコン酸化物又はシリコン窒化物である、請求項11に記載の方法。
- 前記ステップ(か)が、前記SiGe層をエピタキシャルに成長させる、請求項11に記載の方法。
- 前記歪みシリコンの層の厚さが2.5nm〜10nmである、請求項11に記載の方法。
- 前記ステップ(か)と前記ステップ(き)との間に、前記SiGe層の上表面が前記第1シリコン窒化物層の上表面よりも下になるまで前記SiGe層を選択的に窪ませるステップを行う、請求項11に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2003/000562 WO2004064148A1 (en) | 2003-01-08 | 2003-01-08 | High performance embedded dram technology with strained silicon |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006513567A JP2006513567A (ja) | 2006-04-20 |
JP4524190B2 true JP4524190B2 (ja) | 2010-08-11 |
Family
ID=32710271
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004566393A Expired - Fee Related JP4524190B2 (ja) | 2003-01-08 | 2003-01-08 | 半導体構造体を製造する方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7262451B2 (ja) |
EP (1) | EP1584108A4 (ja) |
JP (1) | JP4524190B2 (ja) |
CN (1) | CN100505218C (ja) |
AU (1) | AU2003202254A1 (ja) |
TW (1) | TWI294666B (ja) |
WO (1) | WO2004064148A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6891209B2 (en) * | 2001-08-13 | 2005-05-10 | Amberwave Systems Corporation | Dynamic random access memory trench capacitors |
JP4322706B2 (ja) * | 2004-02-27 | 2009-09-02 | 株式会社東芝 | 半導体装置の製造方法 |
JP4177775B2 (ja) * | 2004-03-16 | 2008-11-05 | 株式会社東芝 | 半導体基板及びその製造方法並びに半導体装置 |
US7384829B2 (en) | 2004-07-23 | 2008-06-10 | International Business Machines Corporation | Patterned strained semiconductor substrate and device |
US7704844B2 (en) | 2007-10-04 | 2010-04-27 | International Business Machines Corporation | High performance MOSFET |
DE102011005639B4 (de) * | 2011-03-16 | 2016-05-25 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Reduzieren der Defektrate während des Abscheidens einer Kanalhalbleiterlegierung in ein in-situ-abgesenktes aktives Gebiet |
TWI508139B (zh) * | 2011-08-17 | 2015-11-11 | United Microelectronics Corp | 製作半導體裝置的方法 |
US8669611B2 (en) | 2012-07-11 | 2014-03-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for power MOS transistor |
US9130060B2 (en) | 2012-07-11 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having a vertical power MOS transistor |
CN109687864A (zh) * | 2017-10-19 | 2019-04-26 | 成都海存艾匹科技有限公司 | 含有可编程计算单元的可编程门阵列 |
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US5250448A (en) * | 1990-01-31 | 1993-10-05 | Kabushiki Kaisha Toshiba | Method of fabricating a miniaturized heterojunction bipolar transistor |
JPH05144834A (ja) * | 1991-03-20 | 1993-06-11 | Hitachi Ltd | バイポーラトランジスタ及びその製造方法 |
US5212110A (en) * | 1992-05-26 | 1993-05-18 | Motorola, Inc. | Method for forming isolation regions in a semiconductor device |
US5399507A (en) * | 1994-06-27 | 1995-03-21 | Motorola, Inc. | Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications |
JP2953567B2 (ja) * | 1997-02-06 | 1999-09-27 | 日本電気株式会社 | 半導体装置の製造方法 |
JP4258034B2 (ja) * | 1998-05-27 | 2009-04-30 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
US6333532B1 (en) * | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
JP4074051B2 (ja) * | 1999-08-31 | 2008-04-09 | 株式会社東芝 | 半導体基板およびその製造方法 |
JP3512701B2 (ja) * | 2000-03-10 | 2004-03-31 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2001338988A (ja) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
CA2316480A1 (en) * | 2000-08-18 | 2002-02-18 | Tim Mccarthy | Adjustable partition assembly |
JP3998408B2 (ja) * | 2000-09-29 | 2007-10-24 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6350653B1 (en) * | 2000-10-12 | 2002-02-26 | International Business Machines Corporation | Embedded DRAM on silicon-on-insulator substrate |
JP3875040B2 (ja) * | 2001-05-17 | 2007-01-31 | シャープ株式会社 | 半導体基板及びその製造方法ならびに半導体装置及びその製造方法 |
KR100414204B1 (ko) * | 2001-05-31 | 2004-01-07 | 삼성전자주식회사 | 캐퍼시터 소자를 갖는 반도체 메모리 장치 및 그 형성 방법 |
US6891209B2 (en) * | 2001-08-13 | 2005-05-10 | Amberwave Systems Corporation | Dynamic random access memory trench capacitors |
JP2004165197A (ja) * | 2002-11-08 | 2004-06-10 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
-
2003
- 2003-01-08 CN CNB038257718A patent/CN100505218C/zh not_active Expired - Fee Related
- 2003-01-08 US US10/541,660 patent/US7262451B2/en not_active Expired - Fee Related
- 2003-01-08 EP EP03701269A patent/EP1584108A4/en not_active Withdrawn
- 2003-01-08 JP JP2004566393A patent/JP4524190B2/ja not_active Expired - Fee Related
- 2003-01-08 AU AU2003202254A patent/AU2003202254A1/en not_active Abandoned
- 2003-01-08 WO PCT/US2003/000562 patent/WO2004064148A1/en active Application Filing
-
2004
- 2004-01-05 TW TW093100168A patent/TWI294666B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
AU2003202254A1 (en) | 2004-08-10 |
US7262451B2 (en) | 2007-08-28 |
EP1584108A4 (en) | 2006-06-07 |
CN100505218C (zh) | 2009-06-24 |
EP1584108A1 (en) | 2005-10-12 |
CN1720616A (zh) | 2006-01-11 |
US20060024877A1 (en) | 2006-02-02 |
JP2006513567A (ja) | 2006-04-20 |
TWI294666B (en) | 2008-03-11 |
WO2004064148A1 (en) | 2004-07-29 |
TW200524093A (en) | 2005-07-16 |
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