JP4511511B2 - Manufacturing method of multilayer wiring board with built-in capacitor element - Google Patents

Manufacturing method of multilayer wiring board with built-in capacitor element Download PDF

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JP4511511B2
JP4511511B2 JP2006333640A JP2006333640A JP4511511B2 JP 4511511 B2 JP4511511 B2 JP 4511511B2 JP 2006333640 A JP2006333640 A JP 2006333640A JP 2006333640 A JP2006333640 A JP 2006333640A JP 4511511 B2 JP4511511 B2 JP 4511511B2
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capacitor element
wiring board
resin
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multilayer wiring
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JP2007103964A (en
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勲 宮谷
忠 長澤
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Kyocera Corp
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Description

本発明は、各種ＡＶ機器や家電機器・通信機器・コンピュータやその周辺機器等の電子機器に使用される配線基板に関する。   The present invention relates to a wiring board used in various AV devices, home appliances, communication devices, computers, and electronic devices such as peripheral devices.

従来、配線基板はアルミナ等のセラミック材料から成る絶縁層あるいはガラスエポキシ樹脂等の有機樹脂材料から成る絶縁層の内部および表面に複数の配線導体を形成し、上下に位置する配線導体間を絶縁層に形成した貫通導体を介して電気的に接続して成り、この配線基板の表面に半導体素子やコンデンサ・抵抗素子等の電子素子を搭載取着するとともにこれらの電極を各配線導体に接続することによって電子機器に使用される電子装置が形成されている。   Conventionally, a wiring board has a plurality of wiring conductors formed inside and on the surface of an insulating layer made of a ceramic material such as alumina or an organic resin material such as glass epoxy resin, and an insulating layer is formed between upper and lower wiring conductors. Electrically connected through through conductors formed on the board, and mounting and mounting electronic elements such as semiconductor elements, capacitors and resistance elements on the surface of this wiring board, and connecting these electrodes to each wiring conductor Thus, an electronic device used for an electronic device is formed.

しかしながら、近年、電子機器は、移動体通信機器に代表されるように小型・薄型・軽量化が要求されてきており、このような電子機器に搭載される配線基板も小型・高密度化が要求されるようになってきている。   However, in recent years, electronic devices have been required to be small, thin, and lightweight as represented by mobile communication devices, and wiring boards mounted on such electronic devices are also required to be small and high in density. It has come to be.

このような要求に対応するために、特開平11-67961号公報や特開平11-220262号公報には、配線基板の表面に搭載される電子素子の数を減らして配線基板を小型化する目的で、配線基板の内部にチップ状コンデンサ素子を実装することが提案されている。
特開平11-67961号公報 特開平11-220262号公報 In order to meet such demands, Japanese Patent Application Laid-Open No. 11-67961 and Japanese Patent Application Laid-Open No. 11-220262 disclose the purpose of reducing the size of the wiring board by reducing the number of electronic elements mounted on the surface of the wiring board. Therefore, it has been proposed to mount a chip capacitor element inside the wiring board.
Japanese Patent Laid-Open No. 11-67961 Japanese Patent Laid-Open No. 11-220262

しかしながら、特開平11-67961号公報に示されるように、樹脂基板上に導体回路を形成するとともに、この導体回路にチップコンデンサを実装後、チップコンデンサの形状に相当する開口の形成された層間絶縁フィルムを載置し、さらにその上に樹脂基板を積層することによりコンデンサ内蔵多層プリント配線板を製作した場合、層間絶縁フィルムおよび樹脂基板を積層する際に、層間絶縁フィルムと樹脂基板とが界面でずれを生じ、層間絶縁フィルムが横方向よりチップコンデンサに応力を加えるために、チップコンデンサが傾き接続不良が生じてしまうという問題点を有していた。   However, as disclosed in JP-A-11-67961, a conductor circuit is formed on a resin substrate, and after mounting a chip capacitor on the conductor circuit, an interlayer insulation in which an opening corresponding to the shape of the chip capacitor is formed When a multilayer printed wiring board with a built-in capacitor is manufactured by placing a film and then laminating a resin substrate on the film, the interlayer insulation film and the resin substrate are placed at the interface when the interlayer insulation film and the resin substrate are laminated. There is a problem that the chip capacitor is inclined and connection failure occurs because the interlayer insulating film applies stress to the chip capacitor from the lateral direction due to deviation.

また、特開平11-220262号公報に示されるように、あらかじめ離型フィルム上の配線パターンにコンデンサ素子等の回路部品を実装し、これを未硬化樹脂から成る板状体に位置合わせして重ねるとともに加圧して回路部品を樹脂に埋設することにより、回路部品が埋設された回路部品内蔵モジュールを製作した場合、未硬化樹脂の粘度が高い場合は、樹脂の流動性が低いために回路部品を埋設する際に、回路部品に強度の応力が加わり、回路部品の位置がずれて接続不良を生じてしまったり、あるいは十分に埋設されずに回路部品が突出した状態と成り、多層化の際に積層不良を生じて断線してしまうという問題点を有していた。   Also, as disclosed in Japanese Patent Laid-Open No. 11-220262, circuit components such as capacitor elements are mounted in advance on a wiring pattern on a release film, and this is aligned and stacked on a plate-like body made of uncured resin. When the circuit component built-in module in which the circuit component is embedded is manufactured by pressurizing together with the resin and the circuit component is embedded in the resin, if the viscosity of the uncured resin is high, the flowability of the resin is low. When embedding, strong stress is applied to the circuit components, and the position of the circuit components shifts, resulting in poor connection, or the circuit components are not fully embedded and the circuit components protrude. There was a problem in that the stacking failure would cause disconnection.

また、未硬化樹脂の粘度を回路部品を埋設しやすいように低くした場合は、配線パターンや貫通導体が樹脂流れによって本来の位置から流され位置ずれを起こしてショート不良を発生させてしまうという問題点を有していた。   In addition, if the viscosity of the uncured resin is lowered so that circuit components can be embedded easily, the wiring pattern and the through conductor are caused to flow from the original position due to the resin flow, causing a short-circuit failure. Had a point.

本発明はかかる従来技術の問題点に鑑み案出されたものであり、その目的は、位置精度に優れるとともに接続信頼性・絶縁信頼性に優れた小型で軽量なコンデンサ素子内蔵多層配線基板を提供することにある。   The present invention has been devised in view of the problems of the prior art, and its purpose is to provide a small and lightweight multilayer wiring board with a built-in capacitor element that has excellent positional accuracy and excellent connection reliability and insulation reliability. There is to do.

本発明のコンデンサ素子内蔵多層配線基板の製造方法は、上端に幅広部を下端に幅狭部を有する貫通引き出し電極部を備えたコンデンサ素子を、一主面に凹部を有する未硬化の第１樹脂前駆体シート上に、前記コンデンサ素子の下部が前記凹部内に配置され、上部が前記第１樹脂前駆体シートの一主面より上方に位置するように配置させるとともに、前記第１樹脂前駆体シート上に、前記コンデンサ素子の上部を収容するための空洞部を有した未硬化の第２樹脂前駆体シートを、該第２樹脂前駆体シート上に、前記コンデンサ素子の上面を覆い、前記貫通引き出し電極部の幅広部に接続される導体を有する未硬化の第３樹脂前駆体シートをそれぞれ配置させる工程と、前記第１乃至第３樹脂前駆体シートを硬化させることにより樹脂絶縁層を形成するとともに、これら樹脂絶縁層から成る積層構造体の内部に前記コンデンサ素子を固定する工程と、を含むことを特徴とする。

The method of manufacturing a multilayer wiring board with a built-in capacitor element according to the present invention includes: a capacitor element having a through lead electrode portion having a wide portion at the upper end and a narrow portion at the lower end; the precursor sheet, the lower capacitor element is disposed in the recess, together with the upper part is arranged so as to be located above the one main surface of the first resin precursor sheet, the first resin precursor sheet above, the second resin precursor sheet uncured having a cavity for receiving the upper portion of said capacitor element, in the second resin precursor sheet to cover the upper surface of the capacitor element, said through drawers a step of the third resin precursor sheet uncured having conductors connected to the wide portion of the electrode portions respectively disposed, a resin insulating layer by curing the first to third resin precursor sheet As well as formed, characterized in that it comprises a step of fixing the capacitor element inside a laminated structure composed of these resin insulating layer.

本発明の電子装置の製造方法は、上記本発明のコンデンサ素子内蔵多層配線基板に電子素子を搭載する工程を含むことを特徴とする。
A method for manufacturing an electronic device according to the present invention includes a step of mounting an electronic element on the multilayer wiring board with a built-in capacitor element according to the present invention.

本発明によれば、コンデンサ素子を絶縁層の凹部に固定することができるため、絶縁層を積層した際に、絶縁層同士が界面でずれを生じたとしてもコンデンサ素子が傾くことはなく、接続信頼性に優れたものとすることができる。   According to the present invention, since the capacitor element can be fixed in the recess of the insulating layer, even when the insulating layers are stacked, the capacitor element is not inclined even if the insulating layers are displaced at the interface. The reliability can be improved.

また、絶縁層の少なくとも一層に設けられた収容部の内部にコンデンサ素子を挿入するため、コンデンサ素子を埋設する際に、絶縁層の樹脂が妨げになることはなく容易に埋設することが可能となり、コンデンサ素子の位置ずれを生じることがない。   Further, since the capacitor element is inserted into the housing portion provided in at least one layer of the insulating layer, the resin of the insulating layer is not hindered when embedding the capacitor element, and can be easily embedded. No positional deviation of the capacitor element occurs.

さらに、コンデンサ素子が埋設しやすいように絶縁層の樹脂粘度を極度に低くする必要もないため、配線導体や貫通導体が位置ずれをしてショート不良が発生することのない絶縁信頼性に優れたものとすることができる。   Furthermore, since it is not necessary to extremely reduce the resin viscosity of the insulating layer so that the capacitor element can be embedded easily, the wiring conductor and the through conductor are not misaligned and the insulation reliability does not occur. Can be.

次に本発明のコンデンサ素子内蔵多層配線基板および電子装置を添付の図面に基づいて詳細に説明する。   Next, the multilayer wiring board with built-in capacitor element and the electronic device of the present invention will be described in detail with reference to the accompanying drawings.

図１は、本発明のコンデンサ素子内蔵多層配線基板の実施の形態の一例を示す断面図であり、本例では、コンデンサを１個内蔵した場合を示している。また、図２は、本発明のコンデンサ内蔵多層配線基板に内蔵されるコンデンサ素子の実施の形態の一例を示す断面図である。このコンデンサ素子内蔵多層配線基板に半導体素子やコンデンサ・抵抗素子等の電子素子を搭載取着するとともにこれらの電極を各配線導体に接続することによって電子機器に使用される電子装置となる。   FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board with a built-in capacitor element according to the present invention. In this example, a case where one capacitor is built is shown. FIG. 2 is a cross-sectional view showing an example of an embodiment of the capacitor element built in the multilayer wiring board with built-in capacitor of the present invention. By mounting and attaching electronic elements such as a semiconductor element and a capacitor / resistor element on the capacitor element built-in multilayer wiring board, and connecting these electrodes to each wiring conductor, an electronic device used in an electronic device is obtained.

これらの図において、１は絶縁層、２は配線導体、３は貫通導体、７はコンデンサ素子で、主にこれらで本発明のコンデンサ素子内蔵多層配線基板８が構成されている。   In these drawings, reference numeral 1 is an insulating layer, 2 is a wiring conductor, 3 is a through conductor, and 7 is a capacitor element. The capacitor element built-in multilayer wiring board 8 of the present invention is mainly constituted by these.

なお、本例のコンデンサ素子内蔵多層配線基板８は、絶縁層１を３層積層して成るとともに、絶縁層1の少なくとも１層にはコンデンサ素子の収容部となる空洞部４（以下、収容部を空洞部ともいう）が形成され、さらに、空洞部４の底部は絶縁層１に形成された凹部９により形成されており、これらの内部には、コンデンサ素子７が埋設されている。また、コンデンサ素子７は、引き出し電極部10により配線導体２あるいは貫通導体３と電気的に接続されている。 The multilayer wiring board 8 with a built-in capacitor element of this example is formed by laminating three layers of insulating layers 1, and at least one layer of the insulating layer 1 has a cavity portion 4 (hereinafter referred to as a housing portion) serving as a housing portion for capacitor elements. And the bottom of the cavity 4 is formed by a recess 9 formed in the insulating layer 1, and a capacitor element 7 is embedded in these. Further, the capacitor element 7 is electrically connected to the wiring conductor 2 or the through conductor 3 by the lead electrode portion 10.

コンデンサ素子内蔵多層配線基板８に内蔵されるコンデンサ素子７は、縦・横・高さがそれぞれ１〜５ｍｍの直方体であり、図２に断面図で示すように、電極層５とセラミック誘電体層６とを交互に積層することにより形成されている。   The capacitor element 7 incorporated in the multilayer wiring board 8 with a built-in capacitor element is a rectangular parallelepiped having a length, width, and height of 1 to 5 mm. As shown in a sectional view of FIG. 2, the electrode layer 5 and the ceramic dielectric layer And 6 are alternately laminated.

このようなセラミック誘電体層６の材料としては、種々の誘電体セラミック材料を用いることができ、例えば、ＢａＴｉＯ3やＬａＴｉＯ3・ＣａＴｉＯ3・ＳｒＴｉＯ3等のセラミック組成物、あるいは、ＢａＴｉＯ3の構成元素であるＢａをＣａで、ＴｉをＺｒやＳｎで部分的に置換した固溶体等のチタン酸バリウム系材料や、鉛系ペロブスカイト型構造化合物等が挙げられる。   As the material of the ceramic dielectric layer 6, various dielectric ceramic materials can be used. For example, BaTiO 3, LaTiO 3, CaTiO 3, SrTiO 3, or other ceramic compositions, or Ba, which is a constituent element of BaTiO 3, can be used. Examples thereof include barium titanate-based materials such as solid solutions in which Ti is partially substituted with Zr or Sn by Ca, lead-based perovskite-type structural compounds, and the like.

また、電極層５を形成する材料としては、例えばＰｄやＡｇ・Ｐｔ・Ｎｉ・Ｃｕ・Ｐｂ等の金属やそれらの合金が用いられる。   Moreover, as a material which forms the electrode layer 5, metals, such as Pd, Ag * Pt * Ni * Cu * Pb, and those alloys are used, for example.

さらに、コンデンサ素子７は、多数の電極層５に電気的に接続した複数の引き出し電極部10を有しており、これらはコンデンサ素子７の電極層５とコンデンサ素子内蔵多層配線基板12の配線導体２あるいは貫通導体３と電気的に接続する作用を成す。   Furthermore, the capacitor element 7 has a plurality of lead electrode portions 10 electrically connected to a large number of electrode layers 5, which are the wiring layers of the electrode layer 5 of the capacitor element 7 and the multilayer wiring substrate 12 with a built-in capacitor element. 2 or the through conductor 3 is electrically connected.

このような引き出し電極部10は、電極層５とセラミック誘電体層６との積層体に貫通孔を形成し、これに導体を埋め込むことによって形成される。このような構成により、微細化および工程の容易性が容易となる。   Such an extraction electrode portion 10 is formed by forming a through hole in a laminate of the electrode layer 5 and the ceramic dielectric layer 6 and embedding a conductor in the through hole. Such a configuration facilitates miniaturization and ease of process.

このようなコンデンサ素子７に形成される貫通孔は、電極層５とセラミック誘電体層６とから成る積層体に、パンチングによる打ち抜き加工やＵＶ−ＹＡＧレーザやエキシマレーザ・炭酸ガスレーザ等によるレーザ穿設加工等の方法により形成され、特に微細な貫通孔とするためには、レーザによる穿設加工により形成されることが好ましい。また、貫通孔の径は数10μｍ〜数ｍｍであり、コンデンサ素子７の大きさにあわせて適宜決めればよい。   Such a through-hole formed in the capacitor element 7 is formed by punching a laminated body composed of the electrode layer 5 and the ceramic dielectric layer 6 or laser drilling by a UV-YAG laser, an excimer laser, a carbon dioxide gas laser, or the like. It is formed by a method such as processing, and in order to form a particularly fine through hole, it is preferably formed by laser drilling. The diameter of the through hole is several tens of μm to several mm, and may be appropriately determined according to the size of the capacitor element 7.

なお、貫通孔は、内部に充填される導体と電極層５との電気的接続を良好にするために、打ち抜き加工やレーザ穿設加工後に超音波洗浄処理やデスミア処理等を施しても良い。   The through hole may be subjected to an ultrasonic cleaning process, a desmear process, or the like after the punching process or the laser drilling process in order to improve the electrical connection between the conductor filled inside and the electrode layer 5.

また、貫通孔に充填される導体としては、ＰｄやＡｇ・Ｐｔ・Ｎｉ・Ｃｕ・Ｐｂ等の金属やそれらの合金が用いられ、特に電極層５との電気的接続を良好にするという観点からは、電極層５と同じ材質のものを含有することが好ましい。   Moreover, as a conductor with which a through-hole is filled, metals, such as Pd, Ag * Pt * Ni * Cu * Pb, and those alloys are used, especially from a viewpoint of making the electrical connection with the electrode layer 5 favorable. Preferably contains the same material as the electrode layer 5.

このような貫通孔に充填される導体は、有機溶剤に有機バインダ樹脂を溶解させた有機ビヒクル中に金属粉末を分散させて成る導電ペーストを貫通孔にスクリーン印刷法等の方法で充填することにより形成される。なお、ビヒクル中には、これらの他、各種分散剤・活性剤・可塑剤などが必要に応じて添加されても良い。   The conductor filled in such a through-hole is formed by filling the through-hole with a conductive paste in which metal powder is dispersed in an organic vehicle in which an organic binder resin is dissolved in an organic solvent by a method such as screen printing. It is formed. In addition to these, various dispersants, activators, plasticizers and the like may be added to the vehicle as necessary.

また、導電ペーストに用いられる有機バインダ樹脂は、金属粉末を均質に分散させるとともに貫通孔への埋め込みに適正な粘度とレオロジーを与える役割をもっており、例えば、アクリル樹脂やフェノール樹脂・アルキッド樹脂・ロジンエステル・エチルセルロース・メチルセルロース・ＰＶＡ(ポリビニルアルコール)・ポリビニルブチラート等が挙げられる。特に、金属粉末の分散性を良くするという観点からは、アクリル樹脂を用いることが好ましい。   In addition, the organic binder resin used in the conductive paste has the role of uniformly dispersing the metal powder and imparting appropriate viscosity and rheology for embedding in the through hole. For example, acrylic resin, phenol resin, alkyd resin, rosin ester -Ethyl cellulose, methyl cellulose, PVA (polyvinyl alcohol), polyvinyl butyrate, etc. In particular, it is preferable to use an acrylic resin from the viewpoint of improving the dispersibility of the metal powder.

さらに、導電ペーストに用いられる有機溶剤は、有機バインダ樹脂を溶解して金属粉末粒子を分散させ、このような混合系全体をペースト状にする役割をなし、例えば、α-テルピネオールやベンジルアルコール等のアルコール系や炭化水素系・エーテル系・ＢＣＡ（ブチルカルビトールアセテート）等のエステル系・ナフサ等が用いられ、特に、金属粉末の分散性を良くするという観点からは、α-テルピネオール等のアルコール系溶剤を用いることが好ましい。   Further, the organic solvent used in the conductive paste has a role of dissolving the organic binder resin to disperse the metal powder particles and making the entire mixed system into a paste, such as α-terpineol or benzyl alcohol. Alcohol-based, hydrocarbon-based, ether-based, ester-based such as BCA (butyl carbitol acetate), naphtha, etc. are used. Especially from the viewpoint of improving the dispersibility of metal powder, alcohol-based such as α-terpineol It is preferable to use a solvent.

さらにまた、導電ペーストは、埋め込み・焼成後のコンデンサ磁器への接着強度を上げるために、ガラスフリットやセラミックフリットを加えたペーストとすることができる。この場合のガラスフリットやセラミックフリットとしては特に限定されるものではなく、例えば、ホウ珪酸塩系やホウ珪酸亜鉛系のガラス・チタニア・チタン酸バリウムなどのチタン系酸化物などを適宜用いることができる。   Furthermore, the conductive paste can be a paste to which glass frit or ceramic frit is added in order to increase the adhesive strength to the capacitor ceramic after embedding and firing. In this case, the glass frit or ceramic frit is not particularly limited, and for example, borosilicate-based or zinc borosilicate-based glass, titania, barium titanate-based oxides such as barium titanate can be used as appropriate. .

このようなコンデンサ素子７は、次の方法により製作される。まず、周知のシート成形法により作成されたセラミック誘電体層６と成る、例えばＢａＴｉＯ3誘電体セラミックグリーンシート表面に、周知のペースト作成法により作成したＮｉ金属ペーストをスクリーン印刷法により所定形状と成るように印刷して未焼成電極層を形成し、続いてこれらを所定順序に積層し、圧着して積層体を得る。そしてこれを800〜1600℃の温度で焼成することにより製作される。   Such a capacitor element 7 is manufactured by the following method. First, a Ni metal paste prepared by a well-known paste forming method is formed into a predetermined shape by a screen printing method on the surface of, for example, a BaTiO3 dielectric ceramic green sheet to be a ceramic dielectric layer 6 prepared by a well-known sheet forming method. To form an unsintered electrode layer, which are then laminated in a predetermined order and pressed to obtain a laminate. And this is manufactured by baking at the temperature of 800-1600 degreeC.

また、コンデンサ素子７の表面は、絶縁層１とコンデンサ素子７の接着性を向上させるという観点からは、セラミック誘電体層６の表面の算術平均粗さＲの最大値Ｒｍａｘが0.2μｍより大きく、望ましくは0.5μｍ以上、最適には1.0μｍ以上とすることが好ましい。なお、セラミック誘電体層６の表面粗さＲの最大値Ｒｍａｘが５μｍを超えると、コンデンサ素子７に割れや欠けが発生し易くなる傾向があるため、表面粗さＲの最大値Ｒｍａｘを５μｍ以下としておくことが好ましい。   Further, from the viewpoint of improving the adhesion between the insulating layer 1 and the capacitor element 7, the surface of the capacitor element 7 has a maximum value Rmax of the arithmetic average roughness R of the surface of the ceramic dielectric layer 6 larger than 0.2 μm. The thickness is desirably 0.5 μm or more, and optimally 1.0 μm or more. If the maximum value Rmax of the surface roughness R of the ceramic dielectric layer 6 exceeds 5 μm, the capacitor element 7 tends to be cracked or chipped. Therefore, the maximum value Rmax of the surface roughness R is 5 μm or less. It is preferable that

このようなコンデンサ素子７表面のセラミック誘電体層６の表面は、焼成前のグリーンシート積層体の段階で、積層体の表面をブラシ研磨による粗化処理やあらかじめ凹凸加工した平板を押し付けるなどの方法で物理的に凹凸をつけた後、あるいはレーザによりグリーンシート積層体表面に非貫通孔を開けることによりディンプル加工を施した後、焼成することにより所望の表面粗さとすることができる。   The surface of the ceramic dielectric layer 6 on the surface of the capacitor element 7 is a method such as roughening treatment by brush polishing or pressing a flat plate that has been processed in advance on the surface of the laminate at the stage of the green sheet laminate before firing. The surface roughness can be set to a desired surface roughness by physically baking the surface of the green sheet laminated body with a laser, or by performing dimple processing by opening a non-through hole on the surface of the green sheet laminate with a laser.

また、セラミック誘電体層６に用いられるセラミック材料よりも焼成時の耐熱性が高く平均粒子径が10μｍ以上のセラミック粉末、あるいはセラミック誘電体層６に用いられるセラミック材料の一部と反応性を有し平均径が10μｍ以上のセラミック粉末を一部が埋入するようにグリーンシート積層体表面に付着させて焼成することによって所望の表面粗さとしても良い。   In addition, the ceramic material used for the ceramic dielectric layer 6 has higher heat resistance during firing and is more reactive with ceramic powder having an average particle size of 10 μm or more, or a part of the ceramic material used for the ceramic dielectric layer 6. Then, the ceramic powder having an average diameter of 10 μm or more may be adhered to the surface of the green sheet laminate so as to be partially embedded and fired to obtain a desired surface roughness.

さらに、グリーンシート積層体の焼成後のコンデンサ素子の表面をサンドブラスト等の物理的手法あるいはエッチング等の化学的手法により粗化しても良い。   Further, the surface of the capacitor element after firing the green sheet laminate may be roughened by a physical method such as sandblasting or a chemical method such as etching.

次に、本発明のコンデンサ素子内蔵多層配線基板８の製造方法を添付の図３に基づいて詳細に説明する。図３は、図1のコンデンサ素子内蔵多層配線基板８を製作するための工程毎の断面図である。   Next, the manufacturing method of the multilayer wiring board 8 with a built-in capacitor element according to the present invention will be described in detail with reference to FIG. FIG. 3 is a cross-sectional view for each process for manufacturing the multilayer wiring board 8 with a built-in capacitor element shown in FIG.

まず、図３（ａ）に断面図で示すように、絶縁層１と成る未硬化の前駆体シートを準備し、この前駆体シートにレーザ加工により所望の個所に直径が17〜150μｍ程度の貫通孔11を穿設する。   First, as shown in a sectional view in FIG. 3A, an uncured precursor sheet to be the insulating layer 1 is prepared, and this precursor sheet is penetrated into a desired portion by a diameter of about 17 to 150 μm by laser processing. Hole 11 is drilled.

このような絶縁層１と成る未硬化の前駆体シートは、エポキシ樹脂やビスマレイミドトリアジン樹脂・熱硬化性ポリフェニレンエーテル樹脂・液晶ポリマー樹脂等の有機樹脂材料から成り、機械的強度を向上させるためのシラン系やチタネート系等のカップリング剤、熱安定性を改善するための酸化防止剤や耐光性を改善するための紫外線吸収剤等の光安定剤、難燃性を改善するためのハロゲン系もしくはリン酸系の難燃性剤、アンチモン系化合物やホウ酸亜鉛・メタホウ酸バリウム・酸化ジルコニウム等の難燃助剤、潤滑性を改善するための高級脂肪酸や高級脂肪酸エステル・高級脂肪酸金属塩・フルオロカーボン系界面活性剤等の滑剤、熱膨張係数を調整するためおよび／または機械的強度を向上させるための酸化アルミニウム・酸化珪素・酸化チタン・酸化バリウム・酸化ストロンチウム・酸化ジルコニウム・酸化カルシウム・ゼオライト・窒化珪素・窒化アルミニウム・炭化珪素・ホウ酸アルミニウム・スズ酸バリウム・ジルコン酸バリウム・ジルコン酸ストロンチウム等の充填材、あるいは繊維状ガラスを布状に織り込んだガラスクロス等や耐熱性有機樹脂繊維から成る不織布等の基材を含有させてもよい。   Such an uncured precursor sheet that forms the insulating layer 1 is made of an organic resin material such as an epoxy resin, a bismaleimide triazine resin, a thermosetting polyphenylene ether resin, or a liquid crystal polymer resin, and improves mechanical strength. Silane and titanate coupling agents, antioxidants to improve thermal stability, light stabilizers such as UV absorbers to improve light resistance, halogens to improve flame retardancy or Phosphoric acid flame retardants, antimony compounds, flame retardant aids such as zinc borate, barium metaborate, zirconium oxide, higher fatty acids, higher fatty acid esters, higher fatty acid metal salts, fluorocarbons to improve lubricity Lubricants such as surfactants, aluminum oxide and silicon oxide for adjusting thermal expansion coefficient and / or improving mechanical strength・ Filler or filler such as titanium oxide, barium oxide, strontium oxide, zirconium oxide, calcium oxide, zeolite, silicon nitride, aluminum nitride, silicon carbide, aluminum borate, barium stannate, barium zirconate, strontium zirconate You may contain base materials, such as a glass cloth etc. which woven glass into cloth shape, and the nonwoven fabric which consists of a heat resistant organic resin fiber.

このような前駆体シートは、例えば、絶縁材料として熱硬化性樹脂と無機絶縁粉末との複合材料を用いる場合、以下の方法によって製作される。まず、前述した無機絶縁粉末に熱硬化性樹脂を無機絶縁粉末量が17〜80体積％となるように溶媒とともに加えた混合物を得、この混合物を混練機（ニーダ）や３本ロール等の手段によって混合してペーストを製作する。   Such a precursor sheet is manufactured by the following method when, for example, a composite material of a thermosetting resin and an inorganic insulating powder is used as an insulating material. First, a mixture obtained by adding a thermosetting resin to the inorganic insulating powder described above together with a solvent so that the amount of the inorganic insulating powder is 17 to 80% by volume is obtained, and this mixture is used as a kneader (kneader) or means such as three rolls. To make a paste.

そして、このペーストを圧延法や押し出し法・射出法・ドクターブレード法などのシート成形法を採用してシート状に成形した後、熱硬化性樹脂が完全硬化しない温度に加熱して乾燥することにより絶縁層１となる前駆体シートが製作される。   Then, this paste is formed into a sheet by using a sheet forming method such as a rolling method, an extrusion method, an injection method, or a doctor blade method, and then dried by heating to a temperature at which the thermosetting resin is not completely cured. A precursor sheet to be the insulating layer 1 is manufactured.

なお、ペーストは、好適には、熱硬化性樹脂と無機絶縁粉末の複合材料に、トルエン・酢酸ブチル・メチルエチルケトン・メタノール・メチルセロソルブアセテート・イソプロピルアルコール・メチルイソブチルケトン・ジメチルホルムアミド等の溶媒を添加してなる所定の粘度を有する流動体であり、その粘度は、シート成形法にもよるが100〜3000ポイズが好ましい。   The paste is preferably prepared by adding a solvent such as toluene, butyl acetate, methyl ethyl ketone, methanol, methyl cellosolve acetate, isopropyl alcohol, methyl isobutyl ketone, or dimethylformamide to the composite material of thermosetting resin and inorganic insulating powder. The fluid having a predetermined viscosity is preferably 100 to 3000 poise depending on the sheet molding method.

次に、図３（ｂ）に断面図で示すように、貫通孔11内に銅・銀・金・半田等から成る導電性ペーストを従来周知のスクリーン印刷法等を採用して充填し、貫通導体３を形成する。   Next, as shown in a cross-sectional view in FIG. 3B, the through-hole 11 is filled with a conductive paste made of copper, silver, gold, solder, or the like by using a conventionally known screen printing method or the like. Conductor 3 is formed.

次に、図３（ｃ）に断面図で示すように、前駆体シートの表面と裏面とに被着する配線導体２を準備する。そして、図３（ｄ）に断面図で示すように、配線導体２を前駆体シートの表面および裏面に、必要な配線導体２と貫通導体３とが電気的に接続するように重ね合わせて転写する。   Next, as shown in a cross-sectional view in FIG. 3C, a wiring conductor 2 to be attached to the front and back surfaces of the precursor sheet is prepared. Then, as shown in the cross-sectional view of FIG. 3D, the wiring conductor 2 is superimposed and transferred onto the front and back surfaces of the precursor sheet so that the necessary wiring conductor 2 and the through conductor 3 are electrically connected. To do.

なお、本実施例では、配線導体２の形成を転写法によって行っており、このような配線導体２は、次に述べる方法により形成される。まず、離型シート等の支持体12の表面にめっき法などによって製作され、銅・金・銀・アルミニウム等から選ばれる１種または２種以上の合金からなる厚さ１〜35μｍの電解金属箔を接着し、その表面に所望の配線パターンの鏡像パターンとなるようにレジスト層を形成した後、エッチング・レジスト除去によって所定の配線パターンの鏡像の配線導体２を形成する。   In this embodiment, the wiring conductor 2 is formed by a transfer method. Such a wiring conductor 2 is formed by the method described below. First, an electrolytic metal foil having a thickness of 1 to 35 μm, which is manufactured by plating or the like on the surface of a support 12 such as a release sheet and is made of one or more alloys selected from copper, gold, silver, aluminum and the like. And a resist layer is formed on the surface so as to be a mirror image pattern of a desired wiring pattern, and then a wiring conductor 2 having a mirror image of a predetermined wiring pattern is formed by etching and resist removal.

次に、配線導体２の前駆体シートの表面および裏面への被着は、配線導体２が形成された支持体12を前駆体シートの表面および裏面へ重ね合わせ、しかる後、圧力が0.5〜10ＭＰａ、温度が60〜150℃の条件で加圧加熱した後、支持体12を剥がすことにより、図３（ｅ）に断面図に示すように配線導体２が前駆体シートに被着される。なお、この時、貫通導体３は、完全に硬化していない未硬化状態としておくことが重要である。   Next, the deposition of the wiring conductor 2 on the front and back surfaces of the precursor sheet is performed by superimposing the support 12 on which the wiring conductor 2 is formed on the front and back surfaces of the precursor sheet, and then the pressure is 0.5 to 10 MPa. After pressurizing and heating at a temperature of 60 to 150 ° C., the support 12 is peeled off, so that the wiring conductor 2 is attached to the precursor sheet as shown in the sectional view of FIG. At this time, it is important that the through conductor 3 is in an uncured state that is not completely cured.

また、支持体12としては、ポリエチレンテレフタレートやポリエチレンナフタレート・ポリイミド・ポリフェニレンサルファイド・塩化ビニル・ポリプロピレン等公知のものが使用できる。   As the support 12, known materials such as polyethylene terephthalate, polyethylene naphthalate, polyimide, polyphenylene sulfide, vinyl chloride, and polypropylene can be used.

支持体12の厚みは10〜100μｍが適当であり、望ましくは25〜50μｍが良い。支持体12の厚みが10μｍ未満であると支持体12の変形や折れ曲がりにより形成した配線導体２が断線し易くなり、厚みが100μｍを超えると支持体12の柔軟性がなくなって、前駆体シートからの支持体12の剥離が困難となる傾向がある。また、支持体12表面に電解金属箔を形成するために、アクリル系やゴム系・シリコン系・エポキシ系等公知の接着剤を使用してもよい。   The thickness of the support 12 is suitably 10-100 μm, preferably 25-50 μm. If the thickness of the support 12 is less than 10 μm, the wiring conductor 2 formed by deformation or bending of the support 12 is likely to break, and if the thickness exceeds 100 μm, the flexibility of the support 12 is lost. There is a tendency that peeling of the support 12 becomes difficult. In addition, in order to form the electrolytic metal foil on the surface of the support 12, a known adhesive such as acrylic, rubber, silicon, or epoxy may be used.

そして、図３（ｆ）に断面図で示すように、上記(a)〜(f)の工程を経て製作した複数の前駆体シートと、コンデンサ素子７とを準備し、次に、コンデンサ素子７の引き出し電極部10と貫通導体３および配線導体２との位置合わせを行いコンデンサ素子７を載置するとともに前駆体シートを積層し、温度が150〜300℃、圧力が0.5〜10ＭＰａの条件で30分〜24時間ホットプレスして前駆体シートおよび導電性ペーストを完全硬化させることによって、図３（ｇ）に断面図で示す本発明のコンデンサ素子内蔵多層配線基板８が完成する。   Then, as shown in a cross-sectional view in FIG. 3F, a plurality of precursor sheets manufactured through the steps (a) to (f) and the capacitor element 7 are prepared, and then the capacitor element 7 The lead electrode portion 10 and the through conductor 3 and the wiring conductor 2 are aligned, the capacitor element 7 is placed and a precursor sheet is laminated, and the temperature is 150 to 300 ° C. and the pressure is 0.5 to 10 MPa. The precursor sheet and the conductive paste are completely cured by hot pressing for 24 minutes for 24 minutes, thereby completing the multilayer wiring board 8 with a built-in capacitor element of the present invention shown in a sectional view in FIG.

本発明のコンデンサ素子内蔵多層配線基板８によれば、絶縁層１の少なくとも一層に設けられた空洞部４の内部に、多数の電極層５およびセラミック誘電体層６を交互に積層して成るコンデンサ素子７を内蔵するとともに、空洞部４の底部を絶縁層１に形成された凹部９により構成したことから、コンデンサ素子７を絶縁層１の凹部９に固定することができるため、絶縁層１を積層した際に、絶縁層１同士が界面でずれを生じたとしてもコンデンサ素子７が傾くことはなく、接続信頼性に優れたコンデンサ素子内蔵多層配線基板８とすることができる。   According to the multilayer wiring substrate 8 with a built-in capacitor element of the present invention, a capacitor formed by alternately laminating a large number of electrode layers 5 and ceramic dielectric layers 6 inside the cavity 4 provided in at least one layer of the insulating layer 1. Since the element 7 is built in and the bottom of the cavity 4 is configured by the recess 9 formed in the insulating layer 1, the capacitor element 7 can be fixed to the recess 9 of the insulating layer 1. Even when the insulating layers 1 are displaced at the interface when they are stacked, the capacitor element 7 does not tilt, and the multilayer wiring board 8 with a built-in capacitor element having excellent connection reliability can be obtained.

また、絶縁層１の少なくとも一層に設けられた空洞部４の内部にコンデンサ素子７を挿入するため、コンデンサ素子７を埋設する際に、絶縁層１の樹脂が妨げになることはなく容易に埋設することが可能となり、コンデンサ素子７の位置ずれを生じることがない。さらに、コンデンサ素子７が埋設しやすいように絶縁層１の樹脂粘度を極度に低くする必要もないため、配線導体２や貫通導体３が位置ずれをしてショート不良が発生することのない絶縁信頼性に優れたコンデンサ素子内蔵多層配線基板８とすることができる。   Further, since the capacitor element 7 is inserted into the cavity 4 provided in at least one layer of the insulating layer 1, the resin of the insulating layer 1 is not hindered when embedding the capacitor element 7 and is easily embedded. Therefore, the capacitor element 7 is not displaced. Further, since it is not necessary to extremely reduce the resin viscosity of the insulating layer 1 so that the capacitor element 7 can be embedded easily, the insulation reliability that prevents the wiring conductor 2 and the through conductor 3 from being displaced and causing a short circuit defect. Therefore, the multilayer wiring board 8 with a built-in capacitor element can be obtained.

なお、コンデンサ素子７を設置する空洞部４は、前駆体シートを積層する前に、前駆体シートのコンデンサ素子７が収容される個所にレーザ法やパンチング法により穿設しておけばよい。さらに凹部９も同様に前駆体シートを積層する前に、前駆体シートのコンデンサ素子７が収容される個所にレーザ法により穿設しておけばよい。   Note that the cavity 4 in which the capacitor element 7 is installed may be formed by a laser method or a punching method at a location where the capacitor element 7 of the precursor sheet is accommodated before the precursor sheet is laminated. Further, the concave portion 9 may be similarly drilled by a laser method at a location where the capacitor element 7 of the precursor sheet is accommodated before the precursor sheet is laminated.

また、空洞部４の大きさは、コンデンサ素子７の幅をＬμｍとすると、Ｌ＋３〜Ｌ＋30μｍであり、貫通導体３とコンデンサ素子７との接続における位置精度の観点からはＬ＋30μｍ以下が好ましく、コンデンサ素子７を空洞部４に挿入する際にコンデンサ素子７を挿入し易くするという観点からはＬ＋３μｍ以上が好ましい。   The size of the cavity 4 is L + 3 to L + 30 μm when the width of the capacitor element 7 is L μm. From the viewpoint of positional accuracy in connecting the through conductor 3 and the capacitor element 7, L + 30 μm or less is preferable. From the viewpoint of facilitating insertion of the capacitor element 7 when inserting 7 into the cavity 4, L + 3 μm or more is preferable.

凹部９の大きさは、空洞部４と同様に、Ｌ＋３〜Ｌ＋30μｍで、貫通導体３とコンデンサ素子７との接続における位置精度の観点からはＬ＋30μｍ以下が好ましく、コンデンサ素子７を凹部９に挿入する際にコンデンサ素子７を挿入し易くするという観点からはＬ＋３μｍ以上が好ましい。   The size of the recess 9 is L + 3 to L + 30 μm, similarly to the cavity 4, and is preferably L + 30 μm or less from the viewpoint of positional accuracy in connecting the through conductor 3 and the capacitor element 7. The capacitor element 7 is inserted into the recess 9. From the viewpoint of facilitating insertion of the capacitor element 7 at this time, it is preferably L + 3 μm or more.

また凹部９の深さはコンデンサ素子７の厚みに対して５〜90％であり、コンデンサ素子７を上下の絶縁層１で圧縮して強固に固定するという観点からはコンデンサ素子７の厚みに対して90％以下が好ましく、絶縁層１同士の界面ズレによるコンデンサ素子７の傾斜防止という観点からはコンデンサ素子７の厚みに対して５％以上が好ましい。   The depth of the concave portion 9 is 5 to 90% with respect to the thickness of the capacitor element 7. From the viewpoint of compressing the capacitor element 7 with the upper and lower insulating layers 1 and fixing the capacitor element 7 firmly, the depth of the capacitor element 7 is reduced. 90% or less is preferable, and 5% or more is preferable with respect to the thickness of the capacitor element 7 from the viewpoint of preventing the inclination of the capacitor element 7 due to an interface shift between the insulating layers 1.

かくして、本発明の本発明のコンデンサ素子内蔵多層配線基板によれば、位置精度に優れるとともに接続信頼性・絶縁信頼性に優れた小型で軽量なものとすることができる。   Thus, according to the multilayer wiring board with a built-in capacitor element of the present invention, it is possible to achieve a small size and light weight with excellent positional accuracy and excellent connection reliability and insulation reliability.

なお、本発明のコンデンサ素子内蔵多層配線基板は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上述の実施例では３層の絶縁層を積層することによってコンデンサ素子内蔵多層配線基板を製作したが、４層や５層以上の絶縁層を積層してコンデンサ内蔵多層配線基板を製作してもよい。   The multilayer wiring board with a built-in capacitor element according to the present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present invention. For example, in the above-described embodiments, A multilayer wiring board with a built-in capacitor element is manufactured by laminating three insulating layers, but a multilayer wiring board with a built-in capacitor may be manufactured by stacking four or five or more insulating layers.

また、上述の実施例ではコンデンサ素子を収容する空洞部を１層の絶縁層１に形成したが３層や４層以上にわたって形成したり、あるいは、凹部のみで空洞部を形成しても良い。さらに、コンデンサ素子をより強固に固定するために、凹部の底部に熱硬化性樹脂等の接着剤を用いてコンデンサ素子を接着してもよい。   In the above-described embodiment, the cavity for accommodating the capacitor element is formed in one insulating layer 1, but the cavity may be formed over three layers, four layers or more, or the cavity may be formed only by the recess. Further, in order to more firmly fix the capacitor element, the capacitor element may be bonded to the bottom of the recess using an adhesive such as a thermosetting resin.

本発明のコンデンサ素子内蔵多層配線基板の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the multilayer wiring board with a built-in capacitor | condenser element of this invention. 本発明のコンデンサ素子内蔵多層配線基板に内蔵されるコンデンサ素子の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the capacitor | condenser element incorporated in the multilayer wiring board with a built-in capacitor | condenser element of this invention. （ａ）〜（ｇ）は、それぞれ本発明のコンデンサ素子内蔵多層配線基板の製造方法を説明するための工程毎の断面図である。(A)-(g) is sectional drawing for every process for demonstrating the manufacturing method of the multilayer wiring board with a built-in capacitor element of this invention, respectively.

符号の説明Explanation of symbols

１・・・・・・・・・絶縁層
２・・・・・・・・・配線導体
３・・・・・・・・・貫通導体
４・・・・・・・・・収容部
５・・・・・・・・・電極層
６・・・・・・・・・セラミック誘電体層
７・・・・・・・・・コンデンサ素子
８・・・・・・・・・コンデンサ素子内蔵多層配線基板
９・・・・・・・・・凹部 1... Insulating layer 2... Wiring conductor 3... Through conductor 4. .... Electrode layer 6 ... Ceramic dielectric layer 7 ... Capacitor element 8 ... Multi-layer with built-in capacitor element Wiring board 9 ......... Recess

Claims (2)

上端に幅広部を下端に幅狭部を有する貫通引き出し電極部を備えたコンデンサ素子を、一主面に凹部を有する未硬化の第１樹脂前駆体シート上に、前記コンデンサ素子の下部が前記凹部内に配置され、上部が前記第１樹脂前駆体シートの一主面より上方に位置するように配置させるとともに、前記第１樹脂前駆体シート上に、前記コンデンサ素子の上部を収容するための空洞部を有した未硬化の第２樹脂前駆体シートを、該第２樹脂前駆体シート上に、前記コンデンサ素子の上面を覆い、前記貫通引き出し電極部の幅広部に接続される導体を有する未硬化の第３樹脂前駆体シートをそれぞれ配置させる工程と、
前記第１乃至第３樹脂前駆体シートを硬化させることにより樹脂絶縁層を形成するとともに、これら樹脂絶縁層から成る積層構造体の内部に前記コンデンサ素子を固定する工程と、を含むコンデンサ素子内蔵多層配線基板の製造方法。 A capacitor element having a through lead electrode portion having a wide portion at the upper end and a narrow portion at the lower end is placed on an uncured first resin precursor sheet having a recess on one main surface, and the lower portion of the capacitor element is the recess disposed within, with top be disposed so as to be located above the one main surface of the first resin precursor sheet, the first resin precursor sheet, a cavity for accommodating the upper portion of said capacitor element the second resin precursor sheet uncured having a section, on the second resin precursor sheet to cover the upper surface of the capacitor element, uncured having conductors connected to the wide portion of the through lead electrode portions A step of arranging the third resin precursor sheets of
Forming a resin insulating layer by curing the first to third resin precursor sheets, and fixing the capacitor element inside a laminated structure composed of the resin insulating layers. A method for manufacturing a wiring board. 請求項１に記載のコンデンサ素子内蔵多層配線基板の製造方法により作製されたコンデンサ素子内蔵多層配線基板に、電子素子を搭載する工程を含む電子装置の製造方法。
An electronic device manufacturing method comprising a step of mounting an electronic element on a capacitor element built-in multilayer wiring board manufactured by the method for manufacturing a capacitor element built-in multilayer wiring board according to claim 1.
JP2006333640A 2006-12-11 2006-12-11 Manufacturing method of multilayer wiring board with built-in capacitor element Expired - Fee Related JP4511511B2 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63178374U (en) * 1987-05-11 1988-11-18
JPH05205966A (en) * 1992-01-24 1993-08-13 Murata Mfg Co Ltd Multilayer capacitor
JP2000243873A (en) * 1999-02-22 2000-09-08 Ngk Spark Plug Co Ltd Wiring board, core substrate with built-in capacitor, main body of core substrate, capacitor and their manufacture
JP2001044641A (en) * 1999-07-30 2001-02-16 Kyocera Corp Wiring board incorporating semiconductor element and its manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63178374U (en) * 1987-05-11 1988-11-18
JPH05205966A (en) * 1992-01-24 1993-08-13 Murata Mfg Co Ltd Multilayer capacitor
JP2000243873A (en) * 1999-02-22 2000-09-08 Ngk Spark Plug Co Ltd Wiring board, core substrate with built-in capacitor, main body of core substrate, capacitor and their manufacture
JP2001044641A (en) * 1999-07-30 2001-02-16 Kyocera Corp Wiring board incorporating semiconductor element and its manufacture

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