JP4418764B2 - 樹脂封止型半導体パッケージの製造方法 - Google Patents
樹脂封止型半導体パッケージの製造方法 Download PDFInfo
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- JP4418764B2 JP4418764B2 JP2005048259A JP2005048259A JP4418764B2 JP 4418764 B2 JP4418764 B2 JP 4418764B2 JP 2005048259 A JP2005048259 A JP 2005048259A JP 2005048259 A JP2005048259 A JP 2005048259A JP 4418764 B2 JP4418764 B2 JP 4418764B2
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- resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
前記溶剤可溶性樹脂は、重量分率30〜50%のスチレンブタジエンゴム、アクリル樹脂、ブチラール樹脂、又はエチルセルロースを、トルエン、キシレン、又はメチルエチルケトンに溶かし込んで希釈したものである。本発明のその他の特徴は以下に明らかにする。
以下、本発明の実施の形態1に係る樹脂封止型半導体パッケージの製造方法について図1及び図2を用いて説明する。図1は、各工程における横断面図、図2は各工程におけるアウターリード切断位置における別方向から見た断面図である。
以下、本発明の実施の形態2に係る樹脂封止型半導体パッケージの製造方法について図3及び図4を用いて説明する。図3は、各工程における横断面図、図4は各工程におけるアウターリード切断位置における別方向から見た断面図である。図1又は図2と同様の構成要素には同じ番号を付し、説明を省略する。
図5は、本発明の実施の形態3に係る半導体パッケージの製造方法における封止工程を示す横断面図である。図示のように、片面一括封止に用いるシート状樹脂15aをリードフレーム11上に載置している。封止装置として真空ラミネータまたは真空プレスを用いる。
12 半導体素子
13 ワイヤ
14 溶剤可溶性樹脂
15 封止樹脂
15a シート状樹脂
17,17a めっき皮膜
Claims (4)
- 複数の同一パターンが碁盤目状に形成されたリードフレームの各パターンのダイパッドに半導体素子をダイボンドする工程と、
前記半導体素子の電極パッドと前記リードフレームのインナーリードをワイヤによりワイヤボンドする工程と、
前記リードフレームの隣接するパッケージ間のアウターリード上に溶剤可溶性樹脂を設ける工程と、
前記リードフレーム上に実装された複数の前記半導体素子を封止樹脂で片面一括封止する封止工程と、
前記封止工程の後に前記リードフレームを溶剤に浸漬することで前記溶剤可溶性樹脂を溶解除去する工程と、
各々のパッケージに分離個片化する工程とを有し、
前記溶剤可溶性樹脂は、重量分率30〜50%のスチレンブタジエンゴム、アクリル樹脂、ブチラール樹脂、又はエチルセルロースを、トルエン、キシレン、又はメチルエチルケトンに溶かし込んで希釈したものであることを特徴とする半導体パッケージの製造方法。 - 前記溶剤可溶性樹脂を溶解除去した後に前記アウターリードに外装めっきをする工程を更に有することを特徴とする請求項1に記載の半導体パッケージの製造方法。
- 前記リードフレームに半導体素子をダイボンドする前に、前記リードフレームの少なくともアウターリードとなる領域に外装めっきをする工程を更に有することを特徴とする請求項1に記載の半導体パッケージの製造方法。
- 前記溶剤可溶性樹脂の高さを前記ワイヤの高さよりも高くし、前記片面一括封止にシート状樹脂を用いることを特徴とする請求項1〜3の何れか1項に記載の半導体パッケージの製造方法。
Priority Applications (1)
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JP2005048259A JP4418764B2 (ja) | 2005-02-24 | 2005-02-24 | 樹脂封止型半導体パッケージの製造方法 |
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JP2005048259A JP4418764B2 (ja) | 2005-02-24 | 2005-02-24 | 樹脂封止型半導体パッケージの製造方法 |
Publications (2)
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JP2006237187A JP2006237187A (ja) | 2006-09-07 |
JP4418764B2 true JP4418764B2 (ja) | 2010-02-24 |
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JP2005048259A Expired - Fee Related JP4418764B2 (ja) | 2005-02-24 | 2005-02-24 | 樹脂封止型半導体パッケージの製造方法 |
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Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4367476B2 (ja) * | 2006-10-25 | 2009-11-18 | 株式会社デンソー | モールドパッケージの製造方法 |
JP6030970B2 (ja) * | 2013-02-12 | 2016-11-24 | エスアイアイ・セミコンダクタ株式会社 | 樹脂封止型半導体装置およびその製造方法 |
MY176541A (en) | 2013-11-07 | 2020-08-14 | Agc Inc | Mold release film and process for producing semiconductor package |
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