JP4388895B2 - リコンフィギュアラブルなシーケンサ構造 - Google Patents
リコンフィギュアラブルなシーケンサ構造 Download PDFInfo
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- JP4388895B2 JP4388895B2 JP2004545763A JP2004545763A JP4388895B2 JP 4388895 B2 JP4388895 B2 JP 4388895B2 JP 2004545763 A JP2004545763 A JP 2004545763A JP 2004545763 A JP2004545763 A JP 2004545763A JP 4388895 B2 JP4388895 B2 JP 4388895B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Description
P 44 16 881.0-53, DE 197 81 412.3, DE197 81 483.2, DE 196 54 846.2-53,
DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53,
DE 199 80 312.9, PCT/DE 00/01869, DE 100 36 627.9-33, DE100 28 397.7,
DE 101 10 530.4, DE 101 11 014.6, PCT/DE 00/10516, EP 01 102 674.7,
DE 102 06 856.9, 60/317,876, DE 102 02 044.2, DE 101 29 237.6-53,
DE 101 39 170.6。
OPCODE FETCH、
DATA WRITE INTERN、
DATA WRITE EXTERN、
DATA READ INTERN、
DATA READ EXTERN、
ADRESSPOINTER WRITE INTERN、
ADRESSPOINTER WRITE EXTERN、
ADRESSPOINTER READ INTERN、
ADRESSPOINTER READ EXTERN、
PROGRAMMPOINTER WRITE INTERN、
PROGRAMMPOINTER WRITE EXTERN、
PROGRAMMPOINTER READ INTERN、
PROGRAMMPOINTER READ EXTERN、
STACKPOINTER WRITE INTERN、
STACKPOINTER WRITE EXTERN、
STACKPOINTER READ INTERN、
STACKPOINTER READ EXTERN、
PUSH、
POP、
PROGRAMMPOINTER INCREMENT。
図1は本発明によるセルエレメントフィールドを示し、
図2aはセルエレメントフィールドの詳細を示し、
図2b,cは異なるデータ処理時間にある図2aの詳細を示し、
図3は図2の詳細の代替的な実施形態を示し、
図4は図2の詳細の殊に有利な変形形態を示し、
図5は本発明の機能セル・メモリセル組合せにおける機能折りたたみの例を示し、
図6aは逐次並列的なデータ処理の例を示し、
図6bは本発明の殊に有利な実施例を示し、
図7は機能折りたたみユニットの代替形態を示す。
先ずALU2がコンフィギュレーション情報を従来技術において既に公知であるような中央ロードロジックから受信する。情報伝送をそれ自体公知のやり方でRDY/ACKプロトコルなどを使用して行うことができる。装置の規則通りのコンフィギュレーションを実現するためにロードロジックにFILMOメモリなどが設けられる可能性を言及しておく。
Claims (17)
- 代数的および/または論理的な機能を実施する機能セル手段と、情報を受信、記憶および/または出力するメモリセル手段とを備えたデータ処理のためのセルエレメントフィールドにおいて、
複数の機能セル・メモリセル組合せが前記セルエレメントフィールド内に形成されており、該機能セル・メモリセル組合せはそれぞれ1つの機能セル手段および1つのメモリセル手段を含み、前記機能セル手段および前記メモリセル手段はそれぞれ制御コネクションを介して相互に接続されていることを特徴とする、セルエレメントフィールド。 - 機能および/または配線をリコンフィギュレーション可能および/または予め設定可能である複数のユニット、例えば機能セルおよび/またはメモリセルを備えたプロセッサ、コプロセッサおよび/またはマイクロコントローラを形成する、請求項1記載のセルエレメントフィールド。
- 前記機能セルは算術的な論理ユニットとして形成されている、請求項1または2記載のセルエレメントフィールド。
- 前記算術的な論理ユニットは拡張されたALUとして形成されている、請求項1から3までのいずれか1項記載のセルエレメントフィールド。
- 前記メモリセルはデータを揮発性および/または不揮発性に記憶するよう構成されている、請求項1から4までのいずれか1項記載のセルエレメントフィールド。
- 前記メモリセルは処理すべきデータおよび/または処理すべきプログラムステップを記憶するよう構成されている、請求項1から5までのいずれか1項記載のセルエレメントフィールド。
- 前記メモリセルは該メモリセルを制御する機能セルの制御に基づき、記憶されている情報を前記機能セルに案内されているバスに直接的および/または間接的に供給するよう構成されている、請求項1から6までのいずれか1項記載のセルエレメントフィールド。
- 少なくとも1つのメモリセルおよび/または機能セルにレジスタ、例えばメモリセルと機能セルとの間の情報経路に配置されている逆方向レジスタが配属されている、請求項1から7までのいずれか1項記載のセルエレメントエレメント。
- 前記メモリセルは、該メモリセルを制御する機能セル、入出力セルおよび/または算術的論理ユニットを備えた該メモリセルを制御しないセルからの情報を受信するよう配置されている、請求項1から8までのいずれか1項記載のセルエレメントフィールド。
- 前記機能セル・メモリセル組合せには、外部ユニットおよび/または他の機能セル、機能セル・メモリセル組合せおよび/またはメモリセルに情報を送信する、および/または外部ユニットおよび/または他の機能セル、機能セル・メモリセル組合せおよび/またはメモリセルから情報を受信する、少なくとも1つの入出力手段が配属されている、請求項1から9までのいずれか1項記載のセルエレメントフィールド。
- 前記入出力手段は同様に前記機能セルから制御命令を受信するよう構成されている、請求項1から10までのいずれか1項記載のセルエレメントフィールド。
- 制御部は以下の命令の少なくとも一部、殊に全てを伝送するよう構成されている、および/または前記メモリセルないし入出力セルは以下の命令を復号するよう構成されている:それぞれ例えば内部および/または外部アクセスに関するDATA WRITE/READ、ADRESSPOINTER WRITE/READ、PROGRAMMPOINTER WRITE/READ、PROGRAMMPOINTER INCREMENT、STACKPOINTER WRITE/READならびにPUSH、POP、OPCODE、FETCH、
請求項1から11までのいずれか1項記載のセルエレメントフィールド。 - 前記機能セルはただ1つのマスタとして、制御コネクションおよび/または制御コネクションとして使用されるバス部にアクセス可能である、請求項1から12までのいずれか1項記載のセルエレメントフィールド。
- 前記機能セルはメモリセルおよび入出力セルのうちの少なくとも1つに隣接して配置されている、請求項1から13までのいずれか1項記載のデータ処理のためのセルエレメントフィールド。
- 前記セルエレメントは多次元、例えばマトリクス状に配置されており、前記機能セルおよび/または隣接するメモリセルないし入出力セルは上の列からデータを受信可能であり、下の列にデータを出力可能であり、列内にバスが設けられており、前記機能セルおよび少なくとも1つのメモリセルおよび/または入出力セルは同一の列に存在する、請求項1から14までのいずれか1項記載のセルエレメントフィールド。
- 代数的および/または論理的な機能を実施する機能セルおよび情報供給セル、例えばメモリセルおよび/または情報を受信および/または出力するおよび/または記憶する入出力セルを備えたセルエレメントフィールド、例えば多次元セルエレメントフィールドを動作させる方法において、
それぞれが1つの機能セル手段および1つのメモリセル手段を含む複数の機能セル・メモリセル組合せを前記セルエレメントフィールド内に形成し、前記機能セル手段および前記メモリセル手段をそれぞれ制御コネクションを介して相互に接続し、
少なくとも1つの前記機能セルは制御命令を少なくとも1つの情報供給セルに出力し、該情報供給セルにおいては前記機能セルに対する制御命令情報に応答して処理を行い、
前記機能セルはシーケンサ的にデータを処理するために前記情報供給セルから供給される情報に応答して別のデータ処理を実施するよう構成されていることを特徴とする、セルエレメントフィールドを動作させる方法。 - 前記機能セルは以下の制御命令:
OPCODE FETCH、
DATA WRITE INTERN、
DATA WRITE EXTERN、
DATA READ INTERN、
DATA READ EXTERN、
ADRESSPOINTER WRITE INTERN、
ADRESSPOINTER WRITE EXTERN、
ADRESSPOINTER READ INTERN、
ADRESSPOINTER READ EXTERN、
PROGRAMMPOINTER WRITE INTERN、
PROGRAMMPOINTER WRITE EXTERN、
PROGRAMMPOINTER READ INTERN、
PROGRAMMPOINTER READ EXTERN、
STACKPOINTER WRITE INTERN、
STACKPOINTER WRITE EXTERN、
STACKPOINTER READ INTERN、
STACKPOINTER READ EXTERN、
PUSH、
POP、
PROGRAMMPOINTER INCREMENT
のうちの少なくとも一部を出力し、前記セルエレメントの動作中に前記制御命令の少なくとも一部、殊に全てを必要に応じて出力する、請求項16記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2002141812 DE10241812A1 (de) | 2002-09-06 | 2002-09-06 | Rekonfigurierbare Sequenzerstruktur |
DE10315295 | 2003-04-04 | ||
DE10321834 | 2003-05-15 | ||
EP03019428 | 2003-08-28 | ||
PCT/EP2003/009957 WO2004038599A1 (de) | 2002-09-06 | 2003-09-08 | Rekonfigurierbare sequenzerstruktur |
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JP2006501782A JP2006501782A (ja) | 2006-01-12 |
JP4388895B2 true JP4388895B2 (ja) | 2009-12-24 |
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US (9) | US7394284B2 (ja) |
EP (1) | EP1537486A1 (ja) |
JP (1) | JP4388895B2 (ja) |
AU (1) | AU2003289844A1 (ja) |
WO (1) | WO2004038599A1 (ja) |
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US7782087B2 (en) | 2010-08-24 |
US20180067896A1 (en) | 2018-03-08 |
US7602214B2 (en) | 2009-10-13 |
WO2004038599A1 (de) | 2004-05-06 |
US20080191737A1 (en) | 2008-08-14 |
EP1537486A1 (de) | 2005-06-08 |
US20110006805A1 (en) | 2011-01-13 |
US8310274B2 (en) | 2012-11-13 |
US8803552B2 (en) | 2014-08-12 |
US9817790B2 (en) | 2017-11-14 |
US20130024657A1 (en) | 2013-01-24 |
US20060192586A1 (en) | 2006-08-31 |
JP2006501782A (ja) | 2006-01-12 |
US20110148460A1 (en) | 2011-06-23 |
US20140351482A1 (en) | 2014-11-27 |
US7928763B2 (en) | 2011-04-19 |
US20100039139A1 (en) | 2010-02-18 |
US7394284B2 (en) | 2008-07-01 |
US20160170925A1 (en) | 2016-06-16 |
AU2003289844A1 (en) | 2004-05-13 |
US10296488B2 (en) | 2019-05-21 |
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