JP4372136B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4372136B2 JP4372136B2 JP2006269370A JP2006269370A JP4372136B2 JP 4372136 B2 JP4372136 B2 JP 4372136B2 JP 2006269370 A JP2006269370 A JP 2006269370A JP 2006269370 A JP2006269370 A JP 2006269370A JP 4372136 B2 JP4372136 B2 JP 4372136B2
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- electrode
- semiconductor substrate
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01016—Sulfur [S]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01025—Manganese [Mn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01038—Strontium [Sr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
日経エレクトロニクス2005年10月10日号「Si貫通チップの構造革命」、81〜99頁(日経BP社)
図1及び図2は、本発明の第1の実施形態に係る半導体装置接続電極の製造工程を示す模式図である。先ず,通常のシリコンプロセスで集積回路が形成された、厚さ100μmの第1のダイ1を作成した後、ドライエッチングと気相成長法で直径50μmの貫通孔を形成する。この貫通孔の内部を埋めるようにCuメッキなどで貫通電極3を作成する。貫通電極表面には、電離し易いCuまたはAg等の金属薄膜層4(図1には不図示)を0.05μm、スパッタ法で作成しておく。次に、よく知られたダイシング方法で、ダイを切り出す(図1(a))。
上記のように、第1の実施形態によれば、貫通電極間をセルフアラインで接続するので、従来のダイ積層型半導体装置よりも、高密度の垂直方向電極を形成することができる。
第2の実施形態に係る半導体装置の製造工程は、第1の実施形態と類似しているので、図1〜図3を参照して説明する。
固体電解質以外に、所望の電圧を印加することで、低抵抗の導電パスを形成する薄膜材料がある。従来不揮発性メモリ用途に検討されているものである。第3の実施形態は、これを第1及び第2の実施形態に記載した固体電解質層5の代わりに用いたものである。
(2)遷移金属酸化物(NiO,SrTiO,PrCaMnOなど):膜の上下に電圧を印加することで、初期状態の絶縁体相を電気的に相転位させて、金属相(低抵抗層)に変えることができる。
第1〜第3の実施形態の半導体装置の製造方法では、全ての貫通電極3が同時にオンしないことが問題となる可能性がある。即ち、図1のように表面電極9を用いた場合は、1つの貫通電極3がオン状態になると、それ以降他の貫通電極3の両端に電圧が加わらない。これを解決する方法を第4の実施形態で説明する。
3…貫通電極
4…銀薄膜層
5…固体電界層、GeSbTe層、遷移金属酸化膜層
7…第2のダイ
9、9a〜9h…表面電極
11…裏面電極
13…導通路
15…ヒューズ
101…Siダイ
102…貫通電極(ビア)
103…Siウェハ
104…絶縁膜
105…内部配線
Claims (11)
- 第1の集積回路が形成され複数の第1の貫通電極を含む第1の半導体基板と、第2の集積回路が形成され複数の第2の貫通電極を含む第2の半導体基板とを準備する工程と、
前記第1の半導体基板上に固体電解質層を形成する工程と、
前記固体電界質層の上に、前記第2の半導体基板を載置する工程と、
前記複数の第1の貫通電極と前記複数の第2の貫通電極の間に電圧を印加し、前記固体電解質層中に、前記複数の第1の貫通電極と夫々に対応して近接する前記複数の第2の貫通電極を接続する複数の接続電極を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記電解質層は、CuS若しくはZnCdSを含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記貫通電極はCuまたはAgのいずれかの金属で被覆され、前記接続電極は前記金属を含むことを特徴とする請求項2に記載の半導体装置の製造方法。
- 第1の集積回路が形成され複数の第1の貫通電極を含む第1の半導体基板と、第2の集積回路が形成され複数の第2の貫通電極を含む第2の半導体基板とを準備する工程と、
前記第1の半導体基板上にGeSbTe層を形成する工程と、
前記GeSbTe層の上に、前記第2の半導体基板を載置する工程と、
前記複数の第1の貫通電極と前記複数の第2の貫通電極の間に電圧を印加し、前記GeSbTe層中に、前記複数の第1の貫通電極と夫々に対応して近接する前記複数の第2の貫通電極を接続する複数の接続電極を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記GeSbTe層はアモルファス相であり、前記複数の接続電極はGeSbTe多結晶層を含むことを特徴とする請求項4に記載の半導体装置の製造方法。
- 第1の集積回路が形成され複数の第1の貫通電極を含む第1の半導体基板と、第2の集積回路が形成され複数の第2の貫通電極を含む第2の半導体基板とを準備する工程と、
前記第1の半導体基板上に遷移金属酸化物層を形成する工程と、
前記遷移金属酸化物層の上に、前記第2の半導体基板を載置する工程と、
前記複数の第1の貫通電極と前記複数の第2の貫通電極の間に電圧を印加し、前記遷移金属酸化物層中に、前記複数の第1の貫通電極と夫々に対応して近接する前記複数の第2の貫通電極を接続する複数の接続電極を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記遷移金属酸化物層は、NiO,SrTiO,PrCaMnOのいずれかを含む絶縁層であることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記複数の接続電極は、NiO,SrTiO,PrCaMnOのいずれかを含む低抵抗層を含むことを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記貫通電極はAgまたはNiのいずれかの金属で被覆され、前記接続電極は前記金属を含むことを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記第2の半導体基板の上面に、前記第2の貫通電極と接続する表面電極を形成する工程と、
前記第1の半導体基板の裏面に、前記第1の貫通電極と接続する裏面電極を形成する工程と、
を更に具備し、前記複数の接続電極を形成する工程は、前記表面電極と前記裏面電極の間に電圧を印加することを特徴とする請求項1、4、6のいずれかに記載の半導体装置の製造方法。 - 前記表面電極は前記複数の貫通電極の各々との間に形成されたヒューズを含み、前記表面電極と前記裏面電極の間に電圧を印加する工程において、電流の流れた前記ヒューズは溶断し、前記複数の貫通電極の全てに電流が流れることを特徴とする請求項10に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006269370A JP4372136B2 (ja) | 2006-09-29 | 2006-09-29 | 半導体装置の製造方法 |
CNA2007101534947A CN101154605A (zh) | 2006-09-29 | 2007-09-20 | 半导体器件的制造方法 |
US11/860,102 US7772035B2 (en) | 2006-09-29 | 2007-09-24 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006269370A JP4372136B2 (ja) | 2006-09-29 | 2006-09-29 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008091538A JP2008091538A (ja) | 2008-04-17 |
JP4372136B2 true JP4372136B2 (ja) | 2009-11-25 |
Family
ID=39256162
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006269370A Expired - Fee Related JP4372136B2 (ja) | 2006-09-29 | 2006-09-29 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7772035B2 (ja) |
JP (1) | JP4372136B2 (ja) |
CN (1) | CN101154605A (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5305806B2 (ja) * | 2008-09-25 | 2013-10-02 | 株式会社東芝 | 3次元集積回路の設計方法及び3次元集積回路の設計プログラム |
JP5278747B2 (ja) * | 2009-02-24 | 2013-09-04 | ソーバス株式会社 | 積層チップ |
KR101819825B1 (ko) * | 2016-06-13 | 2018-01-18 | 아주대학교산학협력단 | 플렉시블 전극 제조방법 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040004262A1 (en) * | 1994-05-31 | 2004-01-08 | Welch James D. | Semiconductor devices in compensated semiconductor |
US6387771B1 (en) * | 1999-06-08 | 2002-05-14 | Infineon Technologies Ag | Low temperature oxidation of conductive layers for semiconductor fabrication |
US7342762B2 (en) * | 2005-11-10 | 2008-03-11 | Littelfuse, Inc. | Resettable circuit protection apparatus |
-
2006
- 2006-09-29 JP JP2006269370A patent/JP4372136B2/ja not_active Expired - Fee Related
-
2007
- 2007-09-20 CN CNA2007101534947A patent/CN101154605A/zh active Pending
- 2007-09-24 US US11/860,102 patent/US7772035B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008091538A (ja) | 2008-04-17 |
US7772035B2 (en) | 2010-08-10 |
CN101154605A (zh) | 2008-04-02 |
US20080241996A1 (en) | 2008-10-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI694597B (zh) | 使用虛設接合接觸和虛設互連的混合接合 | |
CN102272916B (zh) | 具有熔丝型硅通孔的3d芯片叠层 | |
CN111446207B (zh) | 形成三维集成布线结构的方法及其半导体结构 | |
JP2023164841A (ja) | 3次元メモリデバイスのハイブリッドボンディングコンタクト構造 | |
US9659819B2 (en) | Interconnects for stacked non-volatile memory device and method | |
TWI231592B (en) | Semiconductor device, three-dimensionally mounted semiconductor device, and method of manufacturing semiconductor device | |
TWI293473B (en) | Method for manufacturing semiconductor device | |
CN109417075A (zh) | 多堆叠层三维存储器件 | |
KR20210062083A (ko) | 관통 계단 콘택트를 갖는 3 차원 메모리 장치 및 장치 형성 방법 | |
CN102918647B (zh) | 非易失性存储装置及其制造方法 | |
CN109643643B (zh) | 键合存储器件及其制造方法 | |
CN109964313A (zh) | 具有由不扩散导电材料制成的键合触点的键合半导体结构及其形成方法 | |
US20100182040A1 (en) | Programmable through silicon via | |
TW200539242A (en) | Semiconductor device and semiconductor system | |
US7579616B2 (en) | Four-terminal programmable via-containing structure and method of fabricating same | |
KR20180082709A (ko) | 반도체 장치 및 이의 제조 방법 | |
TW201010005A (en) | Hybrid conductive vias including small dimension active surface ends and larger dimension back side ends, semiconductor devices including the same, and associated methods | |
CN110088889B (zh) | 用于形成三维综合布线结构和其半导体结构的方法 | |
CN108417550A (zh) | 半导体装置及其制造方法 | |
JP4372136B2 (ja) | 半導体装置の製造方法 | |
TW200921815A (en) | Semiconductor chip device having through-silicon-holes (TSV) and its fabricating method | |
CN109887937A (zh) | 形成再分布线的方法及用该方法制造半导体器件的方法 | |
US20230005869A1 (en) | Micro bump, method for forming micro bump, chip interconnection structure and chip interconnection method | |
US20240172571A1 (en) | Semiconductor device and method of fabricating the same | |
JP2011171391A (ja) | アンチヒューズ構造およびアンチヒューズ構造の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080327 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080908 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080916 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081029 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090804 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090901 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120911 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120911 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120911 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130911 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |