JP4333370B2 - データ処理システム - Google Patents
データ処理システム Download PDFInfo
- Publication number
- JP4333370B2 JP4333370B2 JP2004002577A JP2004002577A JP4333370B2 JP 4333370 B2 JP4333370 B2 JP 4333370B2 JP 2004002577 A JP2004002577 A JP 2004002577A JP 2004002577 A JP2004002577 A JP 2004002577A JP 4333370 B2 JP4333370 B2 JP 4333370B2
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- JP
- Japan
- Prior art keywords
- data
- channel device
- control
- channel
- lpar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000005540 biological transmission Effects 0.000 claims description 9
- 239000000872 buffer Substances 0.000 description 62
- 102000004137 Lysophosphatidic Acid Receptors Human genes 0.000 description 50
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- 239000000835 fiber Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 18
- 230000008569 process Effects 0.000 description 16
- 230000006870 function Effects 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 3
- 101000966782 Homo sapiens Lysophosphatidic acid receptor 1 Proteins 0.000 description 2
- 101001038001 Homo sapiens Lysophosphatidic acid receptor 2 Proteins 0.000 description 2
- 102100040607 Lysophosphatidic acid receptor 1 Human genes 0.000 description 2
- 102100040387 Lysophosphatidic acid receptor 2 Human genes 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 238000005192 partition Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- -1 similarly Proteins 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer And Data Communications (AREA)
- Information Transfer Systems (AREA)
Description
LPAR番号とチャネル装置の対応付けを行う時、LPAR番号をポート単位に対応付けを行う。例えば、LPAR#1をポート1に対応させ、LPAR#2をポート2に対応させるように設定する。該設定情報から、LPAR制御プログラム609は、チャネル制御レジスタ1をLPAR#1に割り当て、チャネル制御レジスタ2をLPAR#2に割り当てる。その他の処理は図1で述べたものと同じである。以上より、多ポートのチャネル装置においても複数のOSから共用が可能である。
101、102 データ転送用バッファ
103、104 データ処理システム上のLPAR#1及びLPAR#2
105 メモリアクセス制御回路
106 入出力処理制御手段
107 フレームの送受信を行うリンク
108 受信バッファ
109 LPAR制御プログラム
110 チャネル制御レジスタ
200 主記憶(MS)
201 チャネル装置のポート
202 ケーブル
203 メモリアクセス制御チップ
204、205 プロセッサ
206 チャネル装置
207 ハブ(Hub)
208 I/Oデバイス
300 チャネル制御レジスタ
301 PCIコンフィギュレーションレジスタ
302 WWPN#レジスタ
303 I/O処理ベースアドレスレジスタ
304 I/O処理イネーブルレジスタ
500 データ領域を示すアドレスを含むDA_AD
501 SCSIコマンドを含む領域
502 SCSIコマンドに対する応答フレームストア領域
503 データバッファアドレス領域を示すアドレスを含むBU_AD
504 データバッファアドレス領域の有効性等の情報を含むFLAG
505 SCSIコマンド領域のアドレスDB_AD0
506 データバッファ領域のアドレスDB_AD1
507 データバッファ領域
600 チャネル装置
601、602 データ転送用バッファ
603、604 データ処理システム上のLPAR#1及びLPAR#2
605 メモリアクセス制御回路
606 入出力処理制御手段
607、608 フレームの送受信を行うリンク
609 LPAR制御プログラム
610 チャネル制御レジスタ
611、612 フレームの送受信を行うポート1及びポート2
Claims (2)
- 中央処理装置上で制御プログラムが動作し、該制御プログラムの制御下で複数のオペレーティングシステム(OS)の動作が可能であり、I/Oデバイスとの間で前記I/Oデバイスのポートを介して1つのポートでデータを送受信するチャネル装置を具備したデータ処理システムにおいて、前記チャネル装置はデータの送受信を行うための媒体であることを示すためのチャネル装置識別子(以下、IDと呼ぶ。)を複数個備え、前記制御プログラムは前記複数のIDの各々に対して前記システム上の各OSを1個ずつそれぞれに割り当てる手段を備え、各OSから起動される入出力処理に対して各OSのデータには各OSに割り当てられたIDを付し前記各OSに割り当てられたID毎に独立してデータの送受信制御を行う入出力処理制御手段を前記チャネル装置に備え、前記入出力処理制御手段は前記データの送受信制御を複数のOSに対して行うことを特徴とするデータ処理システム。
- 前記チャネル装置は前記システム上の各OSが該チャネル装置を制御するための制御レジスタを複数備え、前記制御プログラムは前記制御レジスタの各々に対して前記システム上の各OSを1個ずつそれぞれに割り当てる手段を備え、前記制御レジスタの各々を前記割り当てられたOSに制御させることを特徴とする請求項1記載のデータ処理システム。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004002577A JP4333370B2 (ja) | 2004-01-08 | 2004-01-08 | データ処理システム |
US11/025,916 US7610581B2 (en) | 2004-01-08 | 2005-01-03 | Data processing system |
US12/562,562 US8607214B2 (en) | 2004-01-08 | 2009-09-18 | Data processing system running on a plurality of operating systems (OS) and enabling a channel device to simultaneously perform processing associated with the plurality of operating systems |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004002577A JP4333370B2 (ja) | 2004-01-08 | 2004-01-08 | データ処理システム |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008104229A Division JP4623126B2 (ja) | 2008-04-14 | 2008-04-14 | データ処理システム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005196509A JP2005196509A (ja) | 2005-07-21 |
JP4333370B2 true JP4333370B2 (ja) | 2009-09-16 |
Family
ID=34817729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004002577A Expired - Lifetime JP4333370B2 (ja) | 2004-01-08 | 2004-01-08 | データ処理システム |
Country Status (2)
Country | Link |
---|---|
US (2) | US7610581B2 (ja) |
JP (1) | JP4333370B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7480742B2 (en) * | 2005-02-25 | 2009-01-20 | International Business Machines Corporation | Method for virtual adapter destruction on a physical adapter that supports virtual adapters |
US7644219B2 (en) * | 2005-06-30 | 2010-01-05 | Dell Products L.P. | System and method for managing the sharing of PCI devices across multiple host operating systems |
US7562163B2 (en) * | 2006-08-18 | 2009-07-14 | International Business Machines Corporation | Apparatus and method to locate a storage device disposed in a data storage system |
JP4996929B2 (ja) * | 2007-01-17 | 2012-08-08 | 株式会社日立製作所 | 仮想計算機システム |
US7853757B2 (en) * | 2007-08-13 | 2010-12-14 | International Business Machines Corporation | Avoiding failure of an initial program load in a logical partition of a data storage system |
US7853758B2 (en) * | 2007-08-13 | 2010-12-14 | International Business Machines Corporation | Avoiding failure of an initial program load in a logical partition of a data storage system |
US8767597B2 (en) * | 2011-11-18 | 2014-07-01 | The University Of Tokyo | Wireless communication apparatus |
JP5847013B2 (ja) * | 2012-05-10 | 2016-01-20 | 株式会社日立製作所 | 計算機及び計算機における入出力制御方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3302177A (en) * | 1963-09-26 | 1967-01-31 | Sperry Rand Corp | Data processing system |
JPS6013501B2 (ja) * | 1978-09-18 | 1985-04-08 | 富士通株式会社 | 仮想計算機システムにおけるチヤネルアドレス制御方式 |
US4396984A (en) * | 1981-03-06 | 1983-08-02 | International Business Machines Corporation | Peripheral systems employing multipathing, path and access grouping |
US4403288A (en) * | 1981-09-28 | 1983-09-06 | International Business Machines Corporation | Methods and apparatus for resetting peripheral devices addressable as a plurality of logical devices |
JP3337508B2 (ja) | 1993-01-20 | 2002-10-21 | 富士通株式会社 | 単一cpuによる疑似複数ホストテスト方法 |
US5894583A (en) * | 1996-04-09 | 1999-04-13 | International Business Machines Corporation | Variable timeout method for improving missing-interrupt-handler operations in an environment having I/O devices shared by one or more systems |
US6014383A (en) * | 1997-02-10 | 2000-01-11 | Compaq Computer Corporation | System and method for controlling multiple initiators in a fibre channel environment |
US5954796A (en) * | 1997-02-11 | 1999-09-21 | Compaq Computer Corporation | System and method for automatically and dynamically changing an address associated with a device disposed in a fire channel environment |
US6453392B1 (en) * | 1998-11-10 | 2002-09-17 | International Business Machines Corporation | Method of and apparatus for sharing dedicated devices between virtual machine guests |
US6343324B1 (en) * | 1999-09-13 | 2002-01-29 | International Business Machines Corporation | Method and system for controlling access share storage devices in a network environment by configuring host-to-volume mapping data structures in the controller memory for granting and denying access to the devices |
JP4087072B2 (ja) | 2001-01-25 | 2008-05-14 | 株式会社日立製作所 | ストレージシステム及び仮想プライベートボリューム制御方法 |
JP2004192105A (ja) * | 2002-12-09 | 2004-07-08 | Hitachi Ltd | 記憶装置の接続装置およびそれを含むコンピュータシステム |
US7617333B2 (en) * | 2003-01-21 | 2009-11-10 | Nextio Inc. | Fibre channel controller shareable by a plurality of operating system domains within a load-store architecture |
US7512717B2 (en) * | 2003-01-21 | 2009-03-31 | Nextio Inc. | Fibre channel controller shareable by a plurality of operating system domains within a load-store architecture |
US7493416B2 (en) * | 2003-01-21 | 2009-02-17 | Nextio Inc. | Fibre channel controller shareable by a plurality of operating system domains within a load-store architecture |
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2004
- 2004-01-08 JP JP2004002577A patent/JP4333370B2/ja not_active Expired - Lifetime
-
2005
- 2005-01-03 US US11/025,916 patent/US7610581B2/en not_active Expired - Fee Related
-
2009
- 2009-09-18 US US12/562,562 patent/US8607214B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8607214B2 (en) | 2013-12-10 |
US20050177648A1 (en) | 2005-08-11 |
JP2005196509A (ja) | 2005-07-21 |
US20100011349A1 (en) | 2010-01-14 |
US7610581B2 (en) | 2009-10-27 |
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