JP4328791B2 - 被測定素子の特性測定方法及び半導体装置の特性管理システム - Google Patents
被測定素子の特性測定方法及び半導体装置の特性管理システム Download PDFInfo
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- JP4328791B2 JP4328791B2 JP2006253941A JP2006253941A JP4328791B2 JP 4328791 B2 JP4328791 B2 JP 4328791B2 JP 2006253941 A JP2006253941 A JP 2006253941A JP 2006253941 A JP2006253941 A JP 2006253941A JP 4328791 B2 JP4328791 B2 JP 4328791B2
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- 238000012360 testing method Methods 0.000 title claims description 54
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000000034 method Methods 0.000 title claims description 19
- 238000005259 measurement Methods 0.000 claims description 29
- 238000000691 measurement method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 235000012489 doughnuts Nutrition 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
11 しきい値が高い領域
12 しきい値が低い領域
100,200 半導体装置
110 主回路部
120 テスト部
121a,122a・・・ 通電素子
121b,122b・・・ 被測定素子
130 制御部
130a 切り替え信号
190 テスタ
191 プローブ
192 測定部
193 ID取得部
199 データベース
210 スイッチ
Claims (6)
- 半導体装置に設けられた被測定素子の特性測定方法であって、前記半導体装置に含まれる主回路部の消費電力が実質的にゼロ又はほぼ一定となるようモード設定する第1のステップと、前記被測定素子に通電させた状態で前記半導体装置に流れる電源電流を計測する第2のステップとを備え、
前記第1のステップは、前記半導体装置に対してコマンド信号を発行することによって前記主回路部をスタンバイ状態とすることにより行い、
前記第1のステップを行った後、前記第2のステップを行う前に、前記被測定素子に通電させない状態で前記半導体装置に流れる初期電流を計測することを特徴とする被測定素子の特性測定方法。 - 前記第2のステップにて計測された電源電流と、前記初期電流との差を算出する第3のステップをさらに備えることを特徴とする請求項1に記載の被測定素子の特性測定方法。
- 前記第2のステップは、複数の被測定素子を順次通電させながら電源電流を計測することにより行うことを特徴とする請求項1又は2に記載の被測定素子の特性測定方法。
- 少なくとも前記第2のステップにて計測された電源電流に基づいて、前記被測定素子のしきい値電圧を算出することを特徴とする請求項1乃至3のいずれか一項に記載の被測定素子の特性測定方法。
- 請求項1乃至4のいずれか一項に記載の被測定素子の特性測定方法を実行するための手段と、当該半導体装置のIDを取得するための手段と、取得したIDと当該半導体装置に対応する計測結果とを関連づけて記憶する手段とを備えることを特徴とする半導体装置の特性管理システム。
- 前記IDには、当該半導体装置のウェハ上における位置に関する情報を含んでいることを特徴とする請求項5に記載の半導体装置の特性管理システム。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006253941A JP4328791B2 (ja) | 2006-09-20 | 2006-09-20 | 被測定素子の特性測定方法及び半導体装置の特性管理システム |
US11/898,551 US7751998B2 (en) | 2006-09-20 | 2007-09-13 | Semiconductor device, method for measuring characteristics of element to be measured, and characteristic management system of semiconductor device |
Applications Claiming Priority (1)
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JP2006253941A JP4328791B2 (ja) | 2006-09-20 | 2006-09-20 | 被測定素子の特性測定方法及び半導体装置の特性管理システム |
Publications (2)
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JP2008078266A JP2008078266A (ja) | 2008-04-03 |
JP4328791B2 true JP4328791B2 (ja) | 2009-09-09 |
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US (1) | US7751998B2 (ja) |
JP (1) | JP4328791B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8174467B2 (en) | 2000-06-27 | 2012-05-08 | Hitachi Displays, Ltd. | Picture image display device and method of driving the same |
US8537081B2 (en) | 2003-09-17 | 2013-09-17 | Hitachi Displays, Ltd. | Display apparatus and display control method |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101171255B1 (ko) | 2010-12-01 | 2012-08-06 | 에스케이하이닉스 주식회사 | 반도체 집적 회로 설계 시스템 및 방법, 이를 위한 컴퓨터로 읽을 수 있는 기록 매체 |
WO2013023941A1 (en) * | 2011-08-17 | 2013-02-21 | Abb Research Ltd | Method and device for detecting a failure of electronic units in printed circuit board assemblies |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3526485A1 (de) * | 1985-07-24 | 1987-02-05 | Heinz Krug | Schaltungsanordnung zum pruefen integrierter schaltungseinheiten |
JPH02116140A (ja) | 1988-10-26 | 1990-04-27 | Fujitsu Ltd | 半導体装置 |
US5053700A (en) * | 1989-02-14 | 1991-10-01 | Amber Engineering, Inc. | Method for wafer scale testing of redundant integrated circuit dies |
JP3156397B2 (ja) | 1992-10-30 | 2001-04-16 | 日本電気株式会社 | 半導体装置 |
JP3614546B2 (ja) | 1995-12-27 | 2005-01-26 | 富士通株式会社 | 半導体集積回路 |
JP2991994B2 (ja) | 1996-07-05 | 1999-12-20 | 松下電器産業株式会社 | 半導体回路システム,半導体集積回路の検査方法及びその検査系列の生成方法 |
JPH11340806A (ja) | 1998-05-25 | 1999-12-10 | Hitachi Ltd | 半導体集積回路装置 |
JP3098499B2 (ja) | 1998-10-19 | 2000-10-16 | 山口日本電気株式会社 | 半導体装置および半導体装置への製造情報記録方法 |
US6492831B2 (en) * | 1998-12-02 | 2002-12-10 | Advantest Corporation | Current measuring method and current measuring apparatus |
JP3277914B2 (ja) | 1999-04-30 | 2002-04-22 | 日本電気株式会社 | プロセスパラメータ測定回路を有する集積回路装置 |
JP2002040090A (ja) * | 2000-07-26 | 2002-02-06 | Ando Electric Co Ltd | 半導体試験装置 |
JP2003043099A (ja) | 2001-08-02 | 2003-02-13 | Sony Corp | 半導体試験方法および半導体装置 |
KR100466984B1 (ko) * | 2002-05-15 | 2005-01-24 | 삼성전자주식회사 | 테스트 소자 그룹 회로를 포함하는 집적 회로 칩 및 그것의 테스트 방법 |
JP4346373B2 (ja) | 2002-10-31 | 2009-10-21 | 株式会社ルネサステクノロジ | 半導体装置 |
US7123040B2 (en) * | 2004-03-04 | 2006-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for check-in control in wafer testing |
JP4599146B2 (ja) * | 2004-11-30 | 2010-12-15 | 株式会社アドバンテスト | 試験装置、及び電源回路 |
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2006
- 2006-09-20 JP JP2006253941A patent/JP4328791B2/ja active Active
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8174467B2 (en) | 2000-06-27 | 2012-05-08 | Hitachi Displays, Ltd. | Picture image display device and method of driving the same |
US8537081B2 (en) | 2003-09-17 | 2013-09-17 | Hitachi Displays, Ltd. | Display apparatus and display control method |
Also Published As
Publication number | Publication date |
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JP2008078266A (ja) | 2008-04-03 |
US20080068037A1 (en) | 2008-03-20 |
US7751998B2 (en) | 2010-07-06 |
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