JP4327144B2 - Pll回路におけるアクティブフィルタ。 - Google Patents
Pll回路におけるアクティブフィルタ。 Download PDFInfo
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- JP4327144B2 JP4327144B2 JP2005289043A JP2005289043A JP4327144B2 JP 4327144 B2 JP4327144 B2 JP 4327144B2 JP 2005289043 A JP2005289043 A JP 2005289043A JP 2005289043 A JP2005289043 A JP 2005289043A JP 4327144 B2 JP4327144 B2 JP 4327144B2
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- Prior art keywords
- charge pump
- circuit
- filter
- voltage
- output
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- 239000003990 capacitor Substances 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 238000004891 communication Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Networks Using Active Elements (AREA)
Description
発明の実施の形態においては、位相比較器の後段側に、3つ以上のチャージポンプ回路を備え、3つ以上のチャージポンプ回路のうちの2つを前述の第1のチャージポンプ回路と第2のチャージポンプ回路として用いることによって、2つのチャージポンプ回路の出力する電流の比を変化可能とするアクティブフィルタを実現することもできる。
図7は、このループ帯域角周波数ωPの説明図である。一般にPLL回路のノイズ特性測定時には、スペクトラムアナライザなどによって図7内のスペクトラム波形が測定されるが、ループ帯域角周波数ωPはこのスペクトラム波形が急激に低下し始めるところで、
従って、静電容量C1は、ループ帯域角周波数ωPを用いて次式によって与えられる。
R2=α(T2−T1)/C1、C2=T1/R2
によって計算することができる。アディショナルフィルタを構成する抵抗R333と静電容量C334の値については、従来例の図10におけると同様に計算することができるが、これらの値は本発明と直接の関連はないため、その説明を省略する。
2 第1のチャージポンプ回路
3 第2のチャージポンプ回路
4 第1の回路要素
5 第2の回路要素
6 電圧加算器
10、11 分周器
12 位相比較器
13 チャージポンプ回路
14 ローパスフィルタ(LPF)
15 電圧制御発振器(VCO)
17 P型MOSトランジスタ
18 N型MOSトランジスタ
32 ボルテージアダー
Claims (4)
- 2つのチャージポンプ回路からの出力を受けるフィルタであって、
前記2つのチャージポンプ回路のうちの一方のチャージポンプ回路の出力とアースとの間に接続される第1の回路要素と、
他方のチャージポンプ回路の出力とアースとの間に接続される第2の回路要素と、
該第1の回路要素の両端の電圧と、第2の回路要素の両端の電圧とを加算する電圧加算器と、を備えるアクティブフィルタの後段に、
前記電圧加算器の出力端子に一方の端子が接続される抵抗と、
該抵抗の他方の端子とアースとの間に接続される容量とを備え、
該容量の両端の電圧を出力電圧とするアディショナルフィルタを接続され、
前記フィルタが、3つ以上のチャージポンプ回路のうちで、前記一方のチャージポンプ回路が出力する電流に対する出力電流の電流比が互いに異なる複数のチャージポンプ回路から選択されたチャージポンプ回路を前記他方のチャージポンプ回路として、前記一方のチャージポンプ回路および前記他方のチャージポンプ回路の2つのチャージポンプ回路からの出力を受けることを特徴とするアクティブフィルタ。 - 請求項1記載のアクティブフィルタを備えることを特徴とするPLL回路。
- 2つのチャージポンプ回路からの出力を受けるフィルタであって、
前記2つのチャージポンプ回路のうちの一方のチャージポンプ回路の出力とアースとの間に接続される第1の回路要素と、
他方のチャージポンプ回路の出力とアースとの間に接続される第2の回路要素と、
該第1の回路要素の両端の電圧と、第2の回路要素の両端の電圧とを加算する電圧加算器と、を備えるアクティブフィルタの後段に、
前記電圧加算器の出力端子に一方の端子が接続される抵抗と、
該抵抗の他方の端子とアースとの間に接続される容量とを備え、
該容量の両端の電圧を出力電圧とするアディショナルフィルタを接続され、
前記フィルタがPLL回路内で用いられるとともに、
前記2つのチャージポンプ回路は、前記PLL回路内の位相比較器の位相比較結果であって前記第1、第2の回路要素側に電流を流すことを示す第1位相比較結果が共通に入力された場合に、前記第1位相比較結果に対応した期間、それぞれ前記第1、第2の回路要素側に電流を流すことを特徴とするアクティブフィルタ。 - 請求項1または3記載のアクティブフィルタと他の回路とがワンチップ上に形成されていることを特徴とする半導体集積回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005289043A JP4327144B2 (ja) | 2005-09-30 | 2005-09-30 | Pll回路におけるアクティブフィルタ。 |
US11/318,608 US7782144B2 (en) | 2005-09-30 | 2005-12-28 | Active filter in PLL circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005289043A JP4327144B2 (ja) | 2005-09-30 | 2005-09-30 | Pll回路におけるアクティブフィルタ。 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007104132A JP2007104132A (ja) | 2007-04-19 |
JP2007104132A5 JP2007104132A5 (ja) | 2007-07-12 |
JP4327144B2 true JP4327144B2 (ja) | 2009-09-09 |
Family
ID=37901323
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005289043A Expired - Fee Related JP4327144B2 (ja) | 2005-09-30 | 2005-09-30 | Pll回路におけるアクティブフィルタ。 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7782144B2 (ja) |
JP (1) | JP4327144B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010252094A (ja) * | 2009-04-16 | 2010-11-04 | Renesas Electronics Corp | Pll回路 |
US10014867B1 (en) * | 2016-12-28 | 2018-07-03 | AUCMOS Technologies USA, Inc. | Low-jitter phase-locked loop circuit |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03136522A (ja) | 1989-10-23 | 1991-06-11 | Mitsubishi Electric Corp | 位相同期回路 |
US5297231A (en) * | 1992-03-31 | 1994-03-22 | Compaq Computer Corporation | Digital signal processor interface for computer system |
JP2778421B2 (ja) | 1993-09-07 | 1998-07-23 | 日本電気株式会社 | チャージポンプ型位相同期ループ |
JP2919321B2 (ja) | 1995-10-27 | 1999-07-12 | 埼玉日本電気株式会社 | Pllシンセサイザ |
JPH1168560A (ja) | 1997-08-20 | 1999-03-09 | Nec Corp | Pll周波数シンセサイザおよびチャージポンプ回路 |
US6040742A (en) * | 1997-09-02 | 2000-03-21 | Lucent Technologies Inc. | Charge-pump phase-locked loop with DC current source |
US6611160B1 (en) * | 2000-11-21 | 2003-08-26 | Skyworks Solutions, Inc. | Charge pump having reduced switching noise |
WO2003098807A1 (en) | 2002-05-22 | 2003-11-27 | Matsushita Electric Industrial Co.,Ltd. | Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit |
US6963232B2 (en) * | 2003-08-11 | 2005-11-08 | Rambus, Inc. | Compensator for leakage through loop filter capacitors in phase-locked loops |
JP2005094427A (ja) | 2003-09-18 | 2005-04-07 | Renesas Technology Corp | 通信用半導体集積回路 |
JP2005167536A (ja) | 2003-12-02 | 2005-06-23 | Renesas Technology Corp | 通信用半導体集積回路および無線通信システム |
US7015735B2 (en) | 2003-12-19 | 2006-03-21 | Renesas Technology Corp. | Semiconductor integrated circuit having built-in PLL circuit |
TWI233265B (en) * | 2004-06-18 | 2005-05-21 | Via Tech Inc | Phase locked loop circuit |
US7427900B2 (en) * | 2004-12-30 | 2008-09-23 | Silicon Laboratories Inc. | Integrated PLL loop filter and charge pump |
-
2005
- 2005-09-30 JP JP2005289043A patent/JP4327144B2/ja not_active Expired - Fee Related
- 2005-12-28 US US11/318,608 patent/US7782144B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7782144B2 (en) | 2010-08-24 |
JP2007104132A (ja) | 2007-04-19 |
US20070075788A1 (en) | 2007-04-05 |
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